JPH04192056A - Arbitration system - Google Patents

Abstract

PURPOSE:To shorten the waiting time required to other master processors to acquire the bus using right by asserting a bus request inhibit signal to an arbitration circuit from an access control circuit in a retry mode. CONSTITUTION:When a certain master processor asserts a bus request signal, an arbitration circuit 14 asserts a bus acquiring signal. Then the master processor starts an access to a bus. An access control circuit 15 decodes an access address to recognize a slave memory 16 and asserts a retry signal to the master processor. The master processor recognizes a retry cycle and interrupts the access to the bus. The circuit 15 asserts a bus request inhibit, signal to the circuit 14. The master processor where the bus request inhibit signal is asserted does not accept a request signal if asserted before an answer is received from the memory 16. Thus it is possible to shorten the waiting time required to other master processors to acquire the bus using right. Then the processing efficiency is improved in an arbitration system.

Description

Detailed Description of the Invention [Summary] Regarding an arbitration method for controlling the order of bus acquisition in a co-multiprocessor device, an arbitration method is proposed that improves processing efficiency by reducing the waiting time for other master processors to acquire a bus. In an arbitration method that controls the order in which a plurality of master processors acquire a bus and controls access to a slave memory, the bus acquisition signal is asserted in response to input of a bus request signal from the master processor, and access control is performed. an arbitration circuit that negates the bus acquisition signal in response to a bus request inhibit signal from a circuit; an arbitration circuit that decodes an access address from the master processor to the slave memory and outputs a retry signal to the master processor; The circuit also includes an access control circuit that negates the bus request inhibit signal in response to a response from the slave memory, and is configured to inhibit the bus request signal during a retry cycle.

[Industrial Field of Application] The present invention relates to an arbitration method for controlling the order of bus acquisition in a multiprocessor device.

In the arbitration method, which includes an arbitration circuit that controls the order in which multiple master processors acquire the bus, and an access control circuit that controls the master processor's access to the slave memory, the arbitration method that controls the master processor's bus occupancy right It is desirable to allow other master processors to access the slave memory even during the retry cycle that occurs, thereby reducing the waiting time of other master processors.

[Prior Art] Examples of conventional arbitration methods include the following.

That is, when a master processor asserts a bus request signal to the arbitration circuit at the rising edge of a clock, the arbitration circuit asserts a bus acquisition signal in response to this request.

When the bus acquisition signal is asserted, the master processor negates the bus request signal and begins accessing the bus. The access control circuit decodes this access address of the master processor and asserts a retry signal to the master processor. The master processor to which the retry signal has been asserted suspends access to the bus during the retry cycle, and again asserts the bus request signal to the arbitration circuit.

When the arbitration circuit recognizes the re-asserted bus request signal, it asserts the bus acquisition signal to the master processor again if no other mask is accessing the bus, and if there is no response from the slave memory, it issues the retry signal again. Assert.

[Problems to be Solved by the Invention] However, in such a conventional arbitration method, after a master processor receives a retry signal, it asserts the bus request signal again to acquire the bus. Since the operation is repeated many times until a response is returned from the slave memory, problems arise such as unnecessary access to the bus and waiting time for other masks to acquire the bus.

The present invention has been made in view of such conventional problems, and provides an arbitration method that improves processing efficiency by reducing the bus acquisition waiting time of other master processors. It is an object.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 11-13 are a plurality of master processors, 16 is a slave memory accessed by the master processors 11-13, and 14 is the master processor 11-13.
an arbitration circuit that asserts a bus acquisition signal in response to input of a bus request signal from the access control circuit 15 and negates the bus acquisition signal in response to a bus request inhibit signal from the access control circuit 15; decodes the access address to the master processor 11-1 and sends a retry signal to the master processor 11-1.
3 and also outputs a bus request inhibit signal to the arbitration circuit 14, and negates the bus request inhibit signal in response to a response from the slave memory 16.

[Operation] In the present invention, when a certain master processor asserts a bus request signal to the arbitration circuit,
The arbitration circuit asserts the bus acquisition signal;
As a result, the master processor negates the bus request signal and starts accessing the bus. The access control circuit decodes this access address, recognizes the slave memory, and asserts a retry signal to the master processor.

The master processor recognizes the retry cycle and suspends access to the bus, while the access control circuit asserts a bus request inhibit signal to the arbitration circuit.

Even if the master processor to which the bus request inhibit signal is asserted asserts the bus request signal until a response is returned from the slave memory, the bus request signal will not be accepted by the arbitration circuit. On the other hand, while the bus request inhibit signal is asserted, bus request signals from other master processors are accepted by the arbitration circuit.

In this way, during a retry cycle of one master processor, the waiting time for other master processors to acquire a bus can be reduced. As a result, processing efficiency can be improved.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIGS. 2 to 4 are diagrams showing an embodiment of the present invention.

In FIG. 3, 11 to 13 are a plurality of master processors, 16 is a low-speed slave memory (slave memory) accessed by the master processors 11 to 13, 14 is an arbitration circuit that controls the bus acquisition order of the master processors 11 to 13, and 15 is an access control circuit that controls access to the low-speed slave memory 16 by the master processors 11 to 13.

These master processors 11 to 13, low speed slave memory 16, arbitration circuit 14, and access control circuit 15 are connected to each other via a bus 17. Note that the arbitration circuit 14 has the following priorities:
For example, master processor 11>master processor 12>
Control is performed so that it becomes the master processor 13.

Next, the configurations of the arbitration circuit 14 and the access control circuit 15 are shown in FIG.

In FIG. 2, 14A indicates a P1 bus request signal from the master processor 11 and a P1 bus request signal from the access control circuit 15.
14B is an AND circuit to which the P2/< bus request signal from the master processor 12 and the P2 bus request suppression bone from the access control circuit 15 are input; 14C is the AND circuit to which the P2 bus request suppression bone is input from the master processor 13 The P3 bus request signal from the P3 bus request signal and the P3 bus request signal from the access control circuit 15
These are AND circuits to which the 3-bus request inhibition signal is input, and the outputs of these AND circuits 14A to 14C are input to flip-flops 14D to 14F, respectively.

Flip-flop 14D outputs a P1 bus acquisition signal to master processor 11 and access control circuit 15, flip-flop 14E outputs a P2 bus acquisition signal to master processor 12 and access control circuit 15, and flip-flop 14F outputs a P1 bus acquisition signal to master processor 11 and access control circuit 15. The acquisition signal is output to master processor 13 and access control circuit 15.

That is, when the P1 to P3 bus request signals go to H level, the P1 to P3 bus acquisition signals are
When the bus request inhibit signal goes to L level, the P1 to P3 bus request signals are negated and the P1 to P3 bus acquisition signals are not activated.

15B is an address decoding unit that decodes the access address that the master processors 11 to 13 output to the bus 17 using the P1 to P3 bus acquisition signal acquirer, and the address decoding unit 15B outputs the decoded signal to the access control unit 1.
Output to 5A. The access control unit 15A controls the low-speed slave memory 16 based on the signal from the address decoding unit 15B.
, and outputs a retry signal to the corresponding master processors 11 to 13 using the P1 to P3 acquisition signals, and outputs a P1 to P3 bus request suppression signal (L level) to the arbitration circuit 14.

The access control unit 15A also controls the low-speed slave memory 1
When there is a response from 6, the bus request suppression signal of P1 to P3 to the arbitration circuit 14 is negated (H
level).

Next, the operation will be explained based on the time chart of FIG. Here, the master processor 11 will be explained as an example.

First, the master processor 11 inputs P1 at the rising edge of the clock.
The required amount of bus is asserted to the arbitration circuit 14 (see FIG. 4, ①).

The arbitration circuit 14 asserts the acquisition of the P1 bus to the master processor 11 and the access control circuit 15 according to the required amount of the P1 bus of the master processor 11 (see FIG. 4, (2)).

When the P1 bus acquisition request is asserted, the master processor 11 negates the required amount of the P1 bus (see FIG. 4, ■) and starts accessing the low-speed slave memory 16 (see FIG. 4, ■).

When access to the low-speed slave memory 16 is started,
The access control circuit 15 decodes the access address from the master processor 11 and transfers it to the low-speed slave memory 16.
It recognizes this and asserts a retry signal to the master processor 11 (see FIG. 4, ①).

The master processor 11 to which the retry signal has been asserted recognizes that it is a retry cycle, and interrupts access to the bus 17 (see FIG. 4, (2)).

Further, the access control circuit 15 asserts the read and write signals to the master processor 11, and also asserts the P1 bus request inhibition signal to the arbitration circuit 14 (see FIG. 4, (2)).

The master processor 11, which has asserted the P1 bus request suppression bone, waits until a response is returned from the low-speed slave memory 16 (see FIG. 4, ■), even if it asserts the P1 bus request amount again (see FIG. 4, (see (2)) is not accepted by the arbitration circuit 14. That is, the master processor 11 cannot obtain the P1 bus acquisition bone.

On the other hand, during the period A in which the P1 bus request suppression bone is asserted, P2.
The required P3 bus amount is accepted by the arbitration circuit 14. Therefore, other master processors 12.13
can reduce the waiting time for bus acquisition.

Next, when a response is returned from the low-speed slave memory 16 (see Figure 4, ■), the P1 bus request suppression bone is negated (see Figure 4, ■), and the P1 bus request amount becomes valid (see Figure 4, ■). (see FIG. 4, 0), the P1 bass acquisition bone is asserted (see FIG. 4, 11).

When the P1 bus acquisition bone is asserted (see FIG. 4, 11), the master processor 11 transfers the low-speed slave memory 16
can be accessed. In this case, since the response is returned from the low-speed slave memory 16 (Fig. 4,
), the retry signal is not asserted.

In this way, during retry, other master processor 1
P2 from 2.13. The required amount of P3 bus is accepted by the arbitration circuit 14, and the amount requested by other master processors 1 is
2.13 bus acquisition waiting time can be reduced.

As a result, processing efficiency can be improved.

[Effects of the Invention] As described above, according to the present invention, the bus request signal is inhibited by asserting the bus request inhibit signal from the access control circuit to the arbitration circuit during retry. The waiting time for bus acquisition by other master processors can be reduced, and as a result, processing efficiency can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is an overall configuration diagram, and FIG. 4 is a time chart. In the figure, 11-13... Master processor, 14... Arbitration circuit, 14A-14C... AND circuit, 14D-14F... Flip-flop, 15... Access control circuit, 15A... Address Decoding section, 1-5B... Access control section, 16... Low speed slave memory (slave memory),
17...Bus.

Claims (1)

[Scope of Claims] In an arbitration method that controls the order of bus acquisition by a plurality of master processors (11 to 13) and controls access to a slave memory (16), a bus request signal from the master processors (11 to 13) is provided. The bus acquisition signal is asserted by the input of the access control circuit (15).
), an arbitration circuit (14) that negates the bus acquisition signal based on a bus request inhibit signal from the master processor (11 to 13), and an arbitration circuit (14) that decodes the access address to the slave memory (16) from the master processor (11 to 13) and sends a retry signal to the master processor. (11 to 13) and also outputs a bus request inhibition signal to the arbitration circuit (14), and also outputs a bus request inhibit signal to the arbitration circuit (14).
16) An arbitration method characterized by comprising an access control circuit (15) that negates the bus request inhibiting signal in response to a response from the bus requesting signal, and inhibiting the bus request signal during a retry cycle.