JPH04175941A

JPH04175941A - Method and device for controlling common memory

Info

Publication number: JPH04175941A
Application number: JP2304440A
Authority: JP
Inventors: Akira Hoshino; 星野　公
Original assignee: Fuji Electric Co Ltd; Fuji Facom Corp
Current assignee: Fuji Electric Co Ltd; Fuji Facom Corp
Priority date: 1990-11-09
Filing date: 1990-11-09
Publication date: 1992-06-23

Abstract

PURPOSE:To efficiently access the common memory which is accessed from plural CPUs by operating a memory control circuit with the same clock with an accessing CPU. CONSTITUTION:This device is equipped with the CPUs 1-1 - 1-n which operate with 1st individual operation clocks CLK1 - CLKn and the common memory 2 which can be accessed by the respective CPUs 1-1 - 1-n. Then the device is provided with a clock selecting circuit 4 which inputs access request signals REQ1 - REQn of the respective CPUs 1-1 - 1-n and the respective operation clocks CLK1 - CLKn and supplies the memory control circuit 3 with the operation clock CLK of a CPU selected by the memory control circuit 3 as an operation clock CLKX. Consequently, the memory 2 that the CPUs 1-1 - 1-n share is accessed with most efficiency matching the speeds of the CPUs.

Description

[Detailed description of the invention]

【産業上の利用分野１本発明は複数のＣＰＵからアクセスされる共有メモリ（
マルチボートメモリともいう）を効率よくアクセスする
ための共有メモリの制御方法およびその装置に関する。なお以下各図において同一の符号は同一もしくは相当部
分を示す。【従来の技術】第２図はこの種の共有メモリの制御回路の構成例を示す
。同図において、１　（１−１〜１−ｎ）はマイクロプ
ロセッサ（ＣＰＵとも記す）、２は共有メモリ（単にメ
モリともいう）、３はＣＰＵ　１〜１〜１−ｎとメモリ
２との間に設けられたメモリ制御回路である。ここで１−１〜１−ｎは異なるマイクロプロセンサ（Ｃ
ＰＵ）を示し、ＣＬ　Ｋ　（ＣＬＫＩ、ＣＬに２−−−
ＣＬｋｎ）は、各々ＣＰ　０１−１．　ＣＰ　Ｕｌ−２
・・ＣＰ　Ｕｌ−ｎに与えられる動作クロックである。この動作り０７りＣＬＫＩ、ＣＬＫ２・・ＣＬＫｎは多
くの場合、周波数がそれぞれ異なる。そのためＣＰ　Ｕ
ｌ−１，ＣＰ　Ｕｌ−２・・ＣＰ　Ｕｌ−ｎの動作速度
もそれぞれ異なる。メモリ制御回路３は各ＣＰＵＩからのメモリアクセスが
メモリ２上で衝突しないように調停する機能を持つ。ア
クセス要求信号ＲＥ　Ｑ　（ＲＥＱＩ、ＲＥＱ２゜−−
−−ＲＥＱｎ）は、それぞれＣＰ　Ｕ　１−１〜１−ｎ
が共有メモリ２をアクセスしようとする信号である。こ
こでメモリ制御回路３はアクセス要求信号ＲＥＱを出力
したＣＰＵＩの１つを予め定められた優先順位の決定方
法に従って選択し、その選択されたＣＰＵＩのアクセス
要求信号ＲＥＱを共有メモリ２に与え、該ＣＰＵＩが共
有メモリ２をアクセスできるようにする。このような構成では、動作の速いＣＰＵの性能を確保す
るため、メモリ制御回路３の動作クロックＣＬＫＸには
、各ＣＰＵの動作クロックＣＬＫＩ　。ＣＬＫ２・・・ＣＬＫｎのうち最も周波数の高いものを
用いることがある。[Industrial Application Field 1] The present invention is a shared memory accessed by multiple CPUs (
The present invention relates to a shared memory control method and device for efficiently accessing shared memory (also called multi-board memory). Note that in the following figures, the same reference numerals indicate the same or corresponding parts. 2. Description of the Related Art FIG. 2 shows an example of the configuration of a control circuit for this type of shared memory. In the figure, 1 (1-1 to 1-n) is a microprocessor (also referred to as CPU), 2 is a shared memory (also simply referred to as memory), and 3 is a link between CPUs 1 to 1 to 1-n and memory 2. This is a memory control circuit provided in the. Here, 1-1 to 1-n are different microprosensors (C
PU) and CL K (CLKI, CL to 2---
CLkn) are each CP 01-1. CP Ul-2
. . . An operating clock given to the CP Ul-n. During this operation, CLKI, CLK2, . . . CLKn often have different frequencies. Therefore, CPU
The operation speeds of CP Ul-1, CP Ul-2, . . . CP Ul-n are also different. The memory control circuit 3 has a function of arbitrating so that memory accesses from each CPUI do not conflict on the memory 2. Access request signal REQ (REQI, REQ2゜--
--REQn) are CPU 1-1 to 1-n, respectively.
is a signal that attempts to access shared memory 2. Here, the memory control circuit 3 selects one of the CPUIs that has outputted the access request signal REQ according to a predetermined priority determination method, provides the access request signal REQ of the selected CPUI to the shared memory 2, and sends the access request signal REQ of the selected CPUI to the shared memory 2. Allow the CPUI to access the shared memory 2. In such a configuration, in order to ensure the performance of a fast-operating CPU, the operating clock CLKX of the memory control circuit 3 is set to the operating clock CLKI of each CPU. The highest frequency among CLK2...CLKn may be used.

[Problem to be solved by the invention]

前述のようにメモリ制御回路３の動作クロックＣＬＫＸ
として、各ＣＰＵの動作クロック中の最高周波数のクロ
ックを用いた場合、制御回路３゜メモリ２とも最も高い
周波数で動作することが要求され、これらの部品が高価
となるが、この最も高い周波数で動作するＣＰＵＩの共
有メモリ２へのアクセス頻度が低い時には、高価な部品
が充分活用されないという問題が生じる。またＣＰＵ動
作クロりクＣＬＫＩ　、　ＣＬＫ２・・・ＣＬＫｎの内
から周波数の低いものを選ぶと、動作の速いＣＰＵには
、待ち時間が増え、ＣＰＵの性能低下が生じる。そこで本発明は複数ＣＰＵが共有するメモリを、そのＣ
ＰＵの速度に合わせて最も効率よくアクセスできるよう
にすることができる共有メモリの制御方法およびその装
置を提供することを課題とする。As mentioned above, the operation clock CLKX of the memory control circuit 3
If the highest frequency clock among the operating clocks of each CPU is used, both the control circuit 3 and the memory 2 are required to operate at the highest frequency, which makes these parts expensive. When the operating CPUI accesses the shared memory 2 infrequently, a problem arises in that expensive components are not fully utilized. Furthermore, if one of the CPU operation clocks CLKI, CLK2, . Therefore, the present invention provides memory that is shared by multiple CPUs.
An object of the present invention is to provide a shared memory control method and device that can provide the most efficient access in accordance with the speed of a PU.

[Means to solve the problem]

前記の課題を解決するために、請求項１）の制御方法は
「それぞれ個別の第１の動作クロック（ＣＬ　Ｋなど〕
で動作する複数のＣＰＵ　（１など）と、前記の各ＣＰＵによるアクセスが可能な共有メモリ（２
など）と、第２の動作クロック（ＣＬＫＸなと）で動作し、前記の
各ＣＰＵのアクセス要求信号（ＲＥ　Ｑなど）を入力し
、要求を出したＣＰＵの１つを選択し、該ＣＰＵの前記
アクセス要求信号を前記共有メモリに与えるメモリ制御
回路（３など）とを備えたシステムにおいて、前記第２の動作クロックを前記共有メモリにアクセスす
ることとなった前記ＣＰＵの第１の動作クロックに、こ
のアクセスのつど等しくするようにｊするものとし、ま
た請求項２）の制御装置は、ｒそれぞれ個別の第１の動作
クロック　（ＣＬＫなと）で動作する複数のＣＰＵ　（
１など）と、前記の各ＣＰＵによるアクセスが可能な共有メモリ（２
など）と、第２の動作クロック（ＣＬＫＸなど）で動作し、前記の
各ＣＰＵのアクセス要求信号（ＲＥＱなど）を入力し、
要求を出したＣＰＵの１つを選択し、該ＣＰＵの前記ア
クセス要求信号を前記共有メモリに与えるメモリ制御回
路（３など）とを備えたシステムにおいて、前記の各ＣＰＵからのアクセス要求信号と、この各Ｃ，
Ｐ、Ｕの前記第１の動作クロックとを人力し、前記メモ
リ制御回路によって選択されるＣＰＵについての第１の
動作クロックを前記第２の動作りロックとして前記メモ
リ制御回路に与える手段（クロック選択回路４など）を
備えたことを特徴とする共有メモリの制御回路。In order to solve the above-mentioned problem, the control method of claim 1) uses "separate first operating clocks (CLK, etc.)".
multiple CPUs (such as 1) that operate on a shared memory (2) that can be accessed by each of the CPUs.
etc.), operates with a second operating clock (CLKX etc.), inputs the access request signal (REQ, etc.) of each CPU mentioned above, selects one of the CPUs that issued the request, and In a system comprising a memory control circuit (such as 3) that provides the access request signal to the shared memory, the second operating clock is set to the first operating clock of the CPU that has accessed the shared memory. , so that the accesses are made equal each time, and the control device according to claim 2) includes a plurality of CPUs (r) each operating with an individual first operating clock (CLK).
1 etc.), and a shared memory (2
etc.), operates with a second operating clock (CLKX, etc.), and inputs the access request signal (REQ, etc.) of each of the CPUs,
A system comprising a memory control circuit (such as 3) that selects one of the CPUs that has issued a request and provides the access request signal of the CPU to the shared memory, the access request signal from each of the CPUs; Each of these C,
Means (clock selection) for manually inputting the first operating clocks of P and U and providing the first operating clock for the CPU selected by the memory control circuit to the memory control circuit as the second operating lock. A shared memory control circuit characterized by comprising a circuit (4, etc.).

[For use]

各ＣＰＵｌ−１〜ｌ−ｎのアクセス要求信号ＲＥＱ１〜
ＲＥＱｎと各動作クロックＣＬＫ１〜ＣＬＫｎとを入力
し、メモリ制御回路３によって選択されるＣＰＵについ
ての動作クロックＣＬＫをメモリ制御回路３に対し動作
クロックＣＬＫＸとして与えるクロック選択回路４を設
ける。Access request signals REQ1 to each CPU l-1 to l-n
A clock selection circuit 4 is provided which inputs REQn and each of the operating clocks CLK1 to CLKn and provides the operating clock CLK for a CPU selected by the memory control circuit 3 to the memory control circuit 3 as an operating clock CLKX.

【Example】

第１図は本発明の実施例としての構成を示すブロック回
路図で、第２図に対応するものである。第１図においては、メモリ制御回路３に入力する動作ク
ロックＣＬＫＸを各ＣＰ　Ｕ　１−１〜１−ｎのクロッ
クＣＬＫＩ〜ＣＬ　Ｋｎから選択できるようにクロック
選択回路４を新たに設けた。即ち各ＣＰＵ１−１〜１−
ｎからのアクセス要求信号ＲＥＱＩ〜ＲＥＱｎおよび動
作クロックＣＬＫ１〜ＣＬＫｎは、このクロック選択回
路４に人力されるように構成されており、クロック選択
回路４は、アクセス要求信号ＲＥＱを出力したＣ　Ｐ　
０１のうちメモリ制御回路３によって選択されるべきＣ
Ｐ　Ｕｌの動作クロックＣＬＫを選択し、動作クロック
ＣＬＫＸとしてメモリ制御回路３に入力する。FIG. 1 is a block circuit diagram showing the configuration of an embodiment of the present invention, and corresponds to FIG. 2. In FIG. In FIG. 1, a clock selection circuit 4 is newly provided so that the operating clock CLKX input to the memory control circuit 3 can be selected from among the clocks CLKI to CL Kn of each of the CPUs 1-1 to 1-n. That is, each CPU1-1 to 1-
The access request signals REQI to REQn and the operation clocks CLK1 to CLKn from the clock selection circuit 4 are configured to be manually inputted to the clock selection circuit 4, and the clock selection circuit 4 is configured to input the access request signals REQI to REQn and the operation clocks CLK1 to CLKn from the clock selection circuit 4, which outputs the access request signal REQ.
01 to be selected by the memory control circuit 3
The operating clock CLK of P Ul is selected and input to the memory control circuit 3 as the operating clock CLKX.

【Effect of the invention】

本発明によれば、各ＣＰＵｌ−１〜１−ｎからのアクセ
ス要求信号ＲＥＱ１〜ＲＥＱｎを、クロック選択回路４
に入力し、クロック選択回路４がこの要求ＲＥＱを出し
たＣＰＵＩの動作クロックＣＬＫを選択してメモリ制御
回路３に与えるようにしたので、メモリ制御回路３はア
クセスしたＣＰＵ１　と同一のクロックで動作すること
ができる。そのため、高速のＣＰＵの不要な待ち時間やメモリ制御
回路３および共有メモリ２の常時の過度の高速動作をな
くすことができる。According to the present invention, the access request signals REQ1 to REQn from each CPU1-1 to 1-n are sent to the clock selection circuit 4.
Since the clock selection circuit 4 selects the operating clock CLK of the CPU that issued this request REQ and supplies it to the memory control circuit 3, the memory control circuit 3 operates with the same clock as the accessed CPU1. be able to. Therefore, unnecessary waiting time of the high-speed CPU and constant excessively high-speed operation of the memory control circuit 3 and shared memory 2 can be eliminated.

[Brief explanation of drawings]

第１図は本発明の実施例としての構成を示すブロック回
路図、第２図は第１図に対応する従来の回路図である。１　（１−１〜１−ｎ）　：　ＣＰ　Ｕ、２：共有メモ
リ、３゜メモリ制御回路、４：クロツタ選択回路、ＣＬ
Ｋ（ＣＬＫＩ　〜ＣＬＫｎ）、ＣＬＫＸ　：動作りｏ　
７り、ＲＥＱ　（ＲＥＱＩ　〜ＲＥＱｎ）：アクセス要
求信号。動ｆ乍クロ・、り、ｔｌＦＡFIG. 1 is a block circuit diagram showing a configuration as an embodiment of the present invention, and FIG. 2 is a conventional circuit diagram corresponding to FIG. 1. 1 (1-1 to 1-n): CPU, 2: Shared memory, 3° memory control circuit, 4: Crochet selection circuit, CL
K (CLKI ~ CLKn), CLKX: Operation o
7. REQ (REQI to REQn): Access request signal. Dynamic f 乍 Kuro, Ri, tlFA

Claims

[Scope of Claims] 1) A plurality of CPUs that each operate with an individual first operating clock, a shared memory that can be accessed by each of the CPUs, and a shared memory that operates with a second operating clock and that each of the CPUs a memory control circuit that inputs an access request signal of the CPU, selects one of the CPUs that has issued the request, and provides the access request signal of the CPU to the shared memory, A method for controlling a shared memory, characterized in that the first operating clock of the CPU that accesses the shared memory is made equal to the first operating clock of the CPU each time the access is made. 2) A plurality of CPUs that each operate with an individual first operating clock, a shared memory that can be accessed by each of the CPUs, and a shared memory that operates with a second operating clock and receives access request signals from each of the CPUs. and a memory control circuit that selects one of the CPUs that has issued a request and provides the access request signal of the CPU to the shared memory, C.P.
and means for inputting the first operating clock of the CPU selected by the memory control circuit to the memory control circuit as the second operating clock. shared memory control circuit.