JPH04170829A - Data communication method between on-vehicle computers - Google Patents

Abstract

PURPOSE:To recognize data due to abnormality caused in the computer of a communicating destination, and to correctly discriminate the effectiveness of the data so as to improve reliability by discriminating whether the received value of first data is effective or not by comparing the inverted value of all the bits of the received value of second data with the received value of the first data. CONSTITUTION:A main computer 1a transmits the same data including a command by bytes from a first byte to a second byte, and on the other hand, a sub computer 1b returns read-out data (first data) by a second byte, and further, it returns the inverted value (second data) of all the bits of this read-out data by the third byte. The main computer 1a compares the received value of the second byte from the sub computer 1b with the inverted value of all the bits of the received value of the third byte, and discriminates whether the received read-out data is normal or not by checking the coincidence of these data. Thus, the data due to the abnormality caused in the computer of the communicating destination can be recognized, and the effectiveness of the data can be correctly discriminated, and the reliability of communication can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of data communication between onboard computers coupled by a serial channel.

[Prior Art] In recent years, many vehicles such as automobiles are equipped with multiple computers.
Publication No. 9154 includes No. 1. A technique is disclosed that includes a second microcomputer and divides the processing of a plurality of types of control items.

Furthermore, in distributed processing using multiple computers, each computer is connected by a serial channel and the data required by each other is serially transmitted. For this serial data transmission, a clock synchronization method is adopted and bidirectional communication is possible. There are many things to do.

In this case, in data communication between each computer,
A method is adopted in which data is received twice, each received data is compared, and if they match, the data is considered valid, thereby ensuring the reliability of the communication data.

[Problems to be Solved by the Invention] However, in clock-synchronous bidirectional communication, transmission and reception are performed simultaneously, so the communication interface of each computer is not equipped with a transmission/reception buffer that serves both transmission and reception. In many cases, in the method described above, if data is sent from computer A, for example,
When a camp occurs on the other party's computer B, this computer B cannot set the reply value in the sending/receiving buffer, and the data stored in this sending/receiving buffer is echoed back to computer A in the next sending/receiving cycle.
will be replied to.

Therefore, as a matter of course, the received value twice becomes the same data in computer A, and the above-described method cannot detect an abnormality in computer B, and there is a possibility that the returned value will be regarded as valid data.

[Object of the Invention] The present invention has been made in view of the above circumstances, and it is an object of the present invention to recognize data due to an abnormality occurring in a communication destination computer, accurately determine the validity of the data, and improve the reliability of communication. The purpose of this research is to provide a data communication method between in-vehicle computers that enables the following.

[Means and operations for solving the problem] To achieve the above object, the present invention provides a data communication method between on-vehicle computers connected via a serial channel. 1 data and second data obtained by inverting all bits of the first data, and combining the received value of the second data with all bits inverted and the received value of the first data. By comparing, it is determined whether the received value of the first data is valid.

Examples of the invention] Hereinafter, the present invention will be described in detail with reference to the drawings.

The drawings show one embodiment of the present invention; FIG. 1 is a flowchart showing the communication procedure of the main computer, FIG. 2 is a flowchart showing the communication procedure of the subcomputer, FIG. 3 is a circuit block diagram of the control device, and FIG. FIG. 5 is an explanatory diagram showing a transmission/reception buffer, FIG. 5 is a time chart of clock synchronous communication, and FIG. 6 is an explanatory diagram showing the configuration of a communication block.

In FIG. 3, reference numeral 1 is a control device (ECTJ) mounted on a vehicle such as an automobile, and this ECU1 has two built-in microcomputers, a main computer 1a and a subcomputer 1b, and a drive circuit 1c. It has built-in peripheral circuits such as

The main computer 1a has, for example, an 8-bit main CPUIO 1ROMI 1. RAMI 2, I10 interface 13, serial interface (SC
(2) 14 and a timer 15 are connected via a pass line 16, and the subcomputer 1b includes, for example, an 8-bit sub CPU 20, ROM 21, RAM 22,
An I10 interface 23, a serial interface (SCI') 24, and a timer 25 are connected via a pass line 26.

At the I10 interface 13 of the main computer 1a, sensors and switches 30 for detecting operating conditions are connected to the input boat, and actuators 31 such as injectors and ignition coils are connected to the output boat via the drive circuit 1c. On the other hand, at the I10 interface 23 of the subcomputer 1b, a knock sensor 32 is connected to the input port.

The ROM II stores engine control programs such as fuel injection control and ignition timing control, a communication program for data communication with the subcomputer 1b, and fixed control data, while the ROM 21 stores engine control programs such as fuel injection control and ignition timing control. , a knock detection processing program, and a communication program for data communication with the main computer 1a are stored.

At the time of system startup, the main CPU 10 transfers fixed data such as an ignition timing map to the subcomputer 1b via the 5C 114, and then adjusts the ignition timing and fuel injection based on the engine operating state parameters from the sensors and switches 30. The pulse width etc. are calculated and output to the actuators 31, and the subcomputer 1
Sends engine control information such as ignition timing to b.

In the sub CPU 20, the main computer 1a
50124, processes the signal from the knock sensor 32, and sends it to the main computer 1a. As a result, when knock occurs, the main computer 1a retards the ignition timing to eliminate the knock and always controls the engine in an appropriate state.

The 5Cs 114 and 24 are connected to each other through the lines of the clock signal CLK, the transmission signal TX, and the reception signal RX, and as shown in FIG. It is loaded into each CPU10, 20 at the timing of
The data written from l0, 20 is transmitted at a predetermined timing.

That is, the data received by the transmitting/receiving buffer 40 is sequentially stored as serial data of 1 bit per pulse in synchronization with the clock signal CLK, and when 8 bits of data is accumulated, 1 byte is stored in each CPU 10.20. 0 is taken in as parallel data for each CPU1
From 0.20 onwards, 1 byte of reply data is written into the transmission/reception buffer 40, and is transmitted as serial data at the next transmission/reception timing.

At this time, the clock signal CLK is supplied from the timer 15 of the main computer 1a, and the main CPU
Clock synchronous full-duplex bidirectional communication is performed between l0 and the sub CPU 20, and as shown in FIG. 5, each bit from LSB (bit O) to MSB (bit 7) of communication data DATA is is strobed at the rising timing of the clock signal CLK.

Next, each computer la in the ECUI.

The communication procedure between 1b will be explained.

In data communication between the main computer 1a and the subcomputer 1b, as shown in FIG.
AI, DATA2. One block is 3 bytes of data consisting of DATA3, and the cycle is T (for example, T=4
ms) byte cycle communication is performed, and this one block of communication block TXB is followed by a blank section T BLAN in a non-communication state.
The first byte data D, which is the first data, is set by BLANK.
Detect ATAI.

In this head data, the command CON instructing the communication mode is indicated by the upper two bits, and this command CON has, for example, the following system.

01...Write mode (writing data from the main computer 1a to the subcomputer 1b) 10...Read mode (reading data from the subcomputer 1b to the main computer 1a) 11...Base address mode (writing the base address to be described later) Setting) Data communication after the second byte is started when a communicable code is returned from the subcomputer 1b at the timing of the first byte data communication, and operates as follows according to each mode.

(Write mode and base address mode) When the main computer 1a sends the second byte of write data, the value received from the subcomputer 1b as the first byte is returned. In the main computer 1a, the first
Subcomputer 1b with byte transmission value and second byte
By matching the response value from the subcomputer 1b, it is possible to check whether the first byte transmission value was received normally by the subcomputer 1b, and when the communication is normal, the third byte transmission value is
The data is the same as the byte transmission value, and when communication is abnormal, the third byte transmission value is transmitted as check data with all bits of the second byte transmission value inverted.

On the other hand, the subcomputer 1b can determine whether the received values from the first byte to the third byte are normal or not by matching the second byte received value and the third byte received value, and in the case of an abnormality, stops writing the received data.

(Read mode) The main computer 1a transmits the same data including the command CON from the first byte to the third byte, while the subcomputer 1b returns read data (first data) in the second byte. , Furthermore, a value (second data) obtained by inverting all bits of this read data is returned in the third byte.

In the main computer 1a, all bits of the second byte received value (first data received value) from the subcomputer 1b and the third byte received value (second data received value) from the subcomputer 1b are inverted. By comparing the values and matching these data, the subcomputer 1
It can be determined whether the read data received from b is normal or not.

Hereinafter, the communication procedure of each computer 1a, 1b will be specifically explained according to the flowcharts of FIGS. 1 and 2.

(Communication procedure of main computer 1a) The flowchart in FIG.
This is a multi-selection step that branches conditionally. In other words, the count value MC of the transmission counter increases from O to 1.2.3 in response to communication for each byte.
Step 5101 to step 3102 according to M
．． 3104.5113.5124, respectively.

First, when the count value MCNT of the transmission counter is "0°" in the above step 5IO1, it is a communication blank interval T BLANK, and the above step 5101 branches to step 5102 to set the communication mode, and then step Proceed to 5703 and set the transmission counter to rv'1cNT4-MCN+1>,
Get out of the routine.

Then, the next routine is started and step 5101
If the count value MCNT of the transmission counter is 1'' and the first data is being transmitted, steps 5101 to 5 are executed.
Branching to step 104, the previously established mode is determined, and if the base address setting mode is the step 5104 to step 5105, if the write mode is the step 5104 to step 8106, if the read mode is the step 5.
The process branches from step 104 to step 5107.

First, let me explain the base address setting mode.
In this base address setting mode, step 5
In step 105, set the 2 bits of the command C as the upper one, and set 1 byte of data, which is the sum of the upper 2 bits, the base address ADB, and the lower 6 bits of the command AD BASE/L, to the transmission data TXDATA. ^←c
OH+AD BASE/L), step 810
Proceed to step 8.

The above base address A D BASE is the sub CPU2
This is the reference address in advance when specifying the address for the 0 memory space, and after the setting of the base address ADBASE, an offset address of less than 1 byte A D 0
Specify only FFSET and set the actual physical address to base address A D BASE and offset address A'
By specifying the logical sum with D0FFSET, the number of communication bytes can be reduced.

That is, if the subcomputer 1b has 8 bits, its address is empty m! Specifying 64 Kbytes (0000 to FFFF in hexadecimal) usually requires 2 bytes of data, but the above base address AD BA
Once SE is set, a physical address can be specified with a logical address using an offset address value of less than 1 byte A D 0FFSET, which reduces the number of communication bytes and improves the efficiency of data transfer. It is.

On the other hand, when the write mode is selected in step 5104, in step 3106, 1 byte of data obtained by adding the offset address ADOFFSET (6 bits) to the 2 bits of the command C is set as the transmission data TXDATA (TXDATA = COH + ADOFFSET).
) Proceeding to step 8108, when in read mode, similarly, in step 5107, 1 byte of data obtained by adding the offset address AD0FFSET (6 bits) to the 2 bits of the command COH is sent as the transmission data TXD.
Please set it to ATA TXDATA 4-COH+ A
D 0FFSET) - Proceed to Stella 73108.

And each step 3105.5106.5107 above
Proceeding to step 5ioa, the transmission data T
TA as the first byte data DATA1 (DATA1
←T
Step 5110
Proceed to.

In step 5110, the data received from the subcomputer 1b in step 5109 is checked, and when the upper two bits of this data are "00", the subcomputer 1b determines that it is in a communicable state and proceeds to step 5111 to transmit. Count up the counter (MCN ding ← M
CNT+1) Pass through 7 retin.

On the other hand, when the upper two bits of the data from the subcomputer 1b are "11" in step 5110, the subcomputer 1b determines that communication is not possible and performs step 511.
Branch to 2, clear the transmission counter (MCNT-0
) The routine is exited, the next cycle is left blank, and data communication starts again from the first byte.

Next, the routine is started again, and when the count value M CNT of the transmission counter is "2" in step 5101, that is, when the second byte data DATA2 is being communicated, a mode determination is performed in step 5113, and when the base address setting mode is set, Step 5113 to step 5114
Go to and reset the upper byte of the base address AD BASE/U to the transmission data TxDATA (TXDATA = AD BASE/U),
Stellaf S116A, proceed.

Further, when the light mode is selected in step 5113, the process proceeds from step 5113 to step 5115,
TXDATA 4-WDA Set the write data W DATA to be written to the memory of the subcomputer 1b whose address has already been specified to the transmission data T XDATA.
TA), proceed to step 8116.

Then, step 5114 or step 511
5 to step 8116, the transmission data T
ATA as second byte data DATA2 (DAT
A2←TXDATA) RAMI 2 (7) Work f
f-! J74 varnish) 7L, in step 5117 it is sent to the subcomputer 1b, and the subcomputer 1
Receive 1 byte of reply data from b and step 311
Proceed to step 8.

In step 8118, the data RXDATA received from the subcomputer 1b in step 5117 is changed to the first byte data D that has already been sent to the subcomputer 1b.
Check whether it matches ATAI or not, RXDATA=O
When AT^1, it is determined that the communication was executed normally and jumps from step 8118 to step 5123, and when RXDATA≠DATAI in step 5118, the communication is not carried out normally and the correct data is received by the subcomputer 1b. If it is determined that the error flag has not been received, the program proceeds from step 3118 to step 5119 to set the error flag FLAG1 (FLAG1←1), proceeds to step 5123 to increment the transmission counter (MCNT+1), and exits the routine.

That is, the first data, which is the first data of the communication block TXB,
When the byte data DATAI is transmitted from the main computer 1a, at the same time, the subcomputer 1b replies to the main computer 1a with a code indicating whether or not it is receivable, and if communication is possible, the second byte data DAT
A2 is transmitted from the main computer 1a according to the communication mode. The subcomputer 1b receives the first byte data DATA1 from the main computer 1a,
2nd byte data DAT from main computer 1a
Since the reply is sent at the transmission timing of A2, the main computer 1a determines whether the communication is executed normally depending on whether the first byte data DATA1 stored in the work area of the RAM 12 matches the received data RXDATA from the subcomputer 1b. It is possible to determine whether or not the

On the other hand, if the read mode is selected in the above step 5113, the process proceeds from the above step 5113 to step 5120, and the offset address AD is set to 2 bits of the command COH.
0FFSET (6 bits) plus 1 byte of data is sent as data T
)--In step 5121, transmission and reception with the subcomputer 1b is executed.

In this read mode, the second byte of transmission data T
2, the received data RXDATA is used as the second byte data DATA2 and the RAM 12 work area J7G varnish)7
L (DATA2 ←RXDATA), x step 5
123 to count up the transmission counter (MCNT
4-MCNT+1) Exit the routine.

Furthermore, in the next communication routine, step 3101
When the count value MCNT of the transmission counter is "3", that is, when the third byte data DATA3 is being transmitted, the mode is determined at step 5124, and when the base address setting mode is set, the steps from step 5124 to step 512 are performed.
Proceed to step 5 and set the upper byte A D BASE/U of the base address A D BASE to the transmission data TXD^■^ again (TXDATA 4-A D BASE/
U) Proceed to STELLA 7S127, and when in the Lye I mode, proceed from Step 5124 to Step 8126 and send the Lye data W DATA to the transmission data T XDAT.
A Set 4m again T XDATA←WDATA
), proceed to Step 5127.

In step 5127, it is determined based on the value of the error flag FLAG1 whether communication was performed normally last time, and F
When LAG1=O, that is, communication has been executed normally, step 5129 is performed and the subcomputer 1b
When FLAGl = 1, that is, there is an abnormality in communication, the process proceeds from STELLA 7S127 to step 3128, inverts all bits of the transmission data TXDATA, and in step 5129 executes transmission and reception to the subcomputer 1b. In other words, if the data communication up to the second byte is executed normally, the third byte data DATA3 transmits the same data as the second byte data DATA2, and if the communication is abnormal, the third byte data DATA3 transmits the same data as the second byte data DATA2. Data obtained by inverting all bits of the byte data DATA2 is transmitted.

Next, when the process proceeds from step 5129 to step 3130, the data RX received from the subcomputer 1b is
It is determined whether the communication was performed normally or not based on whether or not DATA matches the second byte data DATA2 sent to the subcomputer 1b.

If the communication is performed normally, the subcomputer 1b returns the same data as the already transmitted second byte data DATA2.
When DATA = DATA2, it can be determined that communication of 3 bytes of data has been executed normally, and step 5 above is performed.
The program jumps from step 130 to step 5137, clears the transmission counter (MCNT←0), and exits the routine.

Also, in step 5130 above, RXDA Ding A≠DA Ding A
At step 2, there is an abnormality in communication, so step 51 is performed.
30, proceed to step 5131 and set the error flag FLA.
Set G2 FLAG2←1), step 513
At step 7, clear the transmission counter (MCNT←0) and exit the routine.

On the other hand, if the read mode is selected in step 5124, the process proceeds from step 5124 to step 5132, where the offset address AD is set to 2 bits of the command COH.
Set 0FFSET (6 bits) plus 1 byte of data to the transmit data T
1ATA←CO)! + A D 0FFSET), this transmission data T XDATA is transmitted to the subcomputer 1b in step 5133, and 1 byte of return data is received from the subcomputer 1b.

Next, when the process proceeds from step 5133 to step 5134, the data RX received from the subcomputer 1b is
It is determined whether the value RXl)ATA obtained by inverting all bits of DATA matches the second byte data DATA2 already received from the subcomputer 1b.

In other words, since the third byte of return data from the subcomputer 1b is a value obtained by inverting all the bits of the second byte of return data, all bits of the value RX0ATA received from this third byte of return data The validity of the data can be determined by inverting it and comparing it with the second byte data 1) ATA2.

Therefore, an abnormality occurs in the subcomputer 1b, and the SCI
If regular reply data is not set in the sending/receiving buffer 40 of the main computer 1a, if the validity of the data is determined by simply matching two consecutive received data as in the past, the data sent from the main computer 1a (command CO
Offset address A D 0FFSE in 2 bits of H
The data obtained by adding 6 bits of T) is obtained in step 5121 above.
However, according to the present invention, it is possible to correctly recognize an abnormality in the subcomputer 1b and accurately determine the validity of the data, greatly improving reliability. It is possible to improve.

And the above Stella 75134 RXDATA = D
In the case of ArA2, communication is occurring normally, so
Proceeding from step 5134 to step 5135, the value RXDATA obtained by inverting all bits of the data RXDATA received from the subcomputer 1b (or the second byte data DATA2 already stored in the work area of the RAM 22) is stored in the RAM 12 as final data.
The process proceeds to step 5137, clears the transmission counter (MCNT-0), and exits the routine.

On the other hand, the above Stella 75134 RXDATA-#D
If ATA2 (7), there is an abnormality in communication, so proceed from step 5134 to step 8136 and set the error flag FLAG2. FLAG2 = 1
) - Clear the Stellar 75137 transmission counter (MCNT←0) and exit the routine.

Note that the error flags FLAGI and FLAG2 are cleared by performing an error check in a separate routine.

(Communication Procedure of Subcomputer 1b) On the other hand, in the subcomputer 1b, the communication routine shown in FIG. TR←reception interval), then
This time variable TR and set value T SET are set in step 52.
Compare with 02.

This setting value TSET is the byte cycle period T (for example, T-4113) in communication of one block of data.
The blank interval T between communication blocks TXB is longer than
A value that can identify BLANK (for example, TSET=61S
), and in step 5202 above, TR>
When TSET, the reception interval is longer than the period T of the normal byte cycle, and it can be determined that the first data reception is the first data reception after passing through the blank interval T BLAN, and in step 5203, the reception counter is set. Clear the count value 5CNT ( S CNT
←0).

At this time, at the timing of transmitting the first data from the main computer 1a, the reception permission code SC, which will be described later, is
The main computer 1a is notified of whether or not the subcomputer lb is communicable, and when the subcomputer lb is communicable, data communication from the second byte onwards with the main computer 1a is started.

Then, when the process proceeds from step 5203 to step 5204, the upper 2 bits (RX
DATA)87B6, that is, the command COH is interpreted, and when (RXDATA)87B6=11, that is, the command COH instructing the base address mode, the process proceeds from step 5204 to step 3205, sets the base address mode, and proceeds to step 5207. , <RXDATA)87B6=01, that is, when the command COH instructs the write mode, the process proceeds from step 5204 to step 8206, sets the write mode, and proceeds to step 5207.

Then, step 5205 or step 820
6 to step 5207, the received data RXD^
■ ^ as the first byte data DATAI in RAM2
Store DATA in 2'7-ri L'JT ←RX
DATA), and the received data RXDAT in step 8208
Set A to TXDATA as the return data to the main computer 1a (transmission data from the subcomputer 1b) (TXDATA 4-RXDATA), Step 5
The process advances to step 222 and the count value S CNT of the reception counter is counted up (5CNT←5CNT+1), and the routine exits.

Also, in step 5204 above, (RXDATA) 87B
When 6=10, that is, the command COH instructs the read mode, the process proceeds from step 5204 to step 5209 to set the read mode, and then proceeds to step 52.
10, the contents of the memory (A D BASE
D 0FFSET) and the contents of this memory (A
DB^O+A D 0FFSET) to the main computer 1a as reply data TxDATA falsely TXD
ATA ← (ADBASE+ADOFFSET) )
Similarly, in step 5222, the reception counter 5CNT is counted up (SCNT←5CNT+1) and the rule is
Exit Chin.

The reply data TXDATA set in step 8208 or step 5210 is returned at the timing of the next second byte data transmission from the main computer 1a. The same check data as the byte data DATAI is returned, and in read mode, the base address AD
The contents of RAM 22 specified by BASE and offset address A D 0FFSET (A D BASE
+ A D 0FFSET) is returned.

On the other hand, if TR≦TSET in the above step 5202, that is, the second byte and subsequent data is received, the process branches from the above step 5202 to step 5211, and from the count value 5CNT of the reception counter, the second byte data is received or the third byte is received. Determine whether byte data has been received.

When 5CNT=1, that is, the second byte of data is received in the above step 5211, the process proceeds from the above step 5211 to step 5212 to determine the mode, and when the mode is base address mode and write mode, the received data RXDATA is transferred to the second byte in step 5213. The data DATA2 of the RAM 22 is processed by the RAM 22 (0^TA2-RXDATA).

Then, the process proceeds from step 5213 to step 5214, where the previously received first byte data DATA+ is returned to the main computer 1a as return data T XDATA (T XDATA = DATAI),
The reception counter is counted up (S CNT←5CNT+1) at step y7'' 5222 and the routine is exited.

Further, when the read mode is selected in step 5212, the process proceeds from step 5212 to step 5215,
The memory contents of the physical address of RAM22 determined by the base address AD BASE and offset address AD 0FFSET (AD BASE + AD 0
FFSET), all bits are inverted, and the value (A D BASE + A D 0FFSET) with all bits inverted is sent as return data T XDATA to the main computer 1a.
Please set TXDATA←(AD BASE+ A
D0FFSET) ), similarly, step 5222
to count up the reception counter 5CNT (SCN
T←5CNT+1) Exit the routine.

On the other hand, when 5CNT=#1 in the above step 5211, it is the third byte data communication, and the above step 52
11, the process proceeds to step 8216 to determine the mode. If the read mode is selected, the process jumps from step 8216 to step 5221, and if the base address mode is selected, the received data RXDATA from the main computer 1a and the second data stored in the RAM 22 are transferred in step 5217.
Compare with byte data DATA2.

As mentioned above, in the data sent from the main computer 1a, when communication is performed normally, the second and third bytes are the same data, and when there is an abnormality in communication, the third byte is the same data. Since the data is the data obtained by inverting all bits of the data of the second byte, when RXDAT^≠DATA2 in the above step 5217, there is an abnormality in communication, so the step 5221 jumps from the above step 5217, and RXDATA = DATA.
2, the communication is normal, so step 52 is performed.
Proceeding from step 17 to step 8218, the second byte data D
Byte data (DAT
Al) Set 00 in the lower byte and set the base address A
Set D BASE (AD BASE 4-D
ATA2 + (DATA1)00) Step 522
Go to 1.

Further, if the light mode is selected in step 5216, the process proceeds from step 8216 to step 5219;
Similarly, received data RX from the main computer 1a
Compare DATA and data DATA2 of the second pie 1 to 1 stored in RAM22, and write RXDATA# DAT.
When A2, step 5219 to step 522
1 jump, RXDATA = DATA2 ノ,!
: Then, the process proceeds from step 5219 to step 5220, and the received data RXD from the main computer 1a is
Using ATA as final data, base address A D B
Write to the physical address of RAM22 determined by ASE and offset address A D 0FFSET ((A D
BASE+ A D 0FFSET)←Rx0A[A
), proceed to step 5221.

Then, steps 5216 and 52 are performed according to each mode.
18. Proceeding from each step of 5220 to step 5221, the reception permission code SC is returned to the main computer 1a, with the upper two bits set to "00" if communication is possible, and the upper two bits set to "11" if communication is not possible. - Set the reception counter S to TA in step 5222.
Count up CNT (S CNT←SCM ding+
1)! Pass through Lechoco 1.

This reception permission code SC is returned to the main computer 1a at the data transmission timing of the first byte in the next communication block TXB activated by the main computer 1a.

[Effects of the Invention] As explained above, according to the present invention, the first data and
By receiving second data obtained by inverting all bits of this first data, and comparing the value obtained by inverting all bits of the received value of this second data with the received value of the first data, In order to determine whether or not the received value of the first data is valid, it is possible to recognize data due to an abnormality occurring in a communication destination computer, and to accurately determine the validity of the data to improve communication reliability. Excellent effects can be achieved.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is a flowchart showing the communication procedure of the main computer, FIG. 2 is a flowchart showing the communication procedure of the subcomputer, FIG. 3 is a circuit block diagram of the control device, and FIG. FIG. 5 is an explanatory diagram showing a transmission/reception buffer, FIG. 5 is a time chart of clock synchronous communication, and FIG. 6 is an explanatory diagram showing the configuration of a communication block. 1a...Main computer 1b...Sub computer T XDATA...Transmission data RXDATA...Reception data

Claims (1)

[Claims] In a data communication method between in-vehicle computers connected via a serial channel, first data consisting of a predetermined number of bits and second data obtained by inverting all bits of the first data are received. By comparing the received value of the second data with all bits inverted and the received value of the first data, the first
1. A data communication method between in-vehicle computers, characterized in that it is determined whether a received value of data is valid or not.