JPH04159682A - Memory controller - Google Patents

Abstract

PURPOSE:To operate an RAS time-out process in the same manner as a memory refreshing by providing a memory control signal generator, a refresh timer, a row address strobe signal time-out timer and a refresh requesting circuit. CONSTITUTION:An RAS and CAS control block 6 receives an RAS and CAS control opening timing, and supplies a signal to a dynamic RAM. An RAS time-out timer block 7 outputs, if a time of an RAS signal active state becomes longer than a predetermined value, RAS time-out state information to a refresh requesting circuit 9. On the other hand, a memory refresh timer block 8, outputs, if a memory refreshing interval becomes longer than a predetermined value, memory refresh time-out state information to the circuit 9. The circuit 9 outputs a refresh request signal to a host apparatus.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory controller, and particularly to a memory controller having a function of performing timeout processing of a row address strobe signal when a dynamic RAM is used in page mode.

[Conventional technology]

A conventional memory controller is shown in the block diagram of FIG. When the memory controller 21 uses the dynamic RAM in page mode, a row address strobe signal (hereinafter referred to as RAS) timeout occurs completely asynchronously with the memory access cycle. This R.A.
When the output of the RAS timer 22 that detects the occurrence of S timeout and the control start timing from the host device are received at the same time, a cycle arbiter 23 is installed internally to perform RAS timeout processing in synchronization with the memory access cycle. It is a provision.

[Problem to be solved by the invention]

The conventional memory controller described above has a dynamic R
Since the RAS timeout that occurs when AM is used in page mode is handled by itself, the RAS timeout state that occurs completely asynchronously with the memory access cycle is synchronized with the memory access cycle, and the RA
S control block and column fist address strobe signal (
Since it is necessary to provide a memory access cycle arbiter to inform the control block (hereinafter referred to as CAS), there is a problem in that the function becomes complicated. or,
The RAS and CAS control blocks must determine the memory control cycle based on the states of the memory access start signal, memory refresh signal, and RAS timeout signal output by the cycle arbiter described above, so the circuit for this is complex. There was also the problem of becoming

An object of the present invention is to provide an economical memory controller with a simple circuit that does not include an internal memory access cycle arbiter or determine a memory control cycle.

[Means for Solving the Problems] The memory controller of the present invention is a dynamic RAM having a mechanism in which data can be randomly accessed by setting addresses using a row address strobe signal and a column address strobe signal. a memory controller for controlling the dynamic RAM, a memory control signal generation circuit for controlling the dynamic RAM in page mode;
refresh timer, which measures the refresh interval;
The configuration includes a row address strobe signal timeout timer that measures the operation time of the row write address strobe signal, and a refresh request circuit that generates and outputs a memory refresh request signal to the outside.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The memory controller 1 connects the control start signal line 2 to R.
Receives the start timing of AS and CAS control, and
A RAS and CAS control block supplies RAS and CAS signals to a dynamic RAM (not shown) via an AS signal line 3 and a CAS signal line 4, and performs a memory refresh operation when receiving a memory refresh signal from a memory refresh signal line 5. 6, a RAS timeout timer block 7 that measures the time that the RAS signal on the RAS signal line 3 is in the active state, and a memory refresh timer block that monitors the memory refresh signal line 5 and measures the reception interval of the memory refresh signal. 8 and RAS timeout timer block 7
and a refresh request circuit 9 which receives the timeout status information output from the memory refresh timer block 8 and outputs a refresh request signal.

Next, the operation will be explained.

The RAS and CAS control block 6 receives the start timing of RAS and CAS control from the control start signal line 2, and supplies the signal to a dynamic RAM (not shown) via the RAS signal line 3 and the CAS signal line 4. . The RAS timeout timer block 7
The time period during which the RAS signal on the S signal line 3 is in the active state is measured, and when the time period in which the RAS signal is active is longer than a predetermined RAS timeout value, RAS timeout state information is output to the refresh request circuit 9. . As a result, the refresh request circuit 9 outputs a refresh request signal to the host device. The refresh signal from the host device is sent to the memory refresh signal line 5.
and is input to the RAS and CAS control block 6.

Upon receiving the refresh signal, the RAS and CAS control block 6 starts refreshing the dynamic RAM.

On the other hand, when the memory refresh timer block 8 detects a refresh signal on the memory refresh signal line 5, it measures the reception interval of the memory refresh signal, and when the memory refresh interval becomes longer than a specified value, it sends a refresh request circuit 9 to the memory refresh signal line 5. Outputs memory refresh timeout status information. As a result, the refresh request circuit 9 outputs a refresh request signal to the host device. Similarly to the RAS timeout condition described above,
Upon receiving the refresh signal from the host device, the RAS and CAS control block 6 starts refreshing the dynamic RAM.

Note that a bus cycle arbiter that arbitrates between memory access cycles and memory refresh requests and outputs a memory refresh signal exists in a host device of the memory controller (not shown in FIG. 1).

〔Effect of the invention〕

As explained above, the present invention provides dynamic RAM
A memory control signal generation circuit for control in the memory mode, a refresh timer that measures the refresh interval, a row address strobe signal timeout timer that measures the operation time of the row address strobe signal, and a memory refresh for external devices. By providing a refresh request circuit that generates and outputs a request signal, RAS timeout processing that occurs when dynamic memory is used in page mode can be handled in the same way as memory refresh processing, and an internal memory access cycle arbiter is provided. There is no need to provide a memory control cycle, and there is no need to determine the memory control cycle within the memory control signal generation circuit, which has the effect of making the circuit simpler and more economical.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional memory controller. 1... Memory controller, 2... Control start signal line, 3... Row address strobe signal (RAS) signal line, 4... Column 0 Address strobe signal (CAS) signal line, 5...
...Memory refresh signal line, 6...R
AS and CAS controlled al block, 7...RA
S timeout timer block, 8...Memory refresh timer block, 9...Refresh request circuit. Agent Patent Attorney Susumu Uchihara 111f'D Note Laura

Claims (1)

[Claims] A dynamic controller with a mechanism that allows data to be accessed randomly by setting addresses using row address strobe signals and column address strobe signals.
A memory controller that controls the RAM includes a memory control signal generation circuit for controlling the dynamic RAM in page mode, a refresh timer for measuring the refresh interval, and a row controller for measuring the operation time of the row address and strobe signals. A memory controller comprising an address strobe signal timeout timer and a refresh request circuit that generates and outputs a memory refresh request signal to the outside.