JPH0415652B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time-division start-stop playback method for processing start-stop playback of start-stop data of a plurality of channels in a time-division manner.

When asynchronous start-stop data or telex signals are multiplexed and transmitted bit by bit, it is necessary to perform start-stop playback, and conventionally, a start-stop playback means has been provided for each channel. As a result, the circuit scale becomes larger, the equipment becomes larger, and the power consumption also increases.
It also had the disadvantage of being expensive.

Furthermore, conventional start-stop regeneration employs a method in which the start-stop data is sampled using a plurality of sampling pulses per one bit of the start-stop data, and a processor reads the sampling data for each sampling and performs start-stop regeneration processing by software. Therefore, the processing load on the processor is relatively large, and there are significant restrictions on the data speed that can be processed.For example, when using a microprocessor,
Data speeds were limited to about 300 bits/second or less.

The present invention implements sampling processing in hardware, and increases the number of shared parts through time-sharing processing.
The purpose of this is to economically perform start-stop playback of multiple channels. Examples will be described in detail below.

FIG. 1 is a block diagram of an embodiment of the present invention, in which SCAN is a scanning circuit that outputs a scanning address signal SCA by counting the clock CLK, etc.;
MPU is a microprocessor, DB is a data bus,
The SPG is initially set by the microprocessor MPU, and the sampling pulse corresponding to each channel is
Sampling pulse generation circuit that outputs SMP ₀ to SMP ₇ , D ₀ to D ₇ are delay circuits that delay the input start-stop data DI ₀ to DI ₇ by one cycle of the sampling pulse, respectively, MPX1 and MPX2 are multiplexers, and RQC is the sampling pulse SMP ₀ ~
Processing request signal that turns on at the rising edge of SMP ₇ and turns off for the channel specified by the scanning address signal SCA
Processing request control circuit that outputs RQi, ECG is a control register that outputs a start bit detectable signal STE corresponding to the channel, ST-SP is the start-stop data processing section, LAT is the output start-stop data DO ₀ corresponding to the channel.
~Latch circuit that latches DO ₇ , BUF is buffer memory.

The sampling pulse generation circuit SPG outputs sampling pulses SMP ₀ to SMP ₇ at a speed N times the speed of the start-stop data DI ₀ to _{DI 7} of each channel. configured and multiplexer
There is a delay time difference of one sampling pulse between the start-stop data DIA selected by the scanning address signal SCA in MPX1 and the start-stop data DIB selected by the scanning address signal SCA in the multiplexer MPX2 by delay circuits _D0 to _D7 . The start-stop data processing unit ST-SP detects a change in polarity from, for example, a mark to a space by comparing data DIA and DIB, and detects a start signal.

In this embodiment, time-division processing is performed on the start-stop data of 8 channels, so the scanning address signal SCA is as shown in FIG. 2a,
In addition, the sampling pulse SMP ₀ of channel CHo is the same as the sampling pulse SMP 0 of channel CH1 (b) in the same figure.
Assuming that SMP ₁ is shown in d in the same figure, the processing request control circuit RQC outputs the processing request signal RQ ₀ for channel CH0 as shown in c in the same figure, and the processing request signal RQ ₁ for channel CH1 as shown in e in the same figure. I will do it. Therefore, the start-stop data processing section ST
-SP, the start/stop data is processed in a time-division manner according to the channels using the processing request signal RQi (i=1 to 7) and the scanning address signal SCA.

In the above-mentioned FIG. 2, since the speed of the start-stop data DI ₀ is greater than the speed of the start-stop data DI ₁ , N of the speeds of these start-stop data DI ₀ and DI ₁ is
The double sampling pulses SMP ₀ and SMP ₁ are the second
The processing request signal is as shown in b and d in the figure.
RQ ₀ and RQ ₁ are as shown in c and e of FIG.
That is, the sampling pulses SMP ₀ and SMP ₁ are continuously output from the sampling pulse generation circuit SPG at a speed N times the speed of the start-stop data corresponding to the channel, and the processing request signals RQ ₀ and RQ ₁ are outputted from the sampling pulse generation circuit SPG at a speed that is N times the speed of the start-stop data corresponding to the channel. scan address signal SCA with or without
will be output accordingly. Then, the processing timing of channels CH0 and CH1 is the second
As shown in f in the figure, the speed of start-stop data DI ₀ is greater than the speed of start-stop data DI ₁ , so the number of processing times assigned to channel CH0 is
This will be more than the number of processing times allocated to 1.

Figure 3 is a block diagram of the start-stop data processing unit ST-SP, where STDET is a start bit detection circuit, _R1 and _R2 are registers, SEL1 and SEL2 are selection circuits, and CREG is a count register with an area corresponding to a channel. , SUB is the count register CREG
ZDET, a subtraction circuit that subtracts by 1 the content output from the area specified by the scanning address signal SCA in
is a zero detection circuit, and G is a gate circuit.

The start bit detection circuit STDET operates when the start bit detectable signal STE is on, and when the data DIA output from multiplexer MPX1 indicates space polarity and the data DIB output from multiplexer MPX2 indicates mark polarity, the start bit detection circuit STDET operates from mark to space. It is determined that this is a start bit whose polarity changes, and the start bit detection signal STBIT is turned on.

In registers R ₁ and R ₂ , when the sampling pulse speed is N times the start-stop data speed, register R ₂ is set to N and register R ₁ is set to N/2, and the selection circuit SEL1 is set to N/2. , selects register _R1 when the start bit detection signal STBIT is on, and selects register _R2 when it is off. Furthermore, if either the start bit detection signal STBIT or the zero detection signal ZD is on, the selection circuit SEL2 selects the output of the selection circuit SEL1, and both signals STBIT,
If ZD is also off, the output of the subtraction circuit SUB is selected.

Count register CREG is the scan address signal
Writes the output of the selection circuit SEL2 in the area specified by SCA only when the processing request signal RQi is on,
A preset type down counter is constructed in which the contents of the area are updated, the output of the selection circuit SEL1 is preset, and the subtraction circuit SUB counts down. When the output of the subtraction circuit SUB becomes zero, the zero detection signal from the zero detection circuit ZDET
ZD turns on.

The gate circuit G outputs a latchable signal LE based on the logic of ZD and RQi, and by this latchable signal LE and the scanning address signal SCA,
The data output from the multiplexer MPX1 is latched in the latch circuit LAT. Also, latchable signal LE
microprocessor MPU as interrupt signal IRQ
In addition, the microprocessor MPU reads the output of the latch circuit LAT via the buffer memory BUF and data bus DB, identifies the start bit, and controls the control register ECG to turn off the start bit detectable signal STE. If the start-stop data has, for example, a 7-bit configuration including a start bit and a stop bit, the microprocessor MPU updates the contents of the control register ECG and issues a start bit detection enable signal upon detection of the 7th stop bit. Turn on STE. Such a start bit detectable signal
STE processing is performed on a channel-by-channel basis.

FIG. 4 is an explanatory diagram of the operation of FIG.
is the channel CH, an example of which is shown in b and d of Figure 2.
Sampling pulse of channel CHi corresponding to SMP ₀ , SMP ₁
Assuming that the outline of SMPi is shown and the input start-stop data DIi is shown in figure b, multiplexer MPX
2, the data shown in c in the figure is inputted after being delayed by one sampling pulse by the delay circuit Di. When the scanning address signal SCA is i, multiplexers MPX1 and MPX2 apply the data DIA and DIB of the channel CHi to the start bit detection circuit STDET of the start-stop data processing section ST-SP.
At this time, if the start bit detectable signal STE of channel CHi is on as shown in Fig. 4h,
As shown in figure d, the start bit detection signal
STBIT turns on. Further, e in the figure shows the contents of the area corresponding to the channel CHi of the count register CREG, f in the figure shows the zero detection signal ZD, and g in the figure shows the latch enable signal LE.

Noise NS that changes from mark polarity to space polarity before start bit ST of start-stop data DIi
When the start bit detection signal STDET arrives and is added to the start bit detection circuit STDET, the start bit detection signal
STBIT turns on and count register CREG
is set to N/2 from register _R1 , and thereafter is counted down by the subtraction circuit SUB as described above, and when the zero detection signal ZD is turned on,
Assuming that the processing request signal RQi also turns on, the latch enable signal LE turns on. However, since the input start-stop data has mark polarity at this timing, the noise NS will not be mistakenly recognized as the start bit ST and will not be latched into the latch circuit LAT.

Also, when the start bit ST is input, the start bit detection signal STBIT is turned on as described above, N/2 is set in the count register CREG, and the zero detection signal ZD is set by down-counting.
When it turns on, it is almost at the center of the start bit ST, and the latch enable signal LE
When turned on, the latch circuit LAT
The start bit ST of the start-stop data DIi is latched in the area corresponding to the channel CHi, and the interrupt signal IRQ is applied to the microprocessor MPU.

Microprocessor MPU is Startbit ST
When the stop bit SP is identified, the start bit detectable signal STE of the channel CHi is turned off, and when the stop bit SP is identified, the start bit detectable signal STE is turned on. Also, after the start bit detection signal STBIT turns off, a register is added to the count register CREG for each zero detection signal ZD.
The content of _R2 is set to N, and the latch enable signal LE is turned on at approximately the center of each bit of the start-stop data and is latched in the latch circuit LAT. in this case,
If the value of N is odd, register _R1 contains (N±
1) The value of /2 will be set, but if the value of N is not extremely small, after the start bit ST is detected, the value of N set in register _R2 should be set in the count register CREG. As a result, the latch enable signal LE can be output at approximately the center timing of each bit of the start-stop data. for example,
When N=9, register _R1 is set to 4 or 5, and after the start bit ST is detected, the latch enable signal LE is output at the timing of 4/9 or 5/9 of each bit of the start-stop data. Therefore, it is possible to latch at the timing approximately at the center of each bit.

FIG. 5 shows a block diagram when applied to a time division bit multiplexing device. MSTSP is a time division start-stop regeneration circuit with the configuration shown in FIG. ₀
~Performs start-stop playback of DI ₃ , transfers the transmitting signal SX from the transmitting/receiving register SRR to the multiplexing transmitting/receiving section via the data bus DB, and transfers the receiving signal RX from the multiplexing transmitting/receiving section from the transmitting/receiving register SRR to the data bus.
Set in the channel-corresponding area of the reception register RDR via DB, and read start/stop data for 4 channels DI ₄
~Input DI ₇ to the time division start-stop regeneration circuit MSTSP,
The start-stop reproduced start-stop data DO ₄ to _{DO 7} are output. In other words, this shows the case where the 8 channels of input start-stop data DI ₀ to DI ₇ in Fig. 1 are divided into 4 channels, DI ₀ to DI ₃ for transmission and DI ₄ to DI ₇ for reception. It is something.

In addition, the microprocessor MPU performs start-stop playback control as described above using the interrupt signal IRQ, and transfers the transmit signal SX to the multiplex transmitter/receiver or performs reception processing of the receive signal RX using the interrupt signal IRQM from the multiplex transmitter/receiver. It is something to do.

As explained above, the present invention provides multi-channel
Start-stop data for _CH0 to CH7 Channel-compatible sampling pulse SMP ₀ corresponding to the speed of CH0 to _CH7
~SMP ₇ is generated by the sampling pulse generation circuit SPG, and a processing request signal RQi corresponding to the channel is output from the processing request control circuit RQC using the sampling pulse SMP ₀ ~ SMP ₇ and the scanning address signal SCA from the scanning circuit SCAN, and the processing request signal RQi corresponding to the channel is outputted from the processing request control circuit RQC, and the scanning address signal
The start bit ST is detected from the start-stop data of the channel specified by SCA and the data delayed by one period of the sampling pulse of this channel, and according to the scanning address signal SCA and the processing request signal RQi, A latchable signal LE of a predetermined period from the start bit detection point is output from the start-stop data processing section ST-SP, and this latchable signal LE
Let be the interrupt signal IRQ of the microprocessor MPU,
The microprocessor MPU reads and processes the start-stop data latched by the latch enable signal LE, and the start-stop data of multiple channels is processed in a time-division manner, compared to the conventional example that performs start-stop playback corresponding to each channel. Since many parts are shared, the structure is economical. Also, interrupts to the microprocessor MPU are not based on the sampling pulse period, but
This is when the latch enable signal LE is output, so
Start-stop data of multiple channels can be easily processed. Furthermore, even if the data speed of each channel is different, the processing request signal can be processed by generating sampling pulses corresponding to the data speed.
RQi is also output in accordance with the data rate, and has the advantage of being able to distribute processing over time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
The figure is an explanatory diagram of the operation of Figure 1, Figure 3 is a block diagram of the start-stop data processing section in Figure 1, Figure 4 is an explanatory diagram of the operation of Figure 3, and Figure 5 is a diagram of the time division bit multiplexing device. FIG. 4 is a block diagram when applied. MPX1 and MPX2 are multiplexers, SPG is a sampling pulse generation circuit, SCAN is a scanning circuit, RQC is a processing request control circuit, ECG is a control register, _D0 to _D7 are delay circuits, ST-SP is a start-stop data processing section, and LAT is a Latch circuit, BUF is buffer memory, MPU is microprocessor, CLK is clock, SMP ₀ to SMP ₇ are sampling pulses,
RQi is a processing request signal, STE is a start bit detection enable signal, SCA is a scanning address signal, LE is a latch enable signal, IRQ is an interrupt signal, STDET is a start bit detection circuit, SEL1, SEL2 are selection circuits, R ₁ ,
R ₂ is a register, CREG is a count register,
SUB is a subtraction circuit, and ZDET is a zero detection circuit.

Claims (1)

[Scope of Claims] 1. A sampling pulse generation circuit that generates a sampling pulse corresponding to a channel at a speed N times the speed of start-stop data of each of a plurality of channels, and generates a scanning address signal that sequentially specifies the plurality of channels. a scanning circuit; a processing request control circuit that outputs a processing request signal corresponding to the channel from the rising edge of the sampling pulse corresponding to the channel to the scanning address signal specifying the channel; a channel specified by the scanning address signal; When the start-stop data of the start-stop data is space polarity and the data obtained by delaying the start-stop data by one period of the sampling pulse of the channel is of mark polarity, it is determined that the start bit changes from mark polarity to space polarity, and the start bit of the channel is determined. a start-stop data processing unit that outputs a latchable signal with a period corresponding to the speed of the start-stop data of the channel based on the scanning address signal and the processing request signal after detection of the latchable signal and the scanning address signal; and a microprocessor that reads the start-stop data latched in the latch circuit corresponding to each channel by applying the latch enable signal as an interrupt signal, and the start-stop data of the plurality of channels is time-divided by the start-stop data processing section. A time-division start-stop playback method characterized by processing.