JP2570183B2 - Serial communication circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial communication circuit for digital data, and more particularly to a simultaneous serial communication circuit between many-to-one transmission / reception devices.

[0002]

2. Description of the Related Art Conventionally, in this type of serial communication circuit,
(1) a plurality of transmitting apparatuses communicate with the same receiving apparatus using independent communication paths; or (2) a single communication path is shared between the transmitting and receiving apparatuses. There is a method of performing some kind of timing arbitration between them so that transmission data does not collide. For example, in JP-A-63-185139, a plurality of electronic devices are connected to the same controller via independent transmission / reception signal lines, and data is transmitted from each electronic device to the controller.

[0003]

In these conventional serial communication circuits, in the serial communication circuit of (1),
It is necessary to provide communication paths as many as the number of transmission devices, and as the number of transmission devices increases, there is a problem that the structure of the communication channel itself and the receiving unit on the reception device side increases, and
In the serial communication circuit of (2), there is a problem that a circuit for timing arbitration may be complicated, and a dedicated timing signal path or the like may have to be provided for timing arbitration. .

An object of the present invention is to provide a serial communication circuit having a simple circuit configuration for performing simultaneous serial communication from a plurality of transmitting devices to the same receiving device using only one communication path.

[0005]

SUMMARY OF THE INVENTION A serial communication circuit according to the present invention includes a communication path, a receiving apparatus having a pulse generator for generating pulses at certain intervals, and transmitting the pulses to the communication path. The first, second,..., N-th (n ≧
2) and the first, second, and second transmission devices provided corresponding to the first, second,.
,..., N-th pulse delay circuit and first, second,.
.., N-th delay amount insertion / extraction switch for outputting an input signal or an output signal of the n-th pulse delay circuit. A signal output circuit for switching a corresponding delay amount insertion / removal switch; an input of the first pulse delay circuit is connected to a communication path; and an input of an i-th (2 ≦ i ≦ n) pulse delay circuit is (i) -1) is connected to the delay amount insertion / removal switch, the output of the n-th delay amount insertion / removal switch is connected to the input of the receiving device, and the pulse transmitted from the pulse generator and the n-th delay amount in the receiving device. A pulse time difference measuring means for measuring a time difference between the delayed pulse output from the delay amount insertion / removal switch, and decomposing the time difference into a sum of the respective inherent delay amounts of the respective pulse delay circuits; Means output Having a circuit for determining each of the transmitted bit value Luo each transmission apparatus.

[0006]

According to the present invention, a pulse delay circuit and a delay amount insertion / extraction switch are provided for each transmission device in a communication path, and the pulse delay circuit is measured on the reception device side to determine whether each pulse delay circuit is inserted in the communication path. Is determined, and a method of obtaining each transmission bit value is employed, so that simultaneous serial communication from a plurality of transmission devices to the same reception device can be realized using only one communication path and with a simple circuit configuration. .

[0007]

Next, embodiments of the present invention will be described with reference to the drawings.

[0008] Figure 1 is a block diagram of a serial communication circuit of an embodiment of the present invention, FIG. 2 is a configuration diagram of the receiving apparatus 1, FIG. 3 is transmitting device 2 ₁ to 2 _n diagram of FIG. 4 is a serial communication circuit FIG. 5 is a timing chart showing the operation of FIG.

The serial communication circuit according to the present embodiment includes a receiving device 1, n transmitting devices 2 ₁ , 2 ₂ ,..., 2 _n , an initial pulse delay circuit 3, and transmitting devices 2 ₁ , 2 ₂ , 2 respectively. …,
2 _n and delay amounts of 2 ⁰ D, 2 ¹ D,.
^N pulse delay circuits 4 ₁ , 4 ₂ ,.
4 and _n, respectively transmitting device 2 _{1, 2} 2, ..., n number of delay amounts corresponding to the 2 _n insertion changeover switch 5 _1, 5 _2, ..., 5
_n and a communication path 6.

The initial pulse delay circuit 3 receives a signal from the receiver 1.
Pulse S output to channel 6₁By the delay amount d,
Pulse S_TwoIs output. Pulse delay circuit 4₁Is the pulse S
_TwoThe delay amount 2⁰Delay by D. Delay amount insertion / removal switch
Chi 5₁Is the transmitting device 2₁The switching signal output from is "0"
If so, pulse delay circuit 4₁Select and switch the input signal of
If the signal is "1", the pulse delay circuit 4₁Output signal
Select and output. Pulse delay circuit 4_TwoIs the delay amount
Replacement switch 5₁Input signal and delay 2 ¹Only D
Delay. Delay insertion / removal switch 5_TwoIs the transmitting device 2_Two
If the switching signal output from is "0", the pulse delay time
Road 4_TwoIs selected, and if the switching signal is "1",
Pulse delay circuit 4_TwoAnd output the selected signal. Pa
Loose delay circuit 4_Three~ 4_nAlso pulse delay circuit 4_TwoSame as
Yes, delay amount switch 5 _Three~ 5_nDelay insertion and removal
Selector switch 5_TwoIs the same as However, delay amount insertion / removal
Replacement switch 5_nIs input to the receiving device 1.

[0011] transmitting device 2i (i = 1~n), as shown in FIG. 3, as a trigger pulse S ₁ delivered to the communication path 6 from the receiving device 1, delay insertion by the value of the transmitted bit b _i It has a D-type flip-flop 21 for sending a switching signal to the changeover switch 5 _i .

The receiving apparatus 1 has a period D as shown in FIG.
Clock generator 11 for generating clock pulse S ₄ of
When, a pulse generator 12 for delivering a pulse S ₁ based on the clock pulses S ₄ in the communication path 6 at regular intervals, it starts counting the pulse S ₁ from the pulse generator 12, a delay insertion changeover switch 5n the counter 13 stops counting the pulse S _3, and a transmission bit b ₁ ~b value transmitted bit value determines the _n decision circuits 14 from the count value S ₅ of the time of stopping the counter 13.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG.

Based on the clock pulse S ₄ from the clock generator 11, a pulse S ₁ having a pulse width D is generated by the pulse generator 12.
And sent to the communication path 6 and input to the counter 13 at the rising timing of the counter 13.
Starts reset. The pulse S ₁ sent to the communication path 6 is delayed by the delay amount d in the initial pulse delay circuit 3 to become a pulse S ₂ .

According to the transmission bit b _i , each transmission device 2 _i (i = 1 to n) transmits a delay amount insertion / removal switch 5 _i (i = 1 to 5) at the rising timing of the pulse S ₁ through the flip-flop 21i. Send a switching signal to n). Thereafter, the delay amount d delayed pulse S ₂ each pulse delay circuit 4 ₁ to 4 _n and the delay amount insertion changeover switch 51 _to
Sequentially sent to 5 _n, the counter 13 is stopped at the rise timing of the pulse S ₃ when returning to the receiving apparatus 1 again. The output S ₅ of the counter 13 at this time is the counter 13
The transmission bit value determination circuit 14
The output value _{B = T / D = b 1} 2 0 + b 2 2 1 + b 3 2 2 +
.. + B _n 2 ^n-1 are directly read, and each transmission bit b _{1 to} b _n
Is determined.

[0016]

As described above, according to the present invention, a pulse delay circuit and a delay amount insertion / removal switch are provided for each transmission device on a communication path, and the reception device measures the pulse delay amount. Since it is determined whether each pulse delay circuit is inserted in the communication path and obtains each transmission bit value,
This has the effect that simultaneous serial communication from a plurality of transmitting devices to the same receiving device can be realized with a simple circuit configuration using only one round-trip communication path.

[Brief description of the drawings]

FIG. 1 is a block diagram of a serial communication circuit according to one embodiment of the present invention.

FIG. 2 is a configuration diagram of a receiving device 1.

3 is a configuration diagram of a transmitting device 2 ₁ to 2 _n.

FIG. 4 is a timing chart showing an operation of the serial communication circuit of FIG. 1;

[Explanation of symbols]

Count value 11 of the first receiver device 2 ₁ to 2 _n transmitter 3 initial pulse delay circuit 4 ₁ to 4 _n pulse delay circuit 5 ₁ to 5 _n delay insertion changeover switch 6 channel S ₁ to S ₄ pulse S ₅ counter 13 Clock generator 12 Pulse generator 13 Counter 14 Transmission bit value determination circuit 21i D-type flip-flop

Claims (4)

(57) [Claims] 1. A receiving apparatus comprising: one communication path, a pulse generator for generating pulses at a certain interval, and transmitting the pulse to the communication path; and a first, a second and a second connected to the communication path. …,
The first, second,..., N-th transmission devices provided corresponding to the n-th (n ≧ 2) transmission device and the first, second,. A pulse delay circuit;
,..., And n-th delays which are provided corresponding to the n-th transmission device and output input signals or output signals of the first, second,. A signal output circuit for switching a corresponding delay amount insertion / removal switch according to a transmission bit value in each of the transmitting devices; an input of the first pulse delay circuit is connected to the communication path; And
The input of the ith (2 ≦ i ≦ n) pulse delay circuit is (i−
The output of the n-th delay amount insertion / removal switch is connected to the input of the receiver, and the pulse transmitted from the pulse generator and the pulse output from the pulse generator are connected to the input of the receiver. A pulse time difference measuring unit that measures a time difference between the delayed pulse output from the n-th delay amount insertion / removal switch, and decomposes the time difference into a sum of the respective inherent delay amounts of the respective pulse delay circuits; A serial communication circuit having transmission bit value determination means for determining the transmission bit value of each of the transmission devices from the output of the pulse time difference measurement means. 2. The D-type flip-flop, wherein the signal output circuit is a D-type flip-flop that sends a switching signal to a corresponding delay amount insertion / removal switch according to a transmission bit value using a pulse transmitted from the receiving device to the communication path as a trigger. Item 2. The serial communication circuit according to item 1. 3. The pulse time difference measuring means starts resetting with a pulse sent from the pulse generator to the communication path, and performs a counting operation with a pulse output from the n-th delay amount insertion / removal switch. 3. The serial communication circuit according to claim 1, wherein the serial communication circuit is a counter that stops. 4. The apparatus according to claim 1, further comprising an initial pulse delay circuit that delays a pulse transmitted from the receiving device to the communication path and outputs the delayed pulse to a first pulse delay circuit and a first delay amount insertion / removal switch. 4. The serial communication circuit according to claim 3.