JPH04151854A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce chip size by a method wherein the number of wirings is reduced by turning parallel wirings between mega cells into serial connection wirings. CONSTITUTION:The step-up ratio of frequency of a crock step-up circuit 10 is made to coincide with parallel bit width. Adress date having a specified bit width, which data are generated by a mega cell 1, are converted into serial adress data by a serial-parallel converter 4. The serial adress data wherein a frequency stepped-up from an external clock frequency is used are transferred on a serial adress data transferring line 14 at a high speed, and delivered to other mega cells 2, 3. Said data are converted into address data having a specified bit width by serial-parallel convertors 8, 9, and delivered in the insides of the mega cells 2, 3. The same operation is performed concerning to input date. Thereby the number of wirings is decreased and chip size can be reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device that performs wiring layout between megacells by an automatic layerer 1 to a program.
In particular, the circuit configuration is designed to reduce the chip size after automatic layout.

[Conventional technology]

Conventionally, in this type of semiconductor integrated circuit device, address data and input/output data, which are parallel data between megacells, have been connected by wiring in the form of a bus having a constant bit width.

FIG. 4 is a connection diagram of an example of a conventional device in which megacells are wired using an automatic layout program. Megacell (
A-C) Address data with a width of 4 bits between 1 and 3 is laid out by the address bus 21, which also has a width of 4 bits, and input/output data configured as a bus with a width of 4 bits is also laid out using the same 4-bit width. The wiring layout was based on an input/output data bus 22 having a bit width. In addition, the clock from the clock terminal is clock transfer l ¥ 812
It was connected to each megacell 1-3 by.

[Problem to be solved by the invention]

In the above-described semiconductor cumulative circuit device, address data and input/output data between megacells must be connected by wiring in a path having a constant bit width. In this case, in a semiconductor integrated circuit device where wiring between megacells is laid out using automatic layout progera, the wiring area increases by more than 50% compared to wiring done by a designer due to reasons such as an increase in the number of wires. As a result, there was a drawback that the chip size increased.

It is an object of the present invention to provide a semiconductor integrated circuit device that eliminates such drawbacks and reduces the chip size by replacing the parallel connection wiring between megacells with serial connection wiring and reducing the number of wiring lines. It's true.

[Means to solve the problem]

The present invention provides a semiconductor integrated circuit device that performs wiring layout between megacells using an automatic layout program, and includes a serial-parallel converter that converts parallel connections of signal lines between the megacells into serial connections; It is characterized in that it has a clock multiplier circuit for transferring data on the serial connection -F at high speed, and the frequency multiplication rate of this clock multiplier circuit is made to match the parallel bit width.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. Address data having a constant bit width generated by megacell 1 is converted into serial address data by serial-parallel converter 4.

The serial address data is transferred at high speed on the serial address data transfer path 14 using a frequency multiplied by the external clock frequency by the clock multiplier circuit 10 and is transmitted to the other mechanical macros 2 and 3. The serial address data transmitted to the megacells 2 and 3 is converted into address data of a constant bit width by the serial-parallel converters 6 and 9, and transmitted to the inside of the megacells 2 and 3.

An example of the internal configuration of this clock multiplication concave #r], 0 is shown in the second example.
As shown in the figure.

The clock signal input from the external terminal is sent to the delay element 16. Exclusive OR circuit] 9 multiplies the frequency to twice the frequency of the input signal, and then a delay element] 8. The exclusive OR circuit 19 further multiplies the frequency into a serial-to-parallel conversion clock having twice the frequency, and transmits it to the serial-to-parallel converters 4-9.

In this embodiment, since address data and input/output data having a width of 4 bits are assumed, the clock multiplier circuit 10 generates a serial-parallel converter clock having a frequency four times that of the external input clock. There is. Therefore, it is possible to transfer 4-bit data on the serial address transfer paths 1.3 to 1.5 with one pattern of the external manual clock, and data transfer without delay in megacell operation is possible.

The above explanation was only about address data, but
The same operation is performed for input data.

〔Effect of the invention〕

As explained above, in the present invention, by serially connecting address data and input/output data between megacells, the number of wires can be reduced to 1j when wiring layout is executed by an automatic layout program, and the wiring area can be reduced. This has the effect of reducing the chip size, and in the case of parallel connections, it also prevents malfunctions due to differences in switching speed between bits due to unbalanced wiring loads of each bit.

Furthermore, in the present invention, the chip size increases by adding a serial-parallel converter and a clock multiplier circuit, but the reduction in wiring area is sufficiently larger than this increase in chip size, so the chip size is reduced. It has the effect of being able to be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the semiconductor integrated circuit device of the present invention, FIG. 2 is a circuit diagram of an example of the clock multiplier circuit of FIG. 1, and FIG. 3 is a waveform diagram of the clock multiplier circuit of FIG. 2. , FIG. 4 is a block diagram of a conventional semiconductor integrated circuit. 1, to 3... Mega cells A to C14 to 9... Serial parallel converter, 10... Clock multiplier circuit, 11 External input clock terminal, 12... Clock transfer path. 13... Serial-to-parallel conversion clock transfer path, 14
... Serial address data transfer path, ]5... Serial input/output data transfer path, 16, 1.8... Tilley element, 17.19... Exclusive OR circuit, 2].
・Address bus, 22...I/O data bus. Agent Patent Attorney Uchihara Ondai J □L Side

Claims (1)

[Claims] A semiconductor integrated circuit device that performs wiring layout between megacells using an automatic layout program includes a serial-parallel converter that converts parallel connections of signal lines between the megacells into serial connections, and a serial-parallel converter that converts data on the serial connections between the megacells. 1. A semiconductor integrated circuit device comprising a clock multiplier circuit for high-speed transfer, the frequency multiplication rate of the clock multiplier circuit being made to match the parallel bit width.