JPH04137975A - Inverse orthogonal transformation method and circuit - Google Patents

Abstract

PURPOSE:To attain high speed processing with a small sized circuit by applying orthogonal transformation processing only to a partial column including a valid coefficient extracted from a matrix whose elements are DCT coefficients. CONSTITUTION:In the case of the inverse orthogonal transformation method for a decoder, in which a picture data is subject to 2-dimension orthogonal transformation to each block comprising NXN picture elements, the result is quantized and coded and the obtained input code is decoded and subject to inverse quantization and 2-dimension inverse orthogonal transformation, each column of a coefficient matrix comprising N-row and N-column being the result of 2-dimension orthogonal transformation of a block of the picture data is divided into a partial column including a prescribed number of components respectively and a partial column including a valid coefficient having a value other than zero is extracted among the divided partial columns, the operation equivalent to linear orthogonal transformation is implemented to each component of the extracted partial column, the result of the operation corresponding to the extracted partial column is outputted as a component of a column corresponding to the result of linear inverse transformation and the 2nd-dimension orthogonal transformation is implemented to the result of the linear inverse transformation to obtain the picture data.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figures 10 to 16) Means for solving the problem to be solved by the invention (Figure 1) Operation implementation Example (Figures 2 to 9) Effects of the invention [Summary] Based on a code using adaptive two-dimensional discrete cosine transform encoding method 2, which is used for compressing multivalued images such as halftone images and color images. , regarding an inverse orthogonal transform method and an inverse orthogonal transform circuit used in an image data restoration device that restores image data, the purpose is to enable high-speed processing with a small circuit. In an inverse orthogonal transform method of a restoration device, the input code obtained by quantizing and encoding the result of two-dimensional orthogonal transform is decoded, dequantized, and two-dimensional inverse orthogonal transform is performed to restore image data. Each column of an N-by-N coefficient matrix, which is the result of two-dimensional orthogonal transformation of a block of image data, is divided into sub-sequences each containing a predetermined number of components, and from among the sub-sequences, valid elements with values other than zero are selected. A subsequence containing coefficients is extracted, an operation equivalent to one-dimensional orthogonal transformation is performed on each component of the extracted subsequence, and the operation result corresponding to the extracted subsequence is converted into a correspondence with the one-dimensional inverse transformation result. In this method, image data is obtained by outputting the image data as a column component, and performing a second-dimensional orthogonal transformation on this one-dimensional inverse transformation result.

[Industrial application field]

The present invention provides an inverse orthogonal transform method for an image restoration device that restores image data based on a code based on an adaptive two-dimensional discrete cosine transform encoding method used for compressing multivalued images such as halftone images and color images. and an inverse orthogonal transform circuit.

An adaptive discrete cosine transform coding method (^adaptive DiscreteCosin) that uses orthogonal transform is used as a coding method to compress image data representing multivalued images such as halftone images and color images without losing their characteristics.
e Transfer+n (hereinafter referred to as ADCT method) is widely used.

In an image compression device using this ADCT method, a multivalued image is divided into blocks of, for example, 8 pixels x 8 pixels, each of these blocks is multiplied by a matrix consisting of a predetermined transformation constant, and this orthogonal transformation is performed. The result is encoded. Therefore, in order to restore the original image from this code,
It is necessary to inverse transform the orthogonal transform result obtained by decoding this code by performing orthogonal transform again using a matrix consisting of another transform constant.

[Conventional technology]

FIG. 11 shows the configuration of an image compression device to which the ADCT method is applied. Further, FIG. 12 shows an example of blocks obtained by dividing a multivalued image.

The DCT transformation unit 711 performs two-dimensional discrete cosine transformation (hereinafter referred to as DCT) processing by multiplying the input block by the matrix of transformation constants described above. As a result, D represents the spatial frequency distribution of the image of each block.
As the CT coefficients, a matrix of 8 rows and 8 columns as shown in FIG. 13 is generated.

Each component of this DCT coefficient is quantized in a linear quantization unit 721 using a quantization threshold QTH determined based on visual sensitivity to each spatial frequency component, and a quantization coefficient I)ou is calculated. Ru. This quantization threshold Q T
H is a quantization matrix (2) determined based on experimental results, and H is multiplied by a predetermined coefficient.

-g, the visual sensitivity to low spatial frequencies is high and the visual sensitivity to high spatial frequencies is low, so as shown in Figure 14, the absolute value of the component of the quantization matrix VtH corresponding to low spatial frequencies is small. , conversely, the absolute value of the component corresponding to a high spatial frequency is large. Therefore, as shown in Fig. 15, the quantization coefficient I Most AC components are effective coefficients having a value rQJ, and most AC components are often invalid coefficients having a value rQJ.

Each component of this quantization coefficient D0 is converted into one-dimensional data according to a scanning order called zigzag scan as shown in FIG. The encoding unit 731 encodes the set of the value of each effective coefficient and the number of invalid coefficients between the effective coefficient before that effective coefficient, thereby obtaining the quantized coefficient I corresponding to one block.
)ou is compression encoded.

By repeating the above operations for each block that makes up one screen, the image data for one screen is encoded, and this encoded data is stored in a disk device or transmitted via a transmission path. Ru.

Such encoded data is restored to image data by a restoration device shown in FIG.

The decoding unit 811 of the restoration device decodes the input encoded data to restore the quantization coefficient D0, and the dequantization unit 821 sets a quantization threshold Q t to each component of this quantization coefficient DQL+.
The DCT coefficients are restored by multiplying the corresponding components of o. Further, the inverse DCT transform unit 831 restores the image data of each block by performing two-dimensional inverse DCT transform processing on the DCT coefficients corresponding to each block.

Here, in the inverse DCT transformation process, a one-dimensional inverse DCT transformation result is obtained by multiplying the above-mentioned DCT coefficients by a matrix A (hereinafter referred to as transformation constant A) consisting of a predetermined transformation constant.
This is a process in which the transposed matrix obtained by interchanging the rows and columns of this conversion result is multiplied by the above-mentioned conversion constant A, and this multiplication result is transposed again.

The i-th column Y of the above-mentioned one-dimensional inverse DCT transformation result is calculated using the equation (
1). Also, the i-th of the one-dimensional inverse DCT transformation result
Each component of column Y is expressed by equations (2) to (9).

Y=A-X Y+ = (AzXX +A,,XX.

+A, 7XX.

Yz　-(Az+xX ＋Az　a　xχ4 Ten A2. XX.

Y: l = (A: l I X X ++ A
x a X X a + A :r 7 X X t Y4 = (A41XXI +A44XX4 +A 47X X7 Ys = (As+X +A, □×X2 10A, 5XX.

+ A IeX Xe +A22XXZ + A zs X X s ±AzsXXe +A3□×X2 10A y s z X 2 ten A ss X X s +As5XXa + A b 2 X X z + A 6 S X X S +A6IIxX8 +A,, XX2 + A+b ) ... (3) +A33Xχ2 10A 3b X X b) ... (4) +A, 3xX2 +A,,Xχ6) ... (5) +AS3xX2 +A9. XX6 ) ... (6) +A6:l×χ2 + A b b X X b ) ... (Force Y 7 = (A?1 X X + + A41
XXI +At:+XXz+A? 4X Xa +At
5X Xs +A? ,X Xb+A? ? X Xq +
A71X Xs ) ... (8) Ye
= (A11xxl +AezXXz +Aa
3XXz+Al4X Xa +As5X XS +
Aa&X Xi+A*tX X? +A11IX
s )...(9) Conventionally, these formulas (
2) The inverse DCT transform unit 831 of the restoration device is equipped with eight sets of calculation circuits that perform calculations corresponding to each of equations (9), and by operating these calculation circuits in parallel, one-dimensional The aim was to speed up DCT conversion processing.

[Problem to be solved by the invention]

By the way, as described above, if the inverse DCT transformer 831 is configured with eight sets of arithmetic circuits, high-speed processing is possible, but the circuit scale of the inverse DCT transformer 831 becomes large.
There was a problem in that the restoration device became large.

On the other hand, simply reducing the number of multipliers and adders increases the time required for one-dimensional inverse DCT transformation processing, and cannot meet the demand for shortening the time required for restoration processing.

The present invention was created in view of these points, and an object of the present invention is to provide an orthogonal transform device that is a small circuit and enables high-speed processing.

[Failure to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

In FIG. 1(A), the invention of claim 1 decodes the input code obtained by quantizing and encoding the result of two-dimensional orthogonal transformation of image data for each block consisting of N×N pixels, In the inverse orthogonal transform method of a restoration device that restores image data by inverse quantization and two-dimensional inverse orthogonal transform, each column of an N-by-N coefficient matrix that is the result of two-dimensional orthogonal transform of a block of image data is Divide into subsequences containing a predetermined number of components, extract subsequences containing effective coefficients with non-zero values from these subsequences, and calculate 1 for each component of the extracted subsequences. An operation equivalent to dimensional orthogonal transformation is performed, the operation result corresponding to the extracted subsequence is output as a component of the corresponding column of the one-dimensional inverse transformation result, and two-dimensional Obtain image data by performing orthogonal transformation of the eyes.

In FIG. 1A, the invention according to claim 2 is the inverse orthogonal transform method according to claim 1, in which a one-dimensional inverse transform result of each column is output as a component of a corresponding row of a transposed matrix.

In FIG. 1(B), the invention of claim 3 decodes the input code obtained by quantizing and encoding the result of two-dimensional orthogonal transformation of image data for each block consisting of N×N pixels, The coefficient storage means 111 in the inverse orthogonal transform circuit of the restoration device that performs inverse quantization, two-dimensional inverse orthogonal transform, and restores image data stores each component of the input coefficient matrix in N rows and N
Store as a matrix of columns.

The read control means 120 includes a determination means 1 for determining whether each of the subsequences constituting each column of the coefficient matrix input to the coefficient storage means 111 is an effective subsequence containing an effective coefficient.
21, and address holding means 122 that holds the address of the coefficient storage means 111 corresponding to the subsequence determined to be a valid subsequence by the determination means 121, and based on the address held in this address holding means 122, Then, the coefficient storage means 111 is instructed to output each component included in the effective subsequence.

The conversion constant storage means 131 stores a constant matrix of N rows and N columns consisting of conversion constants corresponding to each component of the coefficient matrix. Outputs the conversion constant contained in the column.

The first transformation means 132 performs an operation equivalent to orthogonal transformation on each of the components of the coefficient matrix entered manually and the transformation constant output from the transformation constant storage means 131, and performs an operation equivalent to orthogonal transformation on each component of the coefficient matrix entered manually and on the transformation constant outputted from the transformation constant storage means 131. When the calculations corresponding to all the subsequences are completed, the calculation results are output as the one-dimensional inverse transformation results of the corresponding sequences.

The conversion result holding means 141 holds the output of the first conversion means 132.

The write control means 142 specifies, in accordance with the address held in the address holding means 122, a storage location in the transformation result holding means 141 of the one-dimensional inverse transformation result corresponding to the corresponding column of the coefficient matrix.

The second transformation means 151 performs a second-dimensional orthogonal transformation based on the one-dimensional inverse transformation result held in the transformation result holding means 141.

In FIG. 1(B), the invention according to claim 4 provides that the coefficient storage means 111 in the inverse orthogonal transform circuit according to claim 3 has two
The first transformation means 132 has a capacity to store coefficient matrices corresponding to each of the two blocks, and the first transformation means 132 performs a one-dimensional inverse transformation operation in parallel with the input of the coefficient matrices to the coefficient storage means 111. .

In FIG. 1(B), the invention according to claim 5 is the inverse orthogonal transform circuit according to claim 3, in which the determining means 121 determines that each subsequence formed from N/2 components is an effective subsequence. The conversion constant storage means 1 is configured to determine whether or not
31 is configured to alternately output N/2 conversion constants in the first half and N/2 conversion constants in the second half of the corresponding column according to the output of each component of the coefficient matrix, and the first conversion means 132 is N/2 simultaneously output from the conversion constant storage means 131.
It is configured to include N/2 calculation means 133 corresponding to each of the conversion constants.

Further, each of the N/2 calculation means 133 multiplies the input coefficient matrix component by each of the conversion constants alternately outputted from the conversion constant storage means 131 corresponding to this component. It is constituted by a multiplication means 134, an integration means 135 for integrating each of the multiplication results obtained by the multiplication means 134, and a holding means 136 for holding each of the integration results obtained by the integration means 135. .

In FIG. 1(B), the invention according to claim 6 provides that in the inverse orthogonal transform circuit according to claim 5, the first transform means 132:
The multiplication means 13
4 and the integration means 135.

In FIG. 1(B), the invention according to claim 7 provides the inverse orthogonal transform circuit according to claim 3, in which the write control means 142:
An address generation means 143 for generating an address of the transformation result holding means 141 corresponding to a corresponding row of a transposed matrix obtained by transposing a matrix consisting of a one-dimensional inverse transformation result in accordance with the calculation result obtained by the first transformation means 132. Configured with the necessary features.

In FIG. 1(B), the invention according to claim 8 provides that the inverse orthogonal transform circuit according to claim 7 has a value other than zero from each component of the one-dimensional inverse transform result inputted to the transform result holding means 141. detection means 144 for detecting an effective coefficient;
4, an output instruction means 145 is added for instructing the conversion result holding means 141 to output a subsequence containing an effective coefficient from each column of the matrix of the one-dimensional inverse transformation result, The second conversion means 151 is the conversion result holding means 1
The partial sequence outputted from 41 is configured to undergo second-dimensional orthogonal transformation processing.

In FIG. 1(C), the invention according to claim 9 stores the one-dimensional inverse transform result stored in the transform result holding means 141 in place of the second transform means 151 in the inverse orthogonal transform circuit according to claim 7. 1 conversion means 132 and input means 161 for instructing conversion constant storage means 13 to output a corresponding conversion constant.

In FIG. 1(C), the invention of claim 10 is the invention of claim 9.
The described inverse orthogonal transform circuit includes a detecting means 144 for detecting an effective coefficient having a value other than zero from each component of the one-dimensional inverse transform result inputted to the transform result holding means 141, and a detecting means 1.
44, the conversion result holding means 141
Output instruction means 145 for instructing output of a subsequence containing effective coefficients from each column of the matrix of the one-dimensional inverse transformation result.
and the input means 161 inputs the conversion result holding means 14
The partial sequence outputted by 1 is input to the first conversion means 132.

[For production]

In the invention of claim 1, a subsequence including an effective coefficient is extracted from subsequences obtained by dividing each column of a coefficient matrix, and only arithmetic operations are performed on each component of the extracted subsequence. The calculation results are output as one-dimensional inverse transformation results corresponding to the columns to which these subsequences belong.

Here, as can be seen from equations (2) to (9) above, when each column of the coefficient matrix is orthogonally transformed, the calculation result for the invalid coefficient whose value included in this column is zero is orthogonal. Does not contribute to the conversion result. Therefore, the calculation result for the effective subsequence included in each column is equivalent to the result of orthogonal transformation of the corresponding column of the coefficient matrix, and it is possible to reduce the amount of calculation required to obtain the one-dimensional inverse orthogonal transformation result. Become.

Further, in the invention of claim 2, the calculation result corresponding to the extracted subsequence is output as a component of a transposed matrix obtained by interchanging the rows and columns of the matrix resulting from the one-dimensional inverse transformation. Therefore, in the second-dimensional orthogonal transformation process, the process of transposing the one-dimensional inverse transformation result can be omitted.

Further, in the invention of claim 3, the read control means 120 having the determination means 121 and the address holding means 122 extracts effective subsequences from the coefficient matrix stored in the coefficient storage means 111. For each component included in the effective subsequence of and the conversion constant for one column output from the conversion constant storage means 131, the first conversion means 132
An operation corresponding to dimensional orthogonal transformation is performed. Further, the output of the first transformation means 132 is stored in the transformation result holding unit 141 as a one-dimensional inverse transformation result corresponding to the column of the coefficient matrix to which the relevant effective subsequence belongs, in accordance with instructions from the write control means 142. It is held and passed to the second conversion means 151.

In this way, by performing arithmetic processing by the first converting means 132 only on the effective subsequence extracted by the readout control means 120, the calculation processing is performed on all columns of the coefficient matrix. A dimensional inverse transform result can be obtained, the amount of calculation can be reduced, and the time required for one-dimensional inverse orthogonal transform processing can be shortened.

In the invention of claim 4, in parallel with the operation of inputting a new coefficient matrix to the coefficient storage means 111, the first conversion means 13
2, it is possible to perform a one-dimensional orthogonal transformation operation on the coefficient matrix already stored in the coefficient storage means 111. This makes it possible to reduce the overall time required for one-dimensional inverse transform processing of coefficient matrices corresponding to a plurality of blocks.

In the invention of claim 5, the number of components forming a subsequence is N/2, and the conversion constant storage means 131 stores N/2 components in the first half and N/2 components in the second half of the corresponding column of the constant matrix. It is divided into N/2 pieces and outputted, and input to each of the N/2 calculation means 133 of the first conversion means 132. Further, in each of these calculation means 133, the calculation processing corresponding to the one-dimensional orthogonal transformation is divided into a multiplication operation by the multiplication means 134, an integration operation by the integration means 135, and a holding operation by the holding means 136.

Here, each of these operations, the operation of inputting the components of the coefficient matrix and the conversion constant to the arithmetic means 133, and the operation of outputting the arithmetic results by each arithmetic means 133 can be executed independently. It is possible to perform high-speed processing by vibrating the operation. Also, N/
Since the first conversion means 132 is configured using two calculation means 133, it is also possible to reduce the size of the circuit.

In the invention of claim 6, the calculation control means 137 controls the number of executions of the calculation processing by the multiplication means 134 and the integration means 135, and performs calculations according to the number of effective subsequences included in each column of the coefficient matrix. The one-dimensional inverse transformation result of each column can be obtained by the number of times.

In the invention of claim 7, by instructing the address generated by the address generation means 143 as the storage location of the first conversion means 132, the conversion result holding means 14
1 stores a transposed matrix obtained by transposing a matrix resulting from one-dimensional inverse transformation. Therefore, in the second conversion means 151, 1
It is possible to eliminate the need for transposing the dimensional inverse transformation results.

In the invention of claim 8, the detection means 144 and the output instruction means 145 extract an effective subsequence including an effective coefficient from the one-dimensional inverse transformation result held in the transformation result holding means 141, and perform the second transformation. By inputting it to the means 151, the amount of calculation in the second converting means 151 can be reduced.

In the invention of claim 9, the input means 161:
The one-dimensional inverse transformation result held in the transformation result holding means 141 is input to the first transformation means 132, and the first transformation means 13
2, by performing the calculation equivalent to the orthogonal transformation again, the second transformation means 151 is made unnecessary, and the overall circuit scale of the inverse orthogonal transformation circuit is reduced.

In the invention of claim 10, the detection means 144 and the output instruction means 145 extract an effective subsequence including effective coefficients from the one-dimensional inverse transformation result held in the transformation result holding means 141, and the input means 161 This extracted effective subsequence is input to the first conversion means 132. As a result, the circuit scale is reduced and the first conversion means 132
It is possible to reduce the amount of calculation in the second-dimensional orthogonal transformation process performed by .

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an embodiment of an image data restoration device using the inverse orthogonal transform circuit of the present invention.

FIG. 3 shows an inverse D transform circuit according to an embodiment of the present invention.
An embodiment of the configuration of the first-dimensional orthogonal transform unit of the CT transform unit is shown.

FIG. 5 shows a detailed configuration of an arithmetic processing section which is an embodiment of the first conversion means of the present invention.

FIG. 9 shows an inverse D transform circuit according to an embodiment of the present invention.
An example configuration of a second-dimensional orthogonal transform unit of the CT transform unit is shown.

FIG. 10 shows the configuration of an inverse DCT transform section which is another embodiment of the inverse orthogonal transform circuit of the present invention.

Here, the correspondence between FIG. 1 and the embodiment will be explained.

The coefficient storage means 111 corresponds to the buffer 233.

The read control means 120 corresponds to the read control section 313.

The determining means 121 corresponds to the zero detecting section 331.

The address holding means 122 corresponds to the column address holding section 332.

The conversion constant storage means 131 corresponds to the constant memory 311.

The first conversion means 132 corresponds to the arithmetic processing section 312.

The calculation means 133 corresponds to the calculation circuit 401.

Multiplying means 134 corresponds to multiplier 421.

The integrating means 135 includes an adder 431 and a register 432.4.
33 and multiplexer 434.

The holding means 136 corresponds to the registers 441 and 442.

The calculation control means 137 corresponds to the conversion control section 405.

The conversion result holding means 141 corresponds to the buffer 234.

The write control means 142 corresponds to the write control section 314.

Address generation means 143 corresponds to address latch 341 and write address generation section 342.

The detection means 144 is a zero detection unit 531 of the readout control unit 513.
corresponds to

The output instruction means 145 corresponds to the readout control section 513.

The second transformation means 151 corresponds to the orthogonal transformation section 232.

The input means 161 includes the selector 601 and the read control unit 5
It corresponds to 13.

Assuming that the above-mentioned correspondence exists, the configuration and operation of the embodiment will be described below.

In FIG. 2, the image data restoration device includes a decoding table 211
a decoding unit 210 equipped with a quantization matrix storage unit 22
1, an inverse DCT including a first-dimensional orthogonal transform unit 231, and a second-dimensional orthogonal transform unit 232.
The converting unit 230 is configured to restore image data for each block of 8 pixels×8 pixels based on the input encoded data.

The decoding unit 210 described above decodes the encoded data based on the correspondence between the encoded data and the decoded data stored in the decoding table 211, restores the quantization coefficient DQt+ as an 8-by-8 matrix, and performs the inverse The signal is input to the quantization section 220.

This inverse quantization unit 220 includes a quantization matrix storage unit 22
Based on the quantization matrix VyH (see Figure 13) stored in 1, the DCT coefficients are restored by dequantizing each component of the quantization coefficient DQLI, and each component of this OCT coefficient is sequentially is input to the inverse DCT transform unit 230. At this time, the inverse quantization section 220 sequentially outputs the components of each column starting from the first column of the DCT coefficients, starting from the component corresponding to the first row, and inputs them to the inverse DCT transformation section 230.

The above-described DCT coefficients are input to the first-dimensional orthogonal transform unit 231 of the inverse DCT transform unit 230 via the buffer 233 . Further, the transformation result by the first-dimensional orthogonal transformation unit 231 is input to the second-dimensional orthogonal transformation unit 232 via the buffer 234, and the second-dimensional orthogonal transformation unit 23
The conversion result obtained by step 2 is output as one block of image data via the buffer 235.

The buffer 233 described above is configured to store each component of the DCT coefficient at an address specified by a column number and a row number. In addition, the buffer 234 and the buffer 23
Similarly, 5 is a configuration in which each component of the transformation result by the first-dimensional orthogonal transformation unit 231 and the transformation result by the second-dimensional orthogonal transformation unit 232 is stored at an address specified by the respective column number and row number. It becomes.

Hereinafter, an address indicating an area in which components for one column of a matrix are stored will be referred to as a column address, and an address indicating an area in which components for one row are stored will be referred to as a row address.

FIG. 3 shows a configuration diagram of the first-dimensional orthogonal transform unit 231.

In FIG. 3, a constant memory 311 stores the above-mentioned conversion constant A, and there is a correspondence between each component of the DCT coefficient read out from the buffer 233 and the conversion constant A read out from the constant memory 311. The component to be calculated is the arithmetic processing unit 3.
12. In addition, the zero detection section 3
31, column address holding section 332, counter 333, and read address generation section 334 constitute a read control section 313, and this read control section 313 controls the read operation of data from the buffer 233 and constant memory 311 described above. is controlled. Further, the address latch 341 and the write address generation section 342 constitute a write control section 314, and the write control section 314 controls the operation of writing the output of the arithmetic processing section 312 described above to the buffer 234. will be held. Further, the above-described read control section 313 and write control section 314 are configured to operate according to instructions from the arithmetic processing section 312.

The zero detection unit 331 of the readout control unit 313 operates in parallel with inputting each component of the DCT coefficient to the buffer 233 described above, and inputs each column of the DCT coefficient to the first half corresponding to the first to fourth rows. The first half component and the second half component corresponding to the fifth to eighth rows are divided, and "0" is set for each of the first half and the second half.
It is configured to perform detection. In addition, this zero detection section 33
1 contains 1-bit information indicating whether or not at least one effective coefficient is included as a detection result for each column, and 1-bit information indicating whether or not the latter half contains an effective coefficient. Output. For example, if all the components in both the first half and the second half are invalid coefficients, the detection result is "01".
If all the components in the second half are invalid coefficients, "'11" may be output, and in other cases, "10" may be output.

The detection result by the zero detection unit 331 is input to the column address holding unit 332, and the column address holding unit 332 determines which column address corresponds to the column address of the buffer 233 corresponding to the column of DCT coefficients including at least one effective coefficient. A flag indicating whether all the components in the latter half of the column are invalid coefficients is held.

For example, when a logic "1" is input as the first bit of the detection result described above, the column address holding section 332 stores the corresponding column of the DCT coefficient in the buffer 232.
It is sufficient to hold the column address indicating the area No. 3 and the second bit of the detection result as a flag.

Further, the output of the zero detection section 331 described above is transmitted to the counter 33.
3, and this counter 333 counts the number of columns of DCT coefficients that include at least one effective coefficient. For example, this counter 333 may be configured to perform an operation of adding a counted value in accordance with the first bit of the detection result described above.

In this way, one block of D is sent to the buffer 233.
In parallel with the input operation of CT coefficients, an operation of counting columns including valid coefficients and an operation of holding column addresses and flags corresponding to the corresponding columns are performed.

For example, by decoding the encoded data corresponding to the quantization coefficient 1) ou shown in FIG. will be restored.

When each component of this DCT coefficient is sequentially input to the buffer 233, the above-mentioned zero detection unit 331 outputs the detection result "10" corresponding to the first column, and the second
The detection result “11°” is output corresponding to the column, and the third column ~
The detection result “°01” is output corresponding to the eighth column. In this case, as shown in Table 1, the column address C1 corresponding to the first column and the column address C2 corresponding to the second column are held in the column address holding unit 332, and the counter 33
The count value of 3 is r2J.

Upon completion of the operation of storing one block worth of DCT coefficients in the first table buffer 233, the arithmetic processing unit 312 starts operating, outputs the data request signal RED, and the read control unit 31
3 to start the read operation.

In response to this, the read address generation unit 334 of the read control unit 313 first reads out the first column address and flag held in the column address holding unit 332, and inputs this flag to the arithmetic processing unit 312 described above. .

Next, the read address generation unit 334 sequentially generates a row address specifying each row of the buffer 233 in response to the input of the data request signal RED described above, and assigns the column address read from the column address holding unit 332 to this row. The address is added and output, and input to the buffer 233. In response, each component of the corresponding column of DCT coefficients stored in the buffer 233 is sequentially output from the buffer 233,
The data is input to the arithmetic processing unit 312.

Also, at this time, the read address generation unit 334 sequentially generates column addresses specifying each column of the conversion constant A stored in the constant memory 311, and in synchronization with the data request signal RED described above, reads the constant memory Enter +7311. Accordingly, each column of the conversion constant A stored in the constant memory 311 is read out sequentially, and a vector a (hereinafter referred to as column component a) consisting of the components of this one column is sent to the arithmetic processing unit 312. is input.

In this way, in response to the data request signal RED, the column components corresponding to the above-mentioned column addresses of the DCT coefficients are sequentially read out one by one from the buffer 233, and each column of the conversion constant A is read out from the constant memory 311. are read out sequentially starting from the first column.

Further, if the flag read from the column address holding unit 332 described above is logic “1”, the read address generation unit 334 generates a DC signal when the above-described operation is repeated four times.
The operation of generating read addresses for the corresponding columns of T coefficients is completed. Therefore, in this case, only the first four components of the corresponding column of DCT coefficients are read out from the buffer 233 and input to the arithmetic processing unit 312 along with the column component a corresponding to the conversion constant 60.

On the other hand, if the flag is logic "0", the read address generation unit 334 completes the read operation of the corresponding column of DCT coefficients after repeating the above operation eight times. Therefore, in this case, all eight components of the corresponding column of the DCT coefficients are read out from the buffer 233 and input to the arithmetic processing unit 312 along with the corresponding column component a of the conversion constant A.

In this way, after the read operation of the corresponding column of DCT coefficients is completed, the read address generation section 334 performs the read operation of the next column address and flag from the column address holding section 332, and similarly, A read address to buffer 233 and constant memory 311 is generated.

Further, as described above, the counter 333 subtracts the count value every time the column address is read out, and when the count value reaches 101, outputs the end signal LEND.
The arithmetic processing unit 31 indicates that the reading operation for one block has been completed.
Notify 2.

Therefore, the arithmetic processing unit 312 has one block worth of DCT.
Only the components of the columns containing significant coefficients in the coefficients are input.

FIG. 5 shows a detailed configuration of the arithmetic processing section 312 described above.

In FIG. 5, a register 411, a multiplier 421, a register 422, an adder 431, registers 432, 433, a multiplexer 434, and registers 44 and 442 constitute an arithmetic circuit 401a. In addition, the arithmetic circuit 401
b, 401c, and 401d are each of this arithmetic circuit 4
It is configured similarly to 01a.

However, in the figure, registers 411, 422432 .
433, 441, and 442 are indicated by the symbol R.

Each component of the DCT coefficient read from the buffer 233 described above is inputted to each of the arithmetic circuits 401a, . . . , 401d described above via the register 402. Furthermore, the first four components of column component a, which is made up of one column of conversion constant AO components read from constant memory 311, are input to boat 1 of selector 403, and the latter four components are input to boat 2. It has been entered. This selector 403 is configured to select input to either port 2, and each selected component is input to each register 411 of the four arithmetic circuits 401a, . . . , 401d described above. be done.

Furthermore, the outputs of the respective registers 441 and 442 of the above-mentioned arithmetic circuits 401a, . . . , 401d are input to a multiplexer 404.
The output of 04 is input to the buffer 234 as the output of the arithmetic processing section 312.

Each of these arithmetic circuits 401a, . . . , 401d, the above-mentioned selector 403, and multiplexer 40
4 is configured to operate in response to instructions from the conversion control unit 405.

In addition, hereinafter, in each of the arithmetic circuits 401a, -, 401d, the operation of inputting the corresponding component of the conversion constant A to the register 411 will be referred to as the operation of stage (2), and the multiplier 4
The multiplication operation by the adder 431 and the registers 432 and 433 is called the operation of stage ■, and the operation of storing the cumulative addition result in the registers 441 and 442 is called the operation of stage ■. It is called. Further, the operation in which the multiplexer 404 selects and outputs either of the registers 441 and 442 is referred to as the operation of stage (2).

FIG. 6 shows a flowchart of arithmetic processing by this arithmetic processing section 312.

Here, when the arithmetic processing unit 312 starts arithmetic processing, the register 4 of each arithmetic circuit 401a, . . . , 401d
The contents of 32, register 433, and buffer 234 mentioned above have been cleared.

First, the conversion control unit 405 outputs the data request signal RED and inputs the DCT coefficient component and the column component a of the conversion constant A corresponding to this component (step 501). At this time, the conversion control unit 405 sets the boat 1 to the selector 403.
In response, the first four conversion constants of the column component a described above are selected by each calculation circuit 401a, . . .
, 401d (step 502).

Next, the multiplier 421 of each arithmetic circuit 401a, ..., 401d uses each of the four conversion constants held in the corresponding register 411 and the D
Multiplication with the CT coefficient is performed, and the multiplication result is stored in the corresponding register 422 (step 503).

In this way, the j-th component d ji of the first column of the DCT coefficients and each component (A
r = , .

Next, the conversion control unit 405 controls each arithmetic circuit 401a,...
・The register 432 is added to the multiplexer 434 of 401d.
Instruct the selection. Therefore, each arithmetic circuit 401a,
-2401d adder 431 adds the multiplication result stored in register 422 and the contents of register 432, and stores this addition result in register 432 (step 504).

Next, the conversion control unit 405 sends the boat 2 to the selector 403.
In response, each of the four conversion constants in the second half of column component a described above is selected in each arithmetic circuit 401.
a,...,40]d (step 505
). Further, the multiplier 421 of each arithmetic circuit 401a, . . . , 401d performs multiplication processing in the same manner as step 503 described above (step 506).

In this way, the j-th component d ji of the first column of the DCT coefficient is multiplied by the four components (A s = , ..., Asj) in the second half of the j-th column of the conversion constant A. carried out,
The j-th term of equations (6) to (9) described above is calculated.

Also, at this time, the conversion control unit 405 controls each arithmetic circuit 40
Instructs the multiplexer 434 of 1a, . . . , 401d to select the register 433. As a result, the adder 431 of each arithmetic circuit 4ula, . ).

Next, the conversion control unit 405 determines whether or not the flag input from the readout control unit 313 is a logic "1" degree (step 508), and in the case of an affirmative determination in this step 508, the process proceeds to step 509. , step 5 mentioned above
It is determined whether steps 01 to 508 have been repeated a number of times (four times) corresponding to half the number of lines in one block. On the other hand, in the case of a negative determination in step 508, the process proceeds to step 510, and the steps 501 to 5 described above are performed.
It is determined whether or not step 08 has been repeated a number of times (eight times) corresponding to the number of rows in one block.

In the case of a negative determination in step 509 and step 510 described above, return to step 501 and perform the next DCT.
The component of the coefficient and the column component a of the conversion constant A corresponding to this component are read, and the above-mentioned arithmetic processing is repeated.

In this way, each term of formulas (2) to (5) and each term of formulas (6) to (9) described above are calculated alternately, and these terms are cumulatively added alternately. .

On the other hand, in the case of affirmative determination in step 509 and step 510 described above, the conversion control unit 405 controls the registers 432, 43 of each arithmetic circuit 401a, . . . , 401d.
Store the contents of 3 in the corresponding registers 44 and 442 (
Step 511).

Furthermore, the conversion control unit 405 first instructs the multiplexer 404 to sequentially output the contents of the register 441 of each arithmetic circuit 401a, . . Accordingly, the multiplexer 404 first uses the above-mentioned equation (
The calculation results corresponding to 2) to (5) are output, and then
The calculation results corresponding to equations (6) to (9) are output (step 512).

Here, if the flag is logic "'1°", DCT
All the components in the latter half of the corresponding column of coefficients are invalid coefficients. Therefore, steps 501 to 507 described above
By repeating this four times and performing calculations on the components in the first half of this sequence, it is possible to obtain the result of one-dimensional DCT inverse transformation of this sequence of DCT coefficients.

On the other hand, when the flag is at the logic "'0°", the operations corresponding to equations (2) to (9) are performed by repeating steps 501 to 507 described above eight times.

Therefore, steps 509 and 510 described above
The contents of the register 432 and the register 433 in the case of an affirmative determination in are expressed by the above formulas (2) to (9).
The one-dimensional inverse DCT transform result of the first column of these DCT coefficients is the value of each equation.
2 are sequentially output. Also, at this time, the conversion control unit 405 outputs a write signal WRT in synchronization with the output of the conversion result described above, and instructs the write control unit 314 to perform a write operation to the buffer 234.

Next, the conversion control unit 405 determines whether the end signal LEND from the counter 333 of the read control unit 313 is at logic "1"' (step 513).

In the case of a negative determination in step 513, the conversion control unit 405 sets the initial value rOJ in the register 432 and register 433 of each arithmetic circuit 401a, . . . 401d (step 514), and returns to step 501.
Starts conversion processing for the next column. On the other hand, in the case of an affirmative determination in step 513, it is determined that the conversion process for one block has been completed, and the process is terminated.

Here, each of the operations of stages ■ to ■ mentioned above is
can be executed independently of each other. Therefore, each step of Step 502 to Step 504, each step of Step 505 to Step 507, and Step 511 described above are performed.
and step 512 can be pipelined and controlled.

Figure 7 shows the DCT coefficients shown in Figure 4 as one-dimensional inverse DC
In the case of T-transformation, the manner in which each of the operations from stage 1 to stage 2 described above is pipelined and processed will be described.

In FIG. 7, the numbers in the leftmost column indicate the number of steps in the pipeline. Also, the symbol ROI is register 4
01, symbol R11,..., R14 and symbol R
21,...5 R24 represents each arithmetic circuit 401a, -,
Each of register 411 and register 422 of 401d is shown. Similarly, symbols R31,..., R3
4 and symbols R35..., R38 are registers 432
and registers 433, symbols R41,..., R
44 and symbols R45,..., R48 are register 4
41 and register 442 are shown.

As shown in the column corresponding to stage (2) in FIG. 7, in the odd-numbered steps, each component of the DCT coefficient is input, and the conversion constant A Each component in the first half of the corresponding column component a is inputted, and each component in the second half of this column component a is inputted in an even-numbered step.

Further, from the second step onwards, as shown in the column corresponding to stage (2), the multiplication process of step 503 and the multiplication process of step 506 described above are performed alternately in parallel with the operation of stage (2).

In addition, from the third step onward, as shown in the column corresponding to stage (2), in the odd-numbered steps, the addition process of step 504 described above is performed, and in the even-numbered steps, the addition process of step 507 described above is performed. The processing is
This is carried out in parallel with the operations of stage ■ and stage ■.

As shown in Table 1, the flag corresponding to the first column of the DCT coefficients shown in FIG. All eight components of the first column are input.

In this case, the 8th component DI in the first column of the DCT coefficient
The multiplication processing and addition processing for l+ are performed in parallel with the input of the second column component of the DCT coefficient and the conversion constant A, and in the 17th step and the 18th step,
The one-dimensional inverse DCT transformation results are sent to each arithmetic circuit 401a, .
..., register 441 and register 442 of 401d
(Step 51, see stage ① in Figure 7).

Further, in the 18th step to the 25th step, the output processing in step 512 is performed, and the one-dimensional inverse DCT
The conversion results (y, . . . , Y, .) are sequentially output (see stage 3 in FIG. 7).

Similarly, a one-dimensional inverse DCT transform process is performed on the second column of DCT coefficients, and in the 25th and 26th steps, the operation of stage (2) is performed, and in the 26th to 33rd steps, the operation of stage (2) is performed. An action is taken.

A method for storing the transposed matrix 1 (TI) obtained by transposing the rows and columns of the transformation result H calculated in this manner in the buffer 234 will be described below.

The column address read from the column address holding unit 332 by the read address generation unit 334 shown in FIG.
addressr of the write control unit 314;

341. Further, in response to the input of the write signal WRT described above, the write address generation unit 342
A write address is generated based on the column address held in the address latch 341 described above.

This write address generation unit 342 first converts the above-mentioned column address into a row address corresponding to a row having the same number as the column number corresponding to this column address ζ. In addition, the write address generation unit 342 generates a column address that specifies each column in synchronization with the write signal WRT described above, adds this column address to the row address described above to generate a write address, and buffers the buffer. 234.

Therefore, the conversion results corresponding to the first column of DCT coefficients output by the arithmetic processing unit 312 are sequentially stored in the area corresponding to the first row of the buffer 234.

In this way, the transposed matrix H1 of the transformation result H1 is stored in the buffer 234 and passed to the second-dimensional orthogonal transformation unit 232.

FIG. 8 shows a transposed matrix HT1 corresponding to the DCT coefficients shown in FIG. In FIG. 8, the effective coefficients included in the transposed matrix H'' are shown with subscripts indicating column numbers and row numbers; in the transposed matrix H'', DC
Only rows corresponding to columns containing T coefficients of effective coefficients are rows containing effective coefficients.

The second-dimensional orthogonal transform unit 232, as shown in FIG.
The reading control section 513 includes another zero detection section 531 in place of the zero detection section 331 of the first-dimensional orthogonal transformation section 231 shown in FIG.

This zero detection unit 531 performs zero detection in parallel with the input of each column of the transformation result H, to the buffer 234 described above, and performs the zero detection described above for each column of the transposed matrix 1('' of the transformation result H1). It is configured to output a detection result similar to that of the section 331.

For example, each value of the component in each column of the conversion result H1 is "
0'' is created, the logical sum of this bitmap is sequentially calculated, and this result is output as a detection result indicating whether each column of the transposed matrix HT' contains an effective coefficient. do.

Similarly, the logical sum of the bitmaps corresponding to the 5th to 8th columns of the conversion result H3 is calculated, and the inverted logic of this result is calculated to determine whether the effective coefficient is included in the latter half of each column of the transposed matrix H71. What is necessary is to output it as a detection result indicating whether or not. In this case, similarly to the zero detecting unit 331 described above, the zero detecting unit 531 outputs a detection result of “01” when all of the components in both the first half and the second half are invalid coefficients; When all the components of are invalid coefficients, °'11' is output, and in other cases, 'i o' is output.

For example, when the zero detection unit 531 performs zero detection processing on the transposed matrix H'' shown in FIG. Addresses 01 to C8 and the flag “1°” indicating that all components in the latter half of each column are invalid coefficients,
It is held in the column address holding unit 332, and also stored in the counter 3.
The count value of 33 is FB.

Table 2 Based on the column addresses held in the column address holding unit 332 in this way, a read address is generated by the read address generation unit 334, and the calculation is performed in the same manner as the orthogonal transformation process for the engineering dimension. The processing unit 312 performs second-dimensional orthogonal transformation processing. In addition, in the same manner as the first-dimensional orthogonal transformation processing described above, the write control unit 314 transfers the calculation result by the calculation processing unit 312 to the buffer 23.
5, the transposed matrix ((
T2 is stored and output as restored data.

As described above, the arithmetic circuit 40 includes a multiplier and an adder that operate independently, and a register that connects them.
1 constitutes an arithmetic processing unit 312 that performs one-dimensional inverse DCT transformation processing. In addition, the zero detection unit 331
Zero detection is performed in units of half of the components of one column of DCT coefficients, and based on this detection result, the read operation from buffer 233 and constant memory 311 is controlled.

As a result, only the columns containing effective coefficients in one block of DCT coefficients are processed by the arithmetic processing unit in half of one column.
12, the arithmetic processing unit 312 can efficiently pipeline and process the operations of stages 1 to 2 without causing any waiting time between the stages. For example, when the DCT coefficients shown in FIG. (See Figure 7)
.

In this way, it is possible to perform orthogonal transformation processing at high speed using a small-scale orthogonal transformation circuit, and it is possible to downsize the image data restoration device and speed up the restoration processing.

Note that if the buffer 233 shown in FIG. 1 about manually calculated DCT coefficients
It is possible to perform orthogonal transformation operation for the dimension, and the time required for restoration processing can be further shortened.

Similarly, if the buffer 234 has a capacity corresponding to the data amount of the conversion result for two blocks, the buffer 234
The input operation of the transformation result and the second-dimensional orthogonal transformation process can be performed in parallel, and the time required for the restoration process can be further shortened.

Furthermore, in the inverse DCT conversion section 230, the buffer 234
The first-dimensional conversion result stored in the arithmetic processing unit 31
2, and one arithmetic processing unit 312 may be used to perform the first-dimensional orthogonal transformation processing and the second-dimensional orthogonal transformation processing.

For example, as shown in FIG. 10, the readout control section 513 of the second-dimensional orthogonal transform section 232 shown in FIG. 9 is added to the first-dimensional orthogonal transform section 231 shown in FIG. 601, the output of either the buffer 234 or the buffer 233 may be input to the arithmetic processing unit 312.

In this case, the selector 601 performs the first-dimensional orthogonal transformation processing with the buffer 233 and the arithmetic processing unit 312 connected, and after the first-dimensional orthogonal transformation processing is completed, the selector 601 is switched to 234 and the arithmetic processing unit 312 are connected. Further, the read control unit 513 controls the read operation of data from the buffer 234 and the constant memory 311, and manually inputs each component of the conversion result [4” and the corresponding conversion constant to the arithmetic processing unit 312.
Orthogonal transformation processing for the second dimension is performed, and after completion of the orthogonal transformation processing for the second dimension, the DCT coefficients of the next block are processed.

In this way, by configuring the first-dimensional orthogonal transformation process and the second-dimensional orthogonal transformation process using one arithmetic processing unit 312, it is possible to further reduce the circuit scale of the inverse DCT transformation unit. I can do it.

〔Effect of the invention〕

As described above, according to the present invention, subsequences including effective coefficients are extracted from a matrix consisting of DCT coefficients, and orthogonal transformation processing is performed only on these subsequences.
It is possible to reduce the amount of calculation for inverse DCT transformation processing, and to execute inverse DCT transformation processing at high speed with a small circuit, thereby making it possible to downsize the image data restoration device and shorten the time required for restoration processing. can.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of an image data restoration device using the inverse orthogonal transform circuit of the present invention, and Fig. 3 is an embodiment of the inverse orthogonal transform circuit of the present invention. A certain reverse DC
A configuration diagram of the first-dimensional orthogonal transform section of the T transform section, FIG. 4 is a diagram showing an example of restored DCT coefficients, and FIG. 5 is a calculation processing section that is an embodiment of the first transform means of the present invention. 6 is a flowchart showing arithmetic processing, FIG. 7 is an explanatory diagram of pipeline processing, FIG. 8 is a diagram showing an example of the transform result HT+, and FIG. 9 is an inverse orthogonal transform circuit of the present invention. FIG. 10 is a block diagram of the second-dimensional orthogonal transform section of the inverse DCT transform circuit which is an embodiment of the present invention. FIG. 11 is a block diagram of the inverse DCT transform section which is another embodiment of the inverse orthogonal transform circuit of the present invention. The configuration diagram of the image compression device, Figure 12 is an explanatory diagram of the blocks, Figure 13 is a diagram showing DCT coefficients, Figure 14 is a diagram showing quantization matrix VTH, and Figure 15 is a diagram showing quantization coefficients I)ou. FIG. 16 is an explanatory diagram of a zigzag scan, and FIG. 17 is a configuration diagram of a conventional restoration device. In the figure, 11 is coefficient storage means, 120 is readout control means, 121 is determination means, 122 is address holding means, 131 is conversion constant storage means, 132 is first conversion means, 133 is calculation means, 134 is multiplication means , 135 is an integration means, 136 is a holding means, 137 is an arithmetic control means, 141 is a conversion result holding means, 142 is a write control means, 143 is a detection means, 144 is an address generation means, 151 is a second conversion means, 161 is an input means, 210.811 is a decoding unit, 211 is a decoding table, 220.821 is an inverse quantization unit, 221 is a quantization matrix storage unit, 230.831 is an inverse DCT transformation unit, 23 and 232 are orthogonal transformation units, 233, 234, and 235 are buffers, 311 is a constant memory, 312 is an arithmetic processing unit, 313, 513 is a read control unit, 314 is a write control unit, 33 and 531 are zero detection units, 332 is a column address holding unit, 333 is a counter, 334 is a read address generation section, 341 is an address latch, 342 is a write address generation section, 401 is an arithmetic circuit, 402, 411, 422, 432, 433 degrees, 442 is a register, 403, 601 is a selector, 404. 434 is a multiplexer, 405 is a conversion control unit, 1 is a DCT conversion unit, 1 is a linear quantization unit, and 1 is an encoding unit.

Claims (1)

[Claims] 1) Image data is divided into two blocks for each block consisting of N×N pixels.
In an inverse orthogonal transform method of a restoration device, the image data is restored by decoding an input code obtained by quantizing and then encoding a result of dimensional orthogonal transform, inversely quantizing it, and performing two-dimensional inverse orthogonal transform to restore image data. Divide each column of an N-by-N coefficient matrix, which is the result of two-dimensional orthogonal transformation of a block of data, into subsequences each containing a predetermined number of components, and from among the subsequences, select valid ones with values other than zero. Extract a subsequence containing coefficients, perform an operation equivalent to one-dimensional orthogonal transformation on each component of the extracted subsequence, and apply one-dimensional inverse transformation to the operation result corresponding to the extracted subsequence. An inverse orthogonal transformation method, characterized in that the result is output as a component of a corresponding column, and image data is obtained by performing a second-dimensional orthogonal transformation on the one-dimensional inverse transformation result. (2) The inverse orthogonal transform method according to claim 1, wherein the one-dimensional inverse transform result of each column is output as a component of a corresponding row of a transposed matrix. (3) Decode the input code obtained by quantizing and encoding the result of two-dimensional orthogonal transformation of image data for each block of N×N pixels, dequantizing it, and performing two-dimensional inverse orthogonal transformation, In an inverse orthogonal transform circuit of a restoration device that restores image data, a coefficient storage means (111) stores each component of the input coefficient matrix as a matrix of N rows and N columns, and input to the coefficient storage means (111). determining means (121) for determining whether each of the subsequences constituting each column of the coefficient matrix is an effective subsequence including an effective coefficient; and an address holding means (122) for holding an address of the coefficient storage means (111) corresponding to the subsequence set as readout control means (120) for instructing the means (111) to output each component included in the effective subsequence;
and a constant matrix of N rows and N columns consisting of transformation constants corresponding to each component of the coefficient matrix, and the coefficient storage means (1
conversion constant storage means (131) for outputting the conversion constants included in the columns of the constant matrix corresponding to the components of the coefficient matrix output by step 11); 131) performs an operation equivalent to orthogonal transformation on the transformation constant output from a first conversion means (132) that outputs a one-dimensional inverse conversion result of a column; a conversion result holding means (141) that holds the output of the first conversion means (132); and a conversion result holding means (141) that holds the output of the first conversion means (132); a write control means (142) for specifying a storage location in the transformation result holding means (141) of a one-dimensional inverse transformation result corresponding to a corresponding column of the coefficient matrix according to the address of the coefficient matrix; An inverse orthogonal transform circuit comprising: second transform means (151) that performs second-dimensional orthogonal transform based on the one-dimensional inverse transform result held in the means (141). (4) In the inverse orthogonal transform circuit according to claim 3, the coefficient storage means (111) has a capacity to store coefficient matrices corresponding to each of the two blocks, and the coefficient storage means (111) An inverse orthogonal transform circuit characterized in that the first transform means (132) performs a one-dimensional inverse transform operation in parallel with the input of the coefficient matrix. (5) In the inverse orthogonal transform circuit according to claim 3, the determining means (121) is configured to determine whether or not each subsequence formed from N/2 components is a valid subsequence; The conversion constant storage means (131) alternately outputs N/2 conversion constants in the first half and N/2 conversion constants in the latter half of the corresponding column in accordance with the output of each component of the coefficient matrix. The first conversion means (132) has N/2 calculation means (1
33), each of the N/2 arithmetic means (133) has the following functions: an input coefficient matrix component and each component alternately outputted from the conversion constant storage means (131) corresponding to the input coefficient matrix component. a multiplication means (134) that multiplies each of the conversion constants; an integration means (135) that integrates each of the multiplication results alternately obtained by the multiplication means (134); 1. An inverse orthogonal transform circuit comprising: a holding means (136) for holding each of the obtained integration results. (6) In the inverse orthogonal transformation circuit according to claim 5, the first transformation means (132) comprises the address holding means (12).
2) arithmetic control means for controlling the number of executions of arithmetic processing by the multiplication means (134) and the accumulation means (135) according to the address of the effective subsequence included in each column of the coefficient matrix held in (137) An inverse orthogonal transform circuit characterized by comprising: (137). (7) In the inverse orthogonal transform circuit according to claim 3, the write control means (142) includes the first transform means (132).
Address generation means (143) for generating an address of the transformation result holding means (141) corresponding to a corresponding row of a transposed matrix obtained by transposing the matrix consisting of the one-dimensional inverse transformation result, in accordance with the operation result obtained by An inverse orthogonal transform circuit comprising: (8) In the inverse orthogonal transform circuit according to claim 7, a detection means ( 144), and the conversion result holding means (141) according to the detection result by the detection means (144).
), the second transformation means (151) comprises: An inverse orthogonal transform circuit characterized in that it is configured to perform a second-dimensional orthogonal transform process on the partial sequence output from the transform result holding means (141). (9) In the inverse orthogonal transform circuit according to claim 7, the one-dimensional inverse transform result stored in the transform result holding means (141) is transferred to the first transform means (instead of the second transform means (151)). 132) and input means (161) for instructing the transformation constant storage means (131) to output a corresponding transformation constant. (10) The inverse orthogonal transform circuit according to claim 9, further comprising detecting means ( 144), and the detection means (144);
), the conversion result holding means (1
41), the input means (161) comprises an output instruction means (145) for instructing the output of a subsequence including an effective coefficient from each column of the matrix of the one-dimensional inverse transformation result, and the input means (161) Conversion result holding means (1
41), the subsequence outputted by the first converting means (
132).