JPH04132465A - Composite synchronizing signal separator circuit - Google Patents

Abstract

PURPOSE:To output a horizontal synchronizing signal generated in itself even when a composite synchronizing signal is tentatively missing by using a counter counting one period of the horizontal synchronizing signal so as to combine a decoder decoding the count and as RS latch thereby generating three kinds of pulses. CONSTITUTION:The title circuit consists of a trigger pulse generating circuit 3 generating a trigger pulse synchronously with a rising edge of a composite synchronizing signal inputted from an input terminal 1, a counter 4 receiving a clock from an input terminal 2 and counting one period of the horizontal synchronizing signal, a decoder 5 selecting the count, RS latches 6-8 generating a pulse having an optional period, an AND circuit 9 and an OR circuit 10 generating a reset signal of the counter 4 and a trigger pulse in the case of missing the composite synchronizing signal, a latch circuit 12 outputting the horizontal synchronizing signal and an OR circuit 11 latching the clock with the input composite synchronizing signal, and the horizontal synchronizing signal is outputted from an output terminal 13. Thus, even when an input signal is missing, a signal synchronously with the horizontal synchronizing signal of the inputted composite synchronizing signal is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal separation circuit that separates a horizontal synchronization signal from a video composite synchronization signal. The present invention relates to a composite synchronization signal separation circuit that outputs a signal synchronized with a horizontal synchronization signal of a synchronization signal.

[Conventional technology]

Generally, the video composite synchronization signal is as shown in FIG.
Horizontal synchronization signals 21 with different frequencies and pulse widths. It is composed of three types of signals: a vertical synchronization signal 23 and an equalization pulse signal 22.

Conventionally, this type of composite synchronization signal separation circuit has been constructed using analog technology, for example, as shown in FIG.
1 and a resistor R1 was used.

The composite synchronization signal in Figure 3 has a frequency of 15.734 KHz and a pulse width of 4.1 when the television system is the NTSC system.
Horizontal synchronization signal 21, which is 9 to 5.71 μsec, and 59
．． During the vertical blanking period T1 with a frequency of 94 Hz, the frequency is twice that of the horizontal synchronizing signal, and the pulse width is 26.4~26.4 Hz.
The vertical synchronization signal 23 is 28μsec and the pulse width is 2
．． It is composed of equalization pulse signals 22 located before and after the vertical synchronization signal with a period of 29 to 2.54 μsec.

Further, if one period of the horizontal synchronization signal is IH, the vertical blanking period is a period of 9H, the vertical synchronization signal is 3H, and the equalization pulse is 3H before and after the vertical synchronization signal.

When separating the horizontal synchronization signal from this composite synchronization signal, the composite synchronization signal is inputted from the input terminal 1 using the differentiation circuit shown in FIG. 4, and the horizontal synchronization signal is output from the output terminal 13 through the differentiation circuit.

In this circuit, by arbitrarily selecting the time constant CR, when an input signal is applied, there is no charge in the capacitor C1 at the rising edge of the synchronization signal, so an instantaneous current flows in the resistor R1.
Capacitor C1 is charged with time constants C and R. vice versa,
At the falling edge of the synchronization signal, the charge stored in the capacitor C1 is discharged, and the output signal 13 shown in FIG. 5 is obtained. This output signal is input to the amplification stage and amplified.

[Problem to be solved by the invention]

In recent years, televisions and VTRs have been using integrated circuit components (ICs).
), and the share of digital ICs is increasing. These ICs take in this composite synchronization signal, send necessary signals (vertical synchronization signal or horizontal synchronization signal) to each functional system within the IC, and perform signal processing or various controls in synchronization with these signals. ing. Therefore, when incorporating a composite synchronization signal separation circuit into an IC, it is difficult to incorporate it into the IC depending on the value of the conventional differentiation circuit using a capacitor and resistor, and external components and accompanying input/output terminals are required. do. In addition, in conventional circuits, when the video signal level is temporarily low (weak electric field state), the synchronization signal may not be captured, and the signal is completely lost during that time. In circuits that process images, signal omission sometimes causes malfunctions, resulting in image disturbances.

Furthermore, since the pulse width of the obtained output signal depends on the time constant CH, there is a problem that the precision of the pulse width is not high due to element variations and temperature fluctuations.

The purpose of the present invention is to eliminate such drawbacks, make it easy to integrate into an IC, have high accuracy reliability, and obtain an IH-synchronized horizontal synchronization signal synchronized with an input composite synchronization signal as an output signal after separation. Another object of the present invention is to provide a composite synchronization signal separation circuit that can cope with signal dropout of the composite synchronization signal.

[Means to solve the problem]

The composition of the composite synchronization signal separation circuit of the present invention includes a trigger pulse generation circuit that inputs an input clock and a composite synchronization signal and outputs a trigger pulse synchronized with the rising edge of the composite synchronization signal, and a trigger pulse generation circuit that inputs the input clock and resets the signal. A counter that counts one synchronization portion of a horizontal synchronization signal according to a signal, a decoder that decodes the output of this counter, and a first RS latch circuit that outputs a first pulse every 1,000 cycles from a predetermined output of this decoder. a second RS latch circuit that receives the output of the decoder and the reset signal and outputs a second pulse equivalent to the composite synchronization signal; and a second RS latch circuit that receives the output of the decoder and the trigger pulse. The present invention is characterized by comprising a pulse output circuit that outputs the reset signal, and a latch circuit that receives the first pulse and the composite synchronization signal or the second pulse and outputs the horizontal synchronization signal.

In the present invention, the pulse output circuit includes a third RS latch circuit that outputs the third pulse from a predetermined output of the decoder, and an AND circuit that takes the logical product of the output pulse of the third latch circuit and the trigger pulse. , and an OR circuit that takes the logical sum of the output of this AND circuit and a predetermined output of the decoder and outputs a reset signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a system block diagram of one embodiment of the present invention. This embodiment includes a trigger pulse generation circuit 3 that generates a trigger pulse synchronized with the rising edge of a composite sync signal inputted from a composite sync signal input terminal 1, and a horizontal sync signal inputted with a system clock from a clock input terminal 2. a counter 4 that counts one cycle period (IH), a decoder 5 that selects an arbitrary count value from the count value counted by this counter 4, and an RS latch 6 that creates pulses having various arbitrary cycles. 7.8, an AND circuit 9 and an OR circuit 10 that generate a reset signal for the counter 4 and a trigger pulse when the composite synchronization signal is removed, a latch circuit 12 that outputs a horizontal synchronization signal, and a composite circuit that inputs a clock to latch. It is composed of an OR circuit 11 that latches either a synchronizing signal or a clock generated internally, and outputs a horizontal synchronizing signal from an output terminal 13.

FIG. 2 is a timing diagram explaining the operation of FIG. 1,
Input composite synchronization signal A, system clock B, counter 4
The reset pulse C of the counter 4, the count output of the counter 4, the data input signal E of the latch circuit 12, the setting pulse F of the output valid period of the latch circuit 12, and the input composite synchronization signal that latches the latch circuit 12 when a signal dropout occurs. The clock pulse G and the horizontal synchronization output signal ■ are shown.

A composite synchronization signal A is input from the input terminal 1, and its rising edge trigger pulse C is generated by the trigger pulse generation circuit 3, and this edge trigger pulse C is used as the output valid period setting pulse F.
The counter 4 is reset only during the "H" period. That is, the counter 4 once resets the count value by this trigger pulse C, and starts counting again by the system clock B input from the input terminal 2.

A pulse indicated by the data input signal E of the latch circuit 12 is generated by the decoder 5 and the RS latch 6. The rising edge of this pulse corresponds to the period of the horizontal synchronizing signal (IH = 63.5566μ5e
By rising in a few μsec shorter time than c),
An "H" level is output from the latch circuit 12 in synchronization with the rise of the next composite synchronization signal. Note that the pulse width of the output horizontal synchronizing signal depends on the fall of the output of the RS latch 6.

In addition, since the period of the horizontal synchronization signal is IH, the RS The latch 8 generates a setting pulse F for the output valid period, and outputs only the period when this pulse is "H".

Furthermore, if the input composite sync signal is temporarily lost,
A clock pulse G is generated that rises several hundred μsec to several μsec later than IH, and when the input signal is lost, it is output at the timing of this clock pulse. A horizontal synchronizing signal output is always outputted from these outputs.

〔Effect of the invention〕

As explained above, the present invention uses a counter that counts one cycle of a horizontal synchronization signal, and combines a decoder that decodes the count value of the counter and an RS latch,
By generating three types of pulses, it is possible to synchronize with the composite synchronization signal, and even if this composite synchronization signal temporarily loses the signal, it is possible to output the self-generated horizontal synchronization signal. Since it does not use a capacitor or a resistor, it is easy to integrate into an IC, and it has the advantage of being able to obtain an output signal with very high accuracy and reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of FIG. The figure is a circuit diagram of an example of the prior art, and FIG. 5 is a timing diagram showing the operation of FIG. 4. DESCRIPTION OF SYMBOLS 1... Composite input terminal, 2... System clock input terminal, 3... Trigger pulse generation circuit that generates a trigger pulse synchronized with the rising edge of the composite synchronization signal, 4...
・Counter, 5...Decoder, 6...RS latch 1
．． 7...RS latch 3.8...RS latch 2.9.
...AND circuit, 10.11...OR circuit, 12...
・Latch circuit, 13...Horizontal synchronization signal output terminal, 21
... Horizontal synchronization signal, 22 ... Equalization pulse signal, 23
... Vertical synchronization signal, T1 ... Vertical blanking period, C
1... Capacitor, R1... Resistor, A... Input composite synchronization signal, B... System clock signal, C...
Counter reset pulse, D...Counter counting operation, E...Data input signal, F...Output valid period setting pulse, G...Clock pulse when the input composite synchronization signal has a signal dropout. ,■...Horizontal synchronization output signal.

Claims (1)

[Claims] 1. A trigger pulse generation circuit which inputs an input clock and a composite synchronization signal and outputs a trigger pulse synchronized with the rising edge of the composite synchronization signal; and a trigger pulse generation circuit which inputs the input clock and generates horizontal synchronization by a reset signal. A counter that counts one synchronized portion of a signal, a decoder that decodes the output of this counter, and a first RS latch circuit that outputs a first pulse every horizontal period from a predetermined output of this decoder.
a second RS latch circuit which inputs the output of the decoder and the reset signal and outputs a second pulse equivalent to the composite synchronization signal; and a second RS latch circuit which inputs the predetermined output of the decoder and the trigger pulse and outputs the reset signal. A composite synchronization signal comprising: a pulse output circuit that outputs a signal; and a latch circuit that receives the first pulse and the composite synchronization signal or the second pulse and outputs the horizontal synchronization signal. Separation circuit. 2. The pulse output circuit includes a third RS latch circuit that outputs a third pulse from a predetermined output of the decoder, an AND circuit that takes the logical product of the output pulse of the third latch circuit and the trigger pulse, and 2. The composite synchronization signal separation circuit according to claim 1, further comprising an OR circuit for calculating the logical sum of the output of the AND circuit and a predetermined output of the decoder and outputting a reset signal.