JPH04109782A - Recording device and reproducing device - Google Patents

Abstract

PURPOSE:To reduce the effect of an error without increasing additional information such as error correction by including a specific SYNC pattern to a code word or a final part of linked code words and detecting the SYNC pattern when code synchronization is unlocked at reproduction. CONSTITUTION:A signal inputted from an input section 4 in a coder is inputted to a pattern selector 7. The pattern selector 7 selects an information pattern inputted from an information pattern input section 5 and an end pattern inputted from an end pattern input section 6 according to an input signal and links them and outputs the result to an output section 8. A variable length decoding section 15 in a reproduction device stops decoding when an error information input section 13 detects an error and inputted to the section 15 and restarts a variable length decoding according to a head position of a code word inputted from a SYNC pattern detection section 14. Thus, even when an error takes place at the reproduction, the code synchronization of the variable length code is simply restored.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image signal processing device for processing image signals.

[Prior Art] Conventionally, as an image signal processing device, there is an image signal recording and reproducing device that records an image signal on a recording medium and reproduces the recorded image signal from the recording medium.

The above-mentioned image signal recording and reproducing apparatus includes, for example, a videotape recorder and an electronic still video system, which are configured to record and reproduce image signals using a magnetic tape or a magnetic disk.

In the above-mentioned image signal recording and reproducing apparatus, there is a problem of image quality deterioration caused by time axis fluctuations occurring in the reproduced image signal on the reproduction surface, and in order to remove the time axis fluctuations, a TBC (TimeBase Corrector)
) circuit is used.

The TBC circuit uses PLL (PhaseLoc), a clock signal synchronized with time axis fluctuations occurring in the reproduced image signal.
ked loop) circuit, gated oscillator, etc., and outputs the reproduced image signal in synchronization with the clock signal.
/D conversion to digitize, store the digitized reproduced image signal in memory, read it out from the memory in synchronization with the lock signal, and convert it to analog again to remove time axis fluctuations. This is what I am trying to do.

[The problem that the invention is trying to solve] However,
The TBC circuit described above has a complicated structure, resulting in a very high cost, and also has the following problems.

In other words, the conventional TBC circuit uses the horizontal synchronization signal in the reproduced image signal as a reference signal when forming the clock signal, and the clock is generated by a clocked oscillator or PLL circuit controlled by the horizontal synchronization signal in the reproduced image signal. When forming a signal, a! occurs within the horizontal synchronization period. It is not possible to remove the j-axis fluctuations, and the time-axis fluctuations remain during the period immediately before each horizontal synchronization signal, resulting in image quality deterioration near the right end of the reproduced image.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an image signal processing device that can reduce the time axis fluctuation component occurring in an image signal with a simple and low-cost configuration.

[Means for Solving the Problems] The image signal processing device of the present invention is a device for processing image signals, each having a different delay time d, and extending each input image signal by 'N' and outputting it. a plurality of delay circuits; and a selection means for selecting at least one type of image signal from among the image signals delayed by the plurality of delay circuits in accordance with the amount of time axis variation occurring in the input image signal; and output image signal forming means for forming and outputting an output image signal using the image signal selected by the selection means.

[Operation] According to the above-described configuration, it becomes possible to reduce the time axis fluctuation component occurring in the image signal with a simple and low-cost configuration.

[Example code] Hereinafter, the present invention will be explained using examples of the present invention.

FIG. 1 is a diagram showing a schematic configuration of an image signal reproducing apparatus as a first embodiment of the present invention.

In FIG. 1, a reproduction signal reproduced by a magnetic head 3 from a track of a magnetic disk 2f which is rotated by a motor l at a predetermined rotation speed is supplied to a reproduction signal processing circuit 4, and in the circuit 4, a reproduction signal is Emphasis processing,
After performing various types of reproduction signal processing such as demodulation, the signal is supplied to a flank circuit 5 and a periodic signal separation circuit 6.

The flanking circuit 5 removes the horizontal and vertical synchronizing signals in the reproduced image 48 outputted from the reproduced signal processing circuit 4, and then supplies it to the IH (H is one horizontal interval period) delay MA7.

Further, the synchronization signal separation circuit 6 separates horizontal and vertical synchronization signals from the reproduced image signal outputted from the reproduction signal processing circuit 4, and supplies them to the synchronization signal generator 8 and counter 9.

A synchronization signal generator 8 generates one gate signal for controlling the franking process in the franking circuit 5 based on the horizontal and vertical synchronization signals supplied from the synchronization signal separation circuit 6 in the previous stage, and a clock signal for operating the counter 9. , various synchronization signals for controlling the system controller 10, water flow and vertical synchronization signals to be added in the subsequent synchronization signal addition circuit 13, and supplying 0+ to each circuit.

1) In the f delay line 7, the reproduced image signal delayed by the IH period is supplied to the delay line 11 and the a terminal of the changeover switch 2.

There's a delay! ! 11 has a plurality of intermediate taps, the interval T between each tap is set so that fO='/2T or outside the frequency band of the reproduced image signal, and the number of taps n is n.
-T is set to be larger than the maximum time axis variation that occurs within one screen. In this embodiment, the number of intermediate taps of the delay line 11 is five, and the reproduced image signal output from each intermediate tap and the delay line 11 is supplied to terminals 5 to g of the changeover switch 2, and a-
By selecting one of the g terminals, I
The reproduced image signal delayed by the H delay &l'7 or the delay line 11 is supplied to the synchronizing signal adding circuit 13.

The switching operation of the changeover switch 12 is controlled by the system controller 10 as follows.

That is, the counter 9 measures the length of one horizontal opening period including the jitter component from the synchronization unevenness supplied from the synchronization signal separation circuit 6 based on the clock signal supplied from the synchronization signal generator 8, and uses the λ1 measurement. The horizontal cycle period t
When H' is assumed, tH'=tH+Δt (where tH is the length of one horizontal opening period that does not include the jitter component, Δt represents the jitter component).

Then, the system controller 10, which is supplied with the data representing tH' output from the counter 9, m-T(
m is the number of intermediate tap stages selected by the system controller 10; in this embodiment, m is an integer from o to 6) or Δt/
The connection of the terminals a to g in the changeover switch 12 is controlled every horizontal opening period so that the connection of the terminals a to g in the changeover switch 12 is the closest to 2.

Through the above operations, the jitter component of the reproduced image signal supplied to the synchronization signal addition circuit 13 is reduced by approximately half for each horizontal synchronization period, and the horizontal and manual synchronization signals are further added in the synchronization signal addition circuit 13. Thereafter, 'i' is output from the output terminal 14. FIG. 2 shows a schematic configuration of an image signal reproducing apparatus as a second embodiment of the present invention.

Incidentally, in FIG. 2, the same components as those in FIG. 1 are given reference numbers and detailed explanations will be omitted.

In FIG. 2, the reproduced image signal output from the reproduced signal processing circuit 4 is supplied to the A/D converter 15 after horizontal and vertical synchronizing signals are removed by the flank circuit 5.

After the A/D converter 15 digitizes the reproduced image signal in synchronization with the clock signal output from the synchronization signal generator 16, the A/D converter 15 digitizes the reproduced image signal in synchronization with the clock signal output from the synchronization signal generator 16. After being delayed by the IH period by the shift register 17 that shifts the signal, the signal is supplied to the shift register column 18.

The number of stages of the shift register 17 is 1 horizontal opening period uH.
tBLK is the franking period during H1111 horizontal opening.
, the A/D converter 15 is set to ((LH-tBLK)/ts or more, where ts is the summation blink interval).

The shift register array 17 is composed of four one-sample shift registers 17a to 17d, each of which delays data by one sample link period in synchronization with the clock signal output from the periodic signal generator 16. 17. The digital reproduction image signal output from the shift register array 18 is transferred to the selector switches 19 a and b.

C terminal, d and C terminals of the selector switch 20, and the selector switch 19 supplies the terminals a and b.

By selecting one of the C terminals and selecting either the d or C terminal with the changeover switch 20, the changeover switch 19 outputs a digital reproduced image signal delayed by the shift register 17 or the shift register array 18. The digital reproduction image signal delayed by the shift register array 18 is supplied from the changeover switch 20 to the adder 21 and the h terminal of the changeover switch 23.

The g terminal of the selector switch 23 is connected to the selector switch 19.
The average value of the digital reproduced image signal output from 20 is formed and supplied by an adder 21 and a station coefficient multiplier 22, and by selecting one of the f, g, and h terminals with the changeover switch 23, The digital playback signal delayed by the shift register 17 and the shift register array 18 or the average value of the delayed digital playback signal
The signal is supplied to the D converter 24.

The switching operations of the changeover switches 19, 20, and 23 are controlled by the system controller 25 as follows.

That is, as in the first embodiment shown in FIG. 1, the counter 9 measures the length of one horizontal period including the jitter component. Note that the data output from the counter 9 at this time is data with the sampling link interval ts being medium.

Then, the system controller 25 compares the data t11' representing one water synchronization period including a jitter component supplied from the counter 9 with data tH of one water synchronization period not including a jitter component known in advance. By doing so, data △t representing the jitter component is calculated, and the selector switch 1'l is set according to the magnitude of the jitter component data △t.
, 20.23 are controlled to be connected as shown in FIG.

Then, the digital reproduction image signal with reduced jitter components output from the changeover switch 23 is sent to the D/A converter 2.
4, the signal is analogized in synchronization with the clock signal output from the synchronization signal generator 16, and then horizontal and vertical synchronization signals are added in the synchronization signal separation circuit 13, and then output from the output terminal 14.

The number of intermediate taps of the delay line II in the first embodiment shown in FIG. 1 and the number of 1-sample shift registers in the shift register array 18 in the second embodiment shown in FIG. 2 are shown in the actual travel example. It is not limited to a number.

In addition, although the first and second embodiments have been explained using a magnetic tape reproducing device in which image signals are recorded as an example, the present invention can also be applied to devices such as optical video disc players and video tape recorders. It is possible to obtain a similar effect by using

[Effects of the Invention] As explained above, the present invention provides an image signal processing device that can reduce the flJI axis fluctuation component when it occurs in an image signal with a simple and low-cost configuration. You will be able to do things.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration of an image signal reproducing apparatus as a first embodiment of the present invention. FIG. 2 is a diagram showing a schematic configuration of an image signal reproducing apparatus as a second embodiment of the present invention. FIG. 3 is a diagram for explaining the switching control operation of the changeover switches 19, 20, and 23 by the system controller 25 in the second embodiment shown in FIG. 6... Synchronous signal separation circuit 7... IH delay line 8.16... Synchronous signal generator 9... Counter 10.25... System controller 11... Delay line 12, ]9, 20 .23... Selector switch 15...
A/D converter 17...shift register 18...shift register column 21...adder 22...station coefficient multiplier 24...D/A converter

Claims (1)

[Scope of Claims] An apparatus for processing an image signal, comprising: a plurality of delay circuits each having a different delay time and respectively delaying and outputting an input image signal; and a device delayed by the plurality of delay circuits. selecting means for selecting at least one type of image signal from among the image signals according to the amount of time axis variation occurring in the input image signal; and an output image signal using the image signal selected by the selecting means. An image signal processing device comprising an output image signal forming means for forming and outputting an output image signal.