JPH04105484A - Motion vector detection circuit - Google Patents

Abstract

PURPOSE:To detect a motion vector efficiently at a high speed without deteriorating detection accuracy with less number of arithmetic circuit by inputting a picture data of a current block extracted at an optional position of a series delay circuit to plural arithmetic circuits. CONSTITUTION:Plural delay circuits 10-1-10-36 are connected in series with an input terminal 1a and a selection means 20 is connected to a prescribed position of the delay circuits 10-1-10-36. A picture element data Db of an inputted retrieval range block from an input terminal 1b is sequentially inputted from the upper left of a block in a longitudinal direction (main scanning direction). The data is simultaneously given to arithmetic circuits 30-1-30-13. The picture element data Da of an inputted current block from the input terminal 1a is sequentially inputted from the upper left of a block in the longitudinally direction. Thus, the picture element of both the current block and the retrieval range block is inputted continuously without tracing back each column to output a motion vector one after another.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention provides a motion compensation code for encoding (compressing) moving images in videophones, moving image storage devices, etc. that use motion detection prediction signals for moving images. The present invention relates to a motion vector detection circuit that is installed in a conversion device or the like and detects the movement of pixel data.

(Conventional technology) Conventionally, the technology in this field has been developed by Hatahiko Yasuda supervised “
"High-efficiency coding technology for image transmission" (Sho 62-3-:
31) (Torikebus Co., Ltd.), P. 231L-233.

Conventionally, in videophones, video storage devices, and the like, moving images are handled as digital data that is highly flexible in processing, but if that moving image data is directly expressed as digital data, the amount of data becomes enormous. Therefore, in order to improve communication efficiency and save on recording media, moving images are encoded and communicated or recorded.

In video encoding, motion compensation is effective in improving encoding efficiency, and techniques related to this are described in the above-mentioned documents. Motion compensation involves dividing the frame to be encoded (current frame) into small rectangular blocks, detecting (motion detection) the portion of the previous frame that has the highest degree of approximation for each block, and using this as the predicted signal. It is used as a.

FIGS. 2(a) to 2(C) are explanatory diagrams of this motion detection.

FIG. 2(a) is a diagram showing the correspondence between the current frame and the previous frame.

Ft is the current frame, Ft-1 is the previous frame, A(n, m
> is one divided block of the current frame Ft, B (n
, m) is the search target block corresponding to A (n, m) of the previous frame. A (n, m+1) is A (n, m)
The neighboring block, B(n.

m+1) is the search target block corresponding to A (n, m+1>. B (n, m>(0,0>, B5(n,
m-'-,1) (0,0> is block A (nm),
It is a block of the same size and position at the same location as A (rl, m+1).

FIG. 2(b) is a diagram showing the search range corresponding to block A(n, m), that is, the size of B(n, m>). FIG. 2(C) is a diagram showing the size of B(n, m>) for the search. It is a figure which shows the movement of block B (n, m>(p, q)) in n, m).

B (n, m>(p, Q> is A (n, m> and B
This is a block indicating which part in (n, m> is compared. Vectors p and q are B8(n.

m>(0,0> indicates that the block position has been moved by p pixels in the vertical direction and q pixels in the horizontal direction.B (n, m>(p, q> is B ( n, m
), so ≦k rl p r2. CI≦q≦c2. Here, the value of each pixel in block A (n, m) is x (
i ・n+i,jM-m+j) and the block size is expressed as iMXjM), and the compared block B (n, m>(p, q>) is LM (i - n+i+p, jt-I
M ya・m+j+q)te' is expressed.

In order to detect the part with the highest degree of approximation to A (n, m> within B (n, m>), change p and q and A (n,
m) and B (n, m>(p, q>), and the one with the smallest value is considered to be the one with the highest degree of approximation.

That is, for each p and q, Xt 1 (LM ・n+
i+p.

jM-m+j+9)l...Calculate (1) and find p and q that minimize the result.

Let these p and q be motion vectors, and B8(n, m)(p,
q> as a prediction signal, instead of encoding block A (n, m) of the current frame Ft, which is the frame to be encoded, the motion vector and the prediction signal B (n, m>(
Encoding efficiency can be improved by encoding the error between p, q> and block A (n, m> of the current frame Ft.

In reality, the data of the previous frame F and the current frame F are respectively stored in the frame memory, and between them,
Equation (1) is calculated while shifting p and q little by little.

(Problems to be Solved by the Invention) However, the circuit with the above configuration has the following problems.

In the calculation of equation (1) above, if the vectors p and q are close,
As shown in FIG. 2(c), B8(n.

Although a considerable portion of m> (p, q> is a common pixel, the calculation is performed using pixels that are shifted from each other in pixel units.

Furthermore, as shown in FIG. 2(a), the blocks B (n, m) and B (n, m+1) to be searched also include common pixels, but the blocks A (n, m) and A ( n,
m+1), the pixel data must be read out multiple times, and its control becomes complicated. For this reason, in motion compensation encoding devices and the like having such a motion detection processing function, calculations are generally performed using a processor such as a microprocessor that can be controlled by software.

However, in this case, there is a problem in that the amount of calculation to be handled is extremely large, and the processing takes time. That is, a block A (n, m> in the current frame Ft and a block B8 (n, m) (p,
q), the size of each block is iM
If XjM, the cumulative addition of the absolute difference values is performed I M X J M times. This is the number of possible motion vectors, that is, p and q, (r 1+
r 2 +1 > ×(c 1 + C2+ 1)
repeated times.

By performing these calculations, the motion vector for block A (n, m) is determined. Therefore, for one block A (n, m>) in the current frame Ft, 1 yI
X J MX (rl + r 2 + 1) X
The cumulative addition of absolute difference values is performed (C1, C2÷1) times. Since this is performed for each block of the current frame Ft, the amount of calculation becomes enormous.

Therefore, it is possible to limit the number of vectors. In other words, it is possible to reduce the amount of calculation by thinning out the vectors to the extent that there is no problem in use. However, processors such as microprocessors generally perform each calculation serially, so even with such thinning, the same pixel data must still be read multiple times or a considerable amount of calculation must be performed. However, it took a considerable amount of time to process and was not very practical.

The present invention solves the problem that the prior art had, but when a processor is used to simplify control, the processor performs each calculation serially, so the processing takes a considerable amount of time. The present invention provides a motion vector detection circuit that solves the problem of a high-speed processor and memory being required when handling moving images, resulting in a complicated circuit configuration, an increase in circuit scale, and an increase in cost.

(Means for Solving the Problems) In order to solve the above problems, the first invention divides one frame into a plurality of blocks, and calculates pixel data of each current block by comparing it with other frames. A motion vector detection circuit that detects motion includes a plurality of series-connected delay circuits and a plurality of arithmetic circuits. Here, the plurality of delay circuits are circuits that delay pixel data of the current block among the pixel data of the search range block and the pixel data of the current block in the frames to be compared. The plurality of arithmetic circuits input the pixel data of the current block extracted from predetermined positions of the plurality of delay circuits and the pixel data of the search range block, and calculate an evaluation function for each vector shifted around the current block. This is a circuit that calculates a value.

A second aspect of the invention is based on the first aspect, further comprising a selection means for selecting pixel data of a plurality of current blocks taken out from a plurality of positions of the plurality of delay circuits and inputting the selected pixel data to the arithmetic circuit.

(Operation) According to the first invention, since the motion vector detection circuit is configured as described above, when the pixel data of the search range block and the pixel data of the current block are input, the pixel data of the current block is It is appropriately delayed by a series delay circuit and input to a predetermined arithmetic circuit.Each arithmetic circuit calculates the evaluation function value corresponding to any required vector.This allows the evaluation of blocks that are continuous in the horizontal or vertical direction. In calculations, the same pixel data is not read multiple times, and it is possible to perform calculations at high speed without using high-speed processors or memory.
Motion vectors can be detected.

According to the second invention, the output of the serial delay circuit is selected by the selection means and input to the plurality of arithmetic circuits. As a result, motion vectors can be accurately detected by arranging vectors in accordance with the type of image to be handled (for example, an image that moves entirely, or an image that moves a lot in up, down, left, right, up, down, and left and right directions).

Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a configuration block diagram of a motion vector detection circuit showing a first embodiment of the present invention.

In this motion vector detection circuit, an example circuit is shown in which the current block of the current frame has a size of 4 x 4 pixels, and the search range block of the previous frame as a frame to be compared has a size of 8 x 8 pixels. ing.

This motion vector detection circuit has an input terminal 1a to which pixel data Da of the current block is input, an input terminal 1b to which pixel data Db of the search range block is input, and an output terminal 2. A plurality of delay circuits 1 are connected to the input terminal 1a.
0-1 to 10-36 are connected in series, and the delay circuit 1
Selection means 20 are connected to predetermined positions from 0-1 to 10-36. The output side of the selection means 20 and the input terminal 1b are connected to the input sides of a plurality of arithmetic circuits 30-1 to 30-13, and the output sides of the arithmetic circuits 30-1 to 30-13 are
It is connected to the output terminal 2 via a comparison circuit 40.

The delay circuits 10-1 to 10-36 have a function of delaying the pixel data Da of the current block, and are composed of, for example, registers that temporarily hold input data in synchronization with a clock signal.

The selection means 20 selects the outputs of the delay circuits 10-1 to 10-36 and provides them to the calculation diagrams 30-1 to 30-13, and is composed of a plurality of selectors 20-1 to 20-8. . The selector 20-1 selects one of the input terminal 1a and the output of the delay circuits 10-1, 10-16, and supplies it to the arithmetic circuit 30-1. The selector 20-3 selects any one of the outputs of the delay circuits 10-4.10-2.10-12 and applies it to the calculation circuit 30-2. It has the function to provide to Figure 130-3.

Selector 20-4 is delay diagram #110-16.10-1
The selector 20-5 selects one of the outputs of the delay circuits 10-19 and 10 and supplies it to the arithmetic circuit 30-6.
- Select one of the outputs of 20 and the arithmetic circuit 30 -
8 and selector 20-6 selects delay diagram 810-24.8.
It has a function of selecting one of the outputs of 10-32 and 10-34 and providing it to the arithmetic circuit 30-11. Further, the selector 20-7 selects the delay circuit 10-26.10-
The arithmetic circuit 30-1 selects one of the outputs of the 34 outputs.
2, and the selector 20-8 is applied to the delay circuit 10-2.1.
It has a function of selecting any one of the outputs of 0-35, 10-36 and providing it to the arithmetic circuit 30-13.

However, delay circuit 10-9.10-11.10-25.1
The outputs of 0-27 are directly input to arithmetic circuits 30-4, 30-5, 30-9 and 30-10, respectively, after passing through the selector.

Arithmetic circuits 30-1 to 30-13 are circuits that calculate evaluation function values corresponding to each set vector. Assuming that the evaluation function is the cumulative value of the absolute difference between the pixel data Da of the current block and the pixel data Db of the search range block, each arithmetic circuit 30-1 to 30-13 has an input terminal and a
pixel data Db of the search range block input from;
A difference absolute value circuit and a cumulative addition circuit that perform cumulative addition of the absolute difference value between the outputs of the delay circuits 10-1 to 10-36 and pixel data of the current block extracted from a position delayed by a desired number of stages. It consists of

The comparison circuit 40 is a circuit that successively compares the evaluation function values calculated by each of the calculation circuits 30-1 to 30-13, determines a motion vector for the current block, and outputs the determination result to the output terminal 2. .

In FIG. 1, the connections between each circuit are buses corresponding to the number of signal bits. For example, input terminals 1a, lb
When the input pixel data Da and Db from 8 bits are each given, the input/output lines of each delay circuit 10-1 to 10 to 36 and the input line to each operation diagram B50-1 to 30-13 are It becomes 8 bits. Furthermore, when the size of the current block is 4.times.4, the cumulative addition of absolute difference values is performed 16 times, so the output lines from each of the arithmetic circuits 30-1 to 30-13 are 12 bits.

The operation of the motion vector detection circuit configured as described above is explained in FIGS. 3(a), (b), 4, and 5(a) to (
This will be explained with reference to d).

3(a) and (b) are diagrams showing the current block and the search range block, and FIG. 3(a) shows the current block.A
(n, m), A (n, m+1>... is a block of 4 × 4 pixels. Let the upper left pixel of block A (n, m>) be x t (4n, 4 m), and in that block Let the pixel of block A(n, m+1) be xt(4n+1.4m+j). Also, let the upper left pixel of block A(n, m+1) be xt(4n, 4m+j).
m+1), and the pixels in that block are Xt(4n+i
, 4m+j).

FIG. 3(b) is a diagram showing search range blocks. When detecting motion vectors in the range of +2 in the upper, lower, right, and left directions for the current block A (n, m>, B (n, m>,
The size of the search range block for B (n, m+1>, - is 8×8 pixels.xt(
Let the pixel of B (n, m) that corresponds in position to Xtl (40, 4m) be Xtl (40, 4m), and let the pixel in that block be Xtl (4n + i + p, 4m ± j + q). Here, the search range blocks each have a portion that overlaps with each other, for example, B (n, m> of X (4n-2,
4m+2) and B (n, m+1>Xt-1(4n
2.4 (m+1>2) indicates the same pixel.

FIG. 4 is a diagram showing the data input timing, where Da is the pixel data in the current block input from the input terminal 1a, and D
b is pixel data within the search range block input from the input terminal 1b. If the selector 20-1 selects the input from the input terminal 1-a, the pixel data DaDb shown in FIG. 4 becomes the input to the calculation circuit #130-1. Sl is a timing signal that indicates whether to perform or stop calculation on the pixel data of the current block, depending on the timing at which the data is input to the calculation circuit. Da2 is
It is the output of the delay circuit 10-2, and the selector 20-2 is
When this output is selected, this is the arithmetic circuit 30-2.
is input. S2 is a timing signal indicating whether to perform or stop calculation on the input pixel data at that time.

The pixel data Db of the search range block inputted from the input terminal 1b is sequentially inputted in the vertical direction (main scanning direction) from the upper left of the block in FIG. 3(b).

The lower left of the block, i.e. xt-1(4n + 2).

After the pixel data Db of 4m-2) is input, the pixel data Db of the next column x (4n-2, 4m-2>) is input continuously.In other words, the pixel data Db as shown in FIG. This data is simultaneously input to the arithmetic circuits 30-1 to 30-3.
Given to 0-13.

Pixel data D of the current block input from input terminal 1a
a is input sequentially in the vertical direction from the upper left of the block in FIG. 3(a). The bottom left of the block, i.e. x t(4n +
After the pixel data Da of 3,4 m) is input,
-When the input is stopped and the scanning of the search range block moves to the next column, the pixel data Da of the next column of the current block
Start typing.

The inputs to the input terminals 1a and lb are block A (
The first pixel of the column n, m> and the first pixel of the column of block B (nm>) are respectively input synchronously.

When the selector 20-1 selects the input from the input terminal 1a for the pixel data Da and Db input in this way, the arithmetic circuit 30-1. to x (4n, 4m
>, xt(4n+1.4m>.

...and x (4n 2.4m 2),
Xt 1(4n-1,4m-2>,...
pixel data is input and the calculation is completed,
Based on equation (1), the vector p-2, q=-2, that is, 1=Oj=0-XI-1(4n+i-2, 4m+j-2>) has been calculated.With this calculation result, Some vector p--
2, the cumulative value of the absolute difference values for q=-2 is transferred to the comparator circuit 40.

In the arithmetic circuit 30-2, the selector 20-2 is connected to the delay circuit 1.
If output 0-2 is selected, Xt(4n, 4m>
, Xt(4n+1.4m>,..., t-1(4n, 4
m-2), x <4n-i-14m-2),...
・is input synchronously. And the calculation times &! 30-
2, a sequential operation is performed and xt(4n
+3, 4m+3) pixel data is input, and when the calculation is completed, the vector I
)=0. q=-2, that is, 0J=0-Xt-1(4n+i+0.4m+j-2>) has been calculated.This calculated value is temporally delayed from the pixel data of the current block. Output is delayed.

In this way, each vector p=~2q--2, p-
Operations on 〇, q−−2, . . . can be performed.

FIGS. 5(a) to 5(d) are diagrams showing vector positions.

For example, selector 20-1 selects input from input terminal 1a, and selector 20-2.20-3.20-4
, 2C) -5, 20-6, 20-7° 20-8 is the delay circuit 10-2.10-4.10-16.10-20.10
-32 ]]○ When each output of -34 and 10-3 is selected, each arithmetic circuit 30-1 to 30
-13 are respectively vector values 7jlp-2, q=-2
, p-0゜q=-2, P=+2. CI=-2, p=-1
, 9=1, . . . The vector position to be calculated is shown in Fig. 5 (a). The O mark in the figure indicates the vector position where the calculation is performed. As shown in ＞, vector positions to be calculated are arranged in a staggered manner. Note that ■1 to ■□3 in FIGS. Compatible.

Similarly, selectors 20-1 to 20-8 select delay diagram B.
10-16.10-10.10-2.10-17.10
When each output of -19.10-34.10-26.10-20 is selected, the vector position calculation shown in FIG. 5(b) is performed.

Selectors 20-1 to 20-8 are delay circuits 10-1.1
0-10.10-2.10-17.10-19.10-
When each output of 34.10-26.10-35 is selected, the vector position calculation shown in FIG. 5(c) is performed.

Selectors 20-1 to 20-8 are connected to delay circuits 10-16.
10-10.10-12.10-17゜10-24.1
When each output of 0-26, 10-20 is selected, the vector position calculation shown in FIG. 5(d) is performed.

The output of each arithmetic circuit 30-1 to 30-13 is transferred to the comparator circuit 40 as soon as the arithmetic operation for that vector is completed. The comparison circuit 40 compares the evaluation values that are successively transferred, and calculates the number of vectors that have been operated on for the block, for example, after 13 vectors have been transferred, the number of vectors that have been sent is the last remaining value. Depending on the motion vector value of the block, a value corresponding to the motion vector value for that block is output from the output terminal 2.

Each arithmetic circuit 30-1 to 30-13 has a current block A (
When the input and calculation of pixel data Da of block A (n, m) is completed, the pixel data Da of the next block A (n, m+1>) can be input and the calculation for that block begins.Search range block B (n, m) and While the overlapping portions of B(n, m+1>) are being input, there are arithmetic circuits that are calculating vectors for block A (n, m) and for A(n, m+1). However, , input pixel data Db of the block in the search range is block B(n, m
), the next pixel at the bottom right of block B (n.

The upper left column of m=-1-) is not input, but the next column is input continuously.

In this way, by inputting both the current block and the search range block continuously in the block scanning direction (sub-scanning direction) without reversing each column, the current block A (n, m) A ( n, m+1),...
The motion vectors for ・ are output one after another. here,
The arrangement of vectors shown in FIGS. 5(a) to 5(d) is shown in FIG.
Regarding a), it is suitable for obtaining an approximate motion vector.

Further, it is suitable for determining the motion vector by focusing on the top, bottom, left and right in FIG. 12B, the left and right in FIG. In the configuration shown in FIG. 1, each vector arrangement can be set by switching each selector 20-1 to 20-8. Therefore, this first embodiment has the following advantages.

Motion vectors can be detected by arranging vectors according to the type of image being handled, that is, one that moves entirely, or one that moves a lot in up/down, left/right, up/down, or left/right directions. Therefore, motion vectors can be detected efficiently and at high speed with a small number of arithmetic circuits 30-1 to 30-13 without significantly reducing detection accuracy.

FIG. 6 is a configuration block diagram of a motion vector detection circuit showing a second embodiment of the present invention, and elements common to those in FIG. 1 are given the same reference numerals.

In the first embodiment, the selection means 20 selects the outputs at a plurality of positions of the serial delay circuits 10-1 to 10-36 as the pixel data of the current block, and the calculation diagram H@20-1 to 30- is selected.
13. However, when the types of images to be handled are limited, as shown in FIG. 6, the selection means 20 is omitted and the desired positions of the delay circuits 810-1 to 10-36, for example, as shown in FIG. 5(a), are selected. With the vector arrangement shown,
It may be configured to be fixedly connected to the arithmetic circuits 30-1 to 30-13. Even with this configuration, by limiting the types of images to be handled, not only can substantially the same effects as in the first embodiment be obtained, but also the circuit configuration can be simplified.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, the current block is 4×4, the search range block is 8×8, and the number of vectors to be calculated is 13, but the numbers may be changed to other numbers. Furthermore, Figures 1 and 6
Each block in the figure may be configured as an individual circuit or may be executed under program control by a processor.

(Effects of the Invention) As explained in detail above, according to the first invention, the pixel data of the current block taken out from any position of the series delay circuit is input to a plurality of arithmetic circuits. Therefore, a motion vector can be detected efficiently and at high speed with a small number of arithmetic circuits and without much deterioration in detection accuracy.

In this way, the circuit configuration can be simplified and the circuit scale can be reduced, so that costs can be reduced, and therefore, the present invention can be applied to various devices such as video telephone devices.

According to the second invention, since the selection means is provided and the output of the series delay circuit is switched and inputted to a plurality of arithmetic circuits, it is possible not only to obtain almost the same effect as the first invention, but also to handle Motion vectors can be accurately detected by arranging vectors according to the type of image (for example, an image that moves entirely, or an image that moves a lot in up/down, left/right, up/down, or left/right).

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of a motion vector detection circuit showing a first embodiment of the present invention, FIGS. 2(a) to (c) are explanatory diagrams of conventional motion detection, and FIG. 3(a). (b) is a diagram showing the current block and search range block in Figure 1; Figure 4 is a data input timing diagram in Figure 1;
Figures (a) to (d) are diagrams showing vector positions in Figure 1, and Figure 6 is a block diagram of a motion vector detection circuit showing a second embodiment of the present invention. 10-1 to 10-36...Delay circuit. 20... Selection means, 20-1 to 20-8... Selector, 30-1 to
30-13... Arithmetic circuit, 40... Comparison circuit. (Explanatory diagram of a no movement setup Ryo 2 (a) Sub-scanning direction current b is too large and the surrounding block D11.ri%3) (a no P (C) Vector is squid! Almost 5 Figure (b)

Claims (1)

[Claims] 1. In a motion vector detection circuit that divides one frame into a plurality of blocks and detects the movement of pixel data by comparing each current block with other frames, the frames to be compared. a plurality of series-connected delay circuits that delay the pixel data of the current block among the pixel data of the search range block and the pixel data of the current block within the search range; and a current block extracted from a predetermined position of the plurality of delay circuits. and a plurality of arithmetic circuits that input pixel data of the search range block and pixel data of the search range block and calculate an evaluation function value for each vector shifted around the current block. detection circuit. 2. The motion vector detection circuit according to claim 1, further comprising: selection means for selecting pixel data of a plurality of current blocks extracted from a plurality of positions of the plurality of delay circuits and inputting the selected pixel data to the arithmetic circuit. A motion vector detection circuit featuring: