JPH0395620A - Superhigh-speed disk device - Google Patents

Abstract

PURPOSE:To reduce the power consumption and simultaneously to attain a high speed access by performing the writing/reading tasks with the parallel bits for accesses of plural disk devices and supplying the power to only a disk mechanism part which is selectively connected. CONSTITUTION:When a write access is carried out by a controller 100 in the initial states of disk devices (10-1) - (10-4), a multiplexer 18 functions to connect the read/write circuits (12-1) - (12-4) to four heads (16-1) - (16-4) of a disk mechanism 14-1 respectively. The controller 100 transfers the bits in parallel to the interfaces (28-1) - (28-4) at every four bits b1 - b4 and writes the bits b1 - b4 into the disks (34-1) - (34-4) respectively. At the time of read access, one of mechanisms (14-1) - (14-4) is selected at a switch control part 20 based on the read access. Then the data are read in parallel with each other at every four bits. The power is supplied to the selected disk mechanism part only.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to an ultra-high-speed disk device in which a plurality of disk devices are connected in parallel to a host device, and access is performed by bit parallel transfer between the host device and the device, which simplifies the device configuration and reduces consumption. For the purpose of reducing power consumption, multiple disk devices each having a disk mechanism section with a write/read circuit and multiple heads are connected in parallel to a host device.
A switching circuit is provided between the write/read circuit of each disk device and the disk mechanism section, and parallel bit data write or read access is achieved by selectively connecting the write/read circuit of all disk devices to the head group of a specific disk device. Configure it to do this. By connecting multiple groups of this basic configuration to a host device as one group, the number of bits to be transferred in parallel can be further expanded. Only the disk mechanism to be accessed is driven, and just before the currently accessed disk becomes full, the next disk mechanism or the disk mechanism belonging to the group is activated.

[Industrial Application Field] The present invention relates to an ultra-high-speed detecting device that connects a plurality of disk devices in parallel to a host device and performs access by parallel bit transfer between the disk devices and the host device.

In recent years, as computer systems have become faster, disk devices have been required to have faster access, larger capacity, and lower prices.

In order to satisfy these demands for disk devices, the recording density of the disk is increased and the disk rotation speed is increased to increase the access speed, but it is difficult to dramatically improve performance.

Therefore, we decided to connect multiple existing disk devices to the host device.
By connecting in parallel, allocating one bit to each disk device, and performing parallel bit transfer with the host device, for example, if n disk devices are connected in parallel, write access or read can be performed in units of n bits. This makes it possible to access the data, realizing an n-fold increase in speed and n-fold increase in capacity.

However, operating multiple existing disk devices connected in parallel to a host device consumes a lot of power, and if a disk device dedicated to parallel bit transfer is prepared without using the existing disk device, This increases costs, and an ultra-high-speed disk device that makes effective use of existing disk devices is desired.

[Prior Art] FIG. 9 is a block diagram showing a conventional ultra-high speed disk device.

In FIG. 9, 100 is a controller as a host device, to which one or more hosts are connected. For the controller 100, n disk devices 10-1 to 1
0-n are connected in parallel. Between the host device 100 and each disk device 10-1 to 10-1n, n of bits b1 to bn
Parallel transfer is performed bit by bit.

Existing disk devices 10-1 to 10-n are used, including interface circuits 28-1 to 28-n and read/write circuits 12-1 to 28-n for the controller 100.
12-n, disk mechanism parts 14-1 to 14-n,
Each of the disk mechanism units 14-1 to 14-n is provided with, for example, four heads 16-l to 16-4.
6-1 to 16-4 are positioned and controlled by a voice coil motor 30, and disks 34-1 to 34-4 are controlled by a spindle motor 32 at a constant speed, for example, 3600 rpm.
It is rotated by m. One of the heads 16-1 to 16-4 is selected by the changeover switches 36-1 to 36-n based on the head address.

In such an ultra-high-speed disk device, taking write access as an example, each selector switch 3 is set in the initial state.
6-■ to 36-n select the head 16-1, and the n-bit parallel data transferred from the host device 100 is sent to all read/write circuits 12-1 to 12-n.
data is written in parallel to the same address location on different disks at the same time. Although access is performed by parallel bit transfer for the device as a whole, when viewed as a single disk device, the serially transferred data from the host device is sequentially written bit by bit, and the function as a disk device does not change in any way. isn't it.

[Problems to be Solved by the Invention] However, in a conventional ultra-high-speed disk device in which multiple disk devices are connected in parallel to a host device, all the disk devices are kept in operation, so the overall performance of the device is The power consumption is n times higher than that of a single disk drive, and a power supply with a large capacity must be used, resulting in an increase in running costs.

In order to solve this power consumption problem, as shown in FIG. (integer) disk devices 200-1 to 200-n
newly prepared, and this disk device 200-1 to 200
-n may be connected in parallel to the host device 100 for parallel bit transfer.

However, if a dedicated read/write circuit is provided for each head, the circuit configuration of a single disk device will become significantly more complex, resulting in a significant increase in cost compared to when using an existing disk device. was there.

The present invention has been made in view of these conventional problems, and it is an object of the present invention to provide an ultra-high-speed disk device that can simplify the device structure and reduce power consumption.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 1(a) shows the basic configuration of the present invention, and FIG. 1(b) shows a configuration in which the number of parallel transfer bits is expanded.

First, in the basic configuration shown in FIG. 1(a), when the number of bits transferred in parallel with the host device is n, the n disk devices 10-1 to 10-n that match the number of bits n are Connect in parallel to the host device. Disk devices 10-1 to 10
-n each of the heads 16 for at least n number of bits.
-1 to 16-n disk mechanism unit l4-1 to 14;
-n, and write/read circuits 2-1 to 14-n provided one for each disk device 10-1 to 10-n. Furthermore, a switching means selectively connects the write/read circuits 12-1 to 12-n and the heads 16-1 to 16-n belonging to any one of the disk mechanism units 14-1 to 14-n. 18, and write/read circuits 12-1 to 1 during write access.
2-n is connected to the heads 16-1 to 16-n belonging to a specific disk mechanism section 14-i according to a predetermined switching order, and data is written until the disk is full.
At the time of read access, heads 16-1 to 16-n belonging to a specific disk mechanism section 14-i corresponding to the access are
A switching control means 24- is provided which connects the write/read circuits 12-1 to 12-n to perform parallel reading.

Here, among the plurality of disk mechanism parts 14-1 to 14-n,
The writing/reading circuits 12-1 to 12- are controlled by the switching control means 18.
power is supplied only to the disk mechanism unit connected to n, and immediately before the disk of the disk mechanism unit becomes full, power is supplied to the disk mechanism unit that will be switched next to start at least the spindle motor. Control means 22 are provided.

Next, in the expanded configuration of Fig. 1(b), Fig. 1(a)
The n disk devices 10-1 to 10-n shown in Figure 1 are connected as one group, and the n groups are connected in parallel to the host device, and the total is transferred between each group and the host device in units of n bits. The configuration is extended to transfer nXn bits in parallel at the same time. The disk devices 10-1 to 10-n forming each group have the same basic structure as shown in FIG. 1(a).

Furthermore, a plurality of write/read circuits 12 belonging to a specific group
- a switching means 24 for selectively connecting the heads 16-1 to 16-n of the disk mechanisms 14-1 to 14-n belonging to the same group or another group; At the time of access, the write/read circuits 12-1 to 12-1 of the same group are written to one disk mechanism section 14-1 belonging to a specific group selected according to a predetermined switching order.
12-n, and the heads 1 of the remaining disk mechanisms 14-2 to 14-n belonging to the selected group.
6-1 to 16-n are write/read circuits 12 of other groups.
-1 to 12-n are connected in groups and data is written until the disk is full. At the time of read access, multiple groups of disk mechanisms 14-1 to 14-n belonging to a specific group corresponding to the access are connected. Head 16-1
.about.16-n are connected to the write/read circuits of all groups to read them out in parallel.

In this expanded configuration, a spindle synchronization circuit for synchronizing the rotations of the spindle motors is provided for each of the plurality of disk mechanisms that make up the group, and synchronizing the rotations (spindle sync) of each spindle motor belonging to the group.

Furthermore, in the expanded configuration, power is supplied only to the disk mechanisms 14-1 to 14-n belonging to the group selectively connected by the switching control means 24 among the multiple groups of disk mechanisms, so that the disks in the group are Disk mechanism unit 14 of the next group to be switched and connected immediately before it becomes full
A starting control means 26 is provided for supplying power to the spindle motors 1 to 14-n to start at least each spindle motor.

[Operation] According to the ultra-high-speed disk device of the present invention having such a configuration, in the selected state of the head group of a specific disk device corresponding to the number of parallel transfer bits with the host device,
The write/read circuits are individually provided in each disk device and can be used to access a group of heads, and by simply adding a switching means to an existing disk device, it is possible to easily receive a write/read circuit for each head. An equivalent device configuration can be obtained.

In addition, in the operating state, the write/read circuits are always in operation for all disk devices, but for the disk mechanism, only one selectively connected disk mechanism is turned on and operated, and the rest As a result, even if a plurality of disk devices are connected in parallel, the power consumption can be significantly reduced to approximately that of one disk device.

[Embodiment] FIG. 2 is a block diagram showing a first embodiment of the present invention.

In FIG. 2, 100 is a controller as a host device, and one or more hosts (not shown) are connected to the controller 100 via a channel.

In this embodiment, four disk devices 10-l to 10-4 are connected to the controller 100. The disk devices 10-1 to 10-4 have the same configuration. For example, taking the disk device ALIO-1 as an example, an interface circuit 28-L that performs bit transfer with the controller 100 transfers data during read access. It includes a read/write circuit 12-1 for writing data during read and write access, and a disk mechanism section 14-1. For example, the disk mechanism section 14-1 includes four heads 16.
-J to 16-4 are provided, and heads 16-1 to 16-4 are provided.
Four disks 34-1 to 34-4, which are rotated at a constant speed by a spindle motor 32, are provided correspondingly. Further, the positions of the heads 16-1 to 16-4 are controlled by a voice coil motor 30. Spindle motor 32
The voice coil motor 30 is controlled by a servo circuit which will be explained later.

A drive/drive provided in the disk devices 10-1 to 10-4.
Light circuits 12-1 to 12-4 and disk mechanism section 14-
1 to 14-4, a multiplexer 18 is provided as a switching means. The multiplexer 18 connects the four read/write circuits 12-1 to 12-4 to any one head group of the four disk mechanism units 14-1 to 14-4, that is, the four heads 16-1 to 16-4. selectively connect to. For example, when the heads 16-1 to 16-4 of the disk mechanism section l4-1 are selected, the read/write
The write circuit 12-1 is connected to the head 16-1, the read/write circuit 12-2 is connected to the head 16-2,
The read/write circuit l2-3 is connected to the head 16-3, and the read/write circuit l2-4 is connected to the head 16-4.
connected to.

Here, the solid line arrow shown in the multiplexer l8 indicates the connection relationship when the head selection of the disk mechanism section 14-1 has been performed, and the broken line arrow indicates the connection relationship when the head selection of the disk mechanism section 14-1 is performed.
The connection relationship when head selection 2 is performed is shown.

The multiplexer 18 is switched and controlled by a switching control section 20 provided as a control function of the controller 100.

In the switching control of the multiplexer 18 by the switching control unit 20, first, in the initial state where all the disks are unrecorded, the switching control unit 20 controls the disk mechanism unit 14-1 of the disk device 10-1 for write access. For this purpose, as shown by solid arrows in the multiplexer 18, each disk device 10-1 to 10-4 is provided with a read/write circuit 12-1 to 12-4 connected to the disk mechanism section 14-1. It is connected to each of the heads 16-1 to 16-4 provided in the.

The switching control unit 20 constantly monitors the write capacity for the disk mechanism unit 14-1, and when it determines that the disk is full, it switches to the head for the disk mechanism unit 14-2 of the next disk device 10-2. In the multiplexer 18, read/write circuits 12-1 to 12-4 are connected to each of the heads 16-1 to 16-4 of the disk mechanism section 14-2 as indicated by broken line arrows. .

Here, the disk capacity in the switching control unit 20 of the controller 100 is determined based on write access to the last track of the disk,
This can be determined by counting how many times parallel data transfer is performed in 4-bit units for 01 to 10-4.

FIG. 3 is a configuration diagram of the multiplexer 18 shown in FIG. 2, in which a changeover switch group 18-1 has built-in switches of four circuits corresponding to four disk devices 10-1 to 10-4.
~18-4 are provided, and a changeover switch group 18-1~1 is provided.
Read/write circuits 12-1 to 12- for 8-4
4 sides are commonly connected, and each switch group 18-1 to 18
-4 is connected to four groups of heads 16-1 to 16-4 provided for each disk mechanism side 14-1 to 14-4, respectively.

For the multiplexer 18 having such a configuration, the switching control unit 20 provided in the controller 100 as a control function performs switching according to a predetermined order at the time of write access to any one of the changeover switch groups 18-1 to 18-4. A control signal is output and turned on, and during read access, one of the switch groups corresponding to the read address is controlled to be turned on.

FIG. 4 shows the disk mechanism parts 14-1 to 14 shown in FIG.
FIG. 4 is a schematic configuration diagram illustrating 4 in more detail.

In FIG. 4, in this embodiment, the disk mechanism section 14 is provided with five disks 34-1 to 34-5 and eight heads 16-1 to 16-8. The disks 34-1 to 34-5 are rotated by a spindle motor 32 at a low speed of, for example, 3600 rpm.

In addition, the heads 16-1 to 16-4 are connected to the voice coil motor 3.
Positioning is controlled by 0. 5 discs 34-1
One of the disks 34-5 is a servo disk on which a servo signal is written, and a servo head is provided corresponding to this servo disk, and the voice coil motor 30 is controlled based on the servo signal read by the servo head. Positioning control and constant speed control of the spindle motor 32 are performed.

First, a servo circuit 40 for controlling the voice coil motor 30 includes a servo logic 42, a speed control circuit 44, a position control circuit 46, a coarse/fine switching circuit 48, and a power amplifier 50. That is, when track information corresponding to an appropriate access address is given from the disk controller 42, the servo logic 42 outputs a target speed signal to the speed control circuit 44, and detects the deviation from the actual speed signal obtained from the detection signal of the servo head. Based on this, the speed of the voice coil motor 30 is controlled by the power amplifier 50 via the coarse/fine switching circuit 48 which has been switched to the coarse side, and the head is moved to the target track. In controlling the speed of the head with respect to the target track, one track crossing pulse is obtained from the servo head each time the servo head crosses a track, so the servo logic 42 generates a track crossing pulse from the residual difference between the current track and the target track. is sequentially subtracted, and when the remaining track becomes zero, the coarse/fine switching circuit is switched from coarse to fine, and the position control circuit 46
By applying the output to the voice coil motor 30 via the power amplifier 50, control is switched to trace the head along the target track (on-track control).

Next, as a servo circuit 40 for the spindle motor 32, a PWM control circuit 52, a motor control circuit 54, and a power amplifier 56 are provided. As the spindle motor 32, for example, a brushless DC motor is used, and its rotation is controlled to a constant speed by PWM control.

That is, an index signal for detecting the actual rotation of the disk and a reference clock for determining the reference rotation are input to the PWM control circuit 52. That is, one index signal is obtained every time the disk rotates once, while the reference clock is generated according to the period of one revolution at a constant speed of 3600 rpm.

The PWM control circuit 52 detects the phase difference of the index signal with respect to the reference clock, and performs pulse width control on the motor control circuit 54 so as to make this phase difference zero. For example, when a three-phase, six-pole DC motor is used as the spindle motor 32, the motor control circuit 54 detects the coil phase switching of the stator coil using three Hall elements provided in the spindle motor 32, and detects the coil phase switching of the stator coil. A current is synchronously passed through one of the stator coils, and the pulse width is controlled by the control signal from the PWM control circuit 52 for the energization time according to the coil phase switching, and the rotation speed of the spindle motor 32 is controlled by the reference clock. Maintain a fixed rotation period.

Next, the operation of the embodiment shown in FIG. 2 will be explained.

Assuming that the controller 100 performs write access in the initial state where all disks in the disk devices 10-1 to 10-4 are in an unrecorded state, the multiplexer 18 performs read/write operations as shown by solid arrows. circuit 1
2-1 to 12-4 are connected to each of the four heads 161 to 16-4 provided in the disk mechanism section 14-1 of the first disk device 10-1. Of course, lead/
The write circuits 12-1 to 12-4 switch to a write mode in which the write data from the controller 100 is modulated and output to the head.

When the switching of the multiplexer 18 is completed, the controller 1
From 00, bits are transferred to the interfaces 28-1 to 28-4 in parallel in units of 4 bits b1 to b4, and the data bits BL are transferred from the read/write circuit 12-1 to the disk mechanism section via the multiplexer 18. 14-1, and is written on the disk 34-1.

At the same time, the data pit b2 is applied to the head 16-2 of the disk mechanism section 14-1 via the interface 28-2, the read/write circuit 12-2, and the multiplexer 18, and is written on the disk 34-2. Similarly, bit b
3 and b4, the disk 34- is also simultaneously driven by each of the heads 16-3 and 16-4 of the disk mechanism section 14-1.
3.34-4.

In this way, in write access in the ultra-high-speed disk device of the present invention, write data can be written in one time by transferring write data to multiple disk devices in parallel, which is different from the embodiment shown in FIG. For example, if the transfer rate of a conventional disk device is 3 MB/s, then 3
It is possible to achieve a transfer rate four times higher, which is MB/s X 4 = 12 MB/S.

The switching control unit 20 of the controller 100 selects the first selected disks 34-1 to 34-3 of the disk mechanism unit 14-1.
4-4 is full or not. For example, when a write access is made to the last track of the disk and a write completion notification is received, a switching control signal is output to multiplexer 18 at the time of the next write access. , head 1 of the next disk mechanism i14-2 as indicated by the dashed arrow
6-1 to 16-2.

Thereafter, when the disk mechanism section 14-2 becomes full, the system switches to the next disk mechanism section 14-3, and the disk mechanism section 14-2 is switched to the next disk mechanism section 14-3.
-3 becomes full, it switches to the last disk mechanism section 14-4.

Next, at the time of read access, the switching control unit 20 controls the disk mechanism unit 1 based on the read address obtained by the read access from the host to the controller 100.
4-1 to 14-4, and controls the multiplexer 18 to select the determined disk mechanism, and at the same time controls the servo circuit of the selected disk mechanism. By instructing read access to the head, the head is positioned, read out in parallel in units of 4 bits, and transferred to the controller 100.

FIG. 5 is an embodiment configuration diagram showing a second embodiment of the present invention, and this embodiment is similar to the embodiment of FIG. 2 in that the disk mechanism section of each disk device is activated in response to head selection. It is characterized by being equipped with a start control means.

In FIG. 5, the configuration of the controller 100 and the original disk devices 10-1 to 10-4 is the same as in FIG. 2, but in addition, a startup control circuit 70 is newly provided. When the startup control circuit 70 receives a determination signal from the controller 100 that determines the timing immediately before the disk becomes full in any currently selected disk mechanism, the startup control circuit 70 performs the next head selection according to a predetermined order. A start signal is output to the disk mechanism to be used, and the power is turned on.

That is, in the embodiment shown in FIG. 2, when the device is started, the controller 100 sends all disk devices
A power-on signal is supplied to 10-4 to bring it into an operating state. On the other hand, in the embodiment shown in FIG.
The data processing system including -4 is kept in an operating state with the power always on, but the disk mechanism section 14-1 to
As for 14-4, power is supplied only to the disk mechanism section whose head has been selected by the multiplexer 18, so that it is in an operating state.

For example, if the head selection of the disk mechanism section 14-1 is performed by the multiplexer 18 in write access, the startup control circuit 70 controls the disk mechanism section 14-1.
A power-on command is issued to the disk drive units 14-1 to 14-3 to set them in an operating state, but a power-off signal is supplied to the remaining disk mechanism units 14-1 to 14-3 to stop the power supply.

Then, the disk mechanism section 14 in the head selection state
Controller 100 just before disk 1 becomes full
When receiving the determination signal, the startup control circuit 70 outputs a power-on signal to the next disk mechanism section in a predetermined order, for example, the disk mechanism section 14-2, and the disk in the disk mechanism section 14-1 is activated. Immediately before the disc is full, the disk mechanism section 14-2, which will be next to be head selected, is put into an operating state, specifically, the spindle motor 32 is started to be in a constant speed rotation state, and the servo system of the voice coil motor 30 is turned on. Set the head positioning standby state.

Next, the controller 100 controls the disk mechanism section 14-1.
Suppose that it is determined that the disk is full, and the multiplexer 18 selects the head of the disk mechanism section 14-2 in the next write access.
Since the disk mechanism section 14-1 is already in operation, data can be written immediately without any idle time.

Note that the disk mechanism section 14-, which is already full of disks,
Regarding No. 1, since there is a possibility that read access to write data is performed randomly, the disk mechanism section 14-1 maintains the operating state thereafter.

Thereafter, in the same manner, the process of activating the next disk mechanism just before the head-selected disk becomes full is sequentially repeated.

By controlling the startup of the disk mechanism in this manner, the power supply to the disk mechanism in the idle state is cut off, so that the power consumption of the ultra-high speed disk device can be minimized.

FIG. 6 is an embodiment configuration diagram showing a third embodiment of the present invention. In this embodiment, the configuration on the disk device side of FIG. It is characterized by further increasing the transfer speed.

In FIG. 6, 60-1 to 60-4 are group units, and each of the group units 60-1 to 60-4 has an interface 28-1 to 28-2 shown in FIG.
8-4, read/write circuits 12-1 to 12-4, and disk mechanism units 14-1 to 14-4 are provided.

In FIG. 6, group unit 6 is shown for ease of explanation.
Regarding the disk device 10-1 belonging to 0-1, there is an interface 28-1, a read/write circuit 12-1, a disk mechanism section 14-1, and four heads 16-1 to 16 provided in the disk mechanism section 14-1. -4 is shown, but
For other parts, one disk device is shown by a horizontal bar, the interface and read/write circuit are each shown by a black circle, and the head mechanism section is shown by a simplified rectangular block.

Each group read/write circuit l2-1 to 12-4 in such group units 60-1 to 60-14
A multiplexer 22 as a switching means is provided between the disk mechanism sections 14-1 to 14-4 each having four heads 16-1 to 16-4. The multiplexer 22 connects the 16 read/write circuits on the controller 100 side to any of the disk mechanisms 14-1 to 14-4 of each group unit 60-1 to 60-4.
Selectively switch connections to different heads.

The multiplexer 22 is controlled by a switching control means 24 provided as a control function of the controller 100.

Here, from the controller 100, the group unit}60-
Assuming that parallel data transfer is performed in units of 4 bits b1 to b4 every 1 to 60-4, that is, parallel data transfer of a total of 16 bits is performed, for example, the switching control means 24 first selects the group unit 60-1. The multiplexer 22 is switched to select. By this switching of the multiplexer 22, the four read/write circuits 12-1 to 12-4 belonging to the group unit 60-1 are connected to the four heads 16 provided in the disk mechanism section 14-1 of the same group unit 60-1. -1 to 16-4.

Next disk mechanism section 14- of group unit 60-1
For the four heads provided in group unit 60-2, four read/write circuits 1 provided in group unit 60-2
2-1 to 12-4 are connected. In addition, the
Four single read/write circuits 12-1 to 12-4 provided in group unit 60-3 are connected to each head. Furthermore, 4 in group unit 60-1
Four read/write circuits 12-1 to 12-4 provided in the group unit 60-4 are connected to the four heads provided in the th disk mechanism section 14-4.

That is, for the head select of the group unit 60-1, the 16-bit data simultaneously transferred in parallel from the controller 100 is transmitted to the four group units 60-1 to 60-1.
The signal is modulated by 16 read/write circuits provided in 60-4 and applied in parallel to 16 heads in four disk mechanisms 14-1 to 14-4 of first group unit 60-1. group unit 60-1
data is simultaneously written to 16 discs.

The switching control unit 24 provided in the controller 100 monitors whether the disk in the group unit 60-1 is full or not. For example, upon receiving a notification of completion of write access to the last track of the disk, the switching control unit 24 switches the next write access. The multiplexer 22 is switched and connected to the 16 head groups on the group unit 60-2 side.

Of course, at the time of read access, the corresponding group unit can be determined from the read address, and after controlling the multiplexer 22 to switch so as to select the 16 head groups of the determined group unit, the selected group unit is A read access is commanded to the servo circuit of the disk mechanism section, and 16 bit data are read out in parallel and transferred to the controller 100.

Furthermore, a spindle synchronization circuit 62 is provided in common for the four disk mechanism sections 14-1 to 14-4 provided in the group units 60-1 to 60-4, and one
Since write access or read access is performed simultaneously by six heads, each disk mechanism section 14
A spindle synchronization circuit 62 is provided so that the rotational control of a total of four spindle motors 32 provided at -1 to 144 is synchronized. Specifically, spindle synchronization can be achieved by commonly supplying the reference clock for the PWM control circuit 52 for controlling the spindle motor 32 of the servo circuit 40 shown in FIG. 4 to the four disk mechanisms. .

To explain more specifically, the disk mechanism section 14-1
~14-4 are each equipped with a reference clock oscillator, but only one of the reference clock oscillators is enabled, the other reference clock oscillators are stopped, and the reference clock from a single reference clock oscillator is enabled. PWM control circuit 5 provided in the four disk mechanism sections 14-1 to 14-4
Commonly supplied to 2.

In the expansion system shown in FIG. 6, assuming that the transfer rate of one disk device is 3 MB/S, each group unit 60-1 has a transfer rate of 1 MB/S as shown in FIG.
It has a transfer rate of 2MB/s, and four group units with this transfer rate are connected in parallel, so the transfer rate is 12MB/s.
A transfer rate of B/sX4=48MB/S can be achieved.

FIG. 7 shows the head group switching operation performed in group units in the third embodiment shown in FIG.

FIG. 7(a) shows the selected state of the 16 head groups of the group unit 60-1 in FIG. 6, and for the head mechanism section 14-1, four read/write circuits belonging to the same group 12-1 to 12-4 are connected, but for each of the remaining four heads of head mechanism sections 14-2 to 14-4, four read/write circuits 12 in other group units 60-2 to 60-4 are connected. -1 to 12-4 are connected to each other.

When the disk of the group unit 60-l becomes full, as shown in FIG.
Switches to head select for six heads.

FIG. 8 is an embodiment configuration diagram showing a fourth embodiment of the present invention, and in this embodiment, the fifth embodiment is
A feature of this embodiment is that a group activation control circuit 80 similar to the second embodiment shown in the figure is provided.

In FIG. 8, the configurations of the controller 100 and group units 60-1 to 60-4 are the same as in FIG. 6, but a group activation control circuit 80 is newly provided.

The group activation control circuit 80 controls the group unit 60-
Controls the power supply to four disk mechanism units 14-1 to 14-4 provided for each disk mechanism unit 1 to 60-4.

That is, when the ultra-high-speed disk device is in operation, power is constantly supplied to the data processing system including the interface, read/write circuit, multiplexer, and head in each group unit 60-1 to 60-4. condition.

However, in the disk mechanism section, power is supplied only to the group unit for which head selection has been performed to bring it into operation. This control of supplying power to only the disk mechanism of the group unit for which head selection is being performed to bring it into operation is effective only during write access.

For example, when the group unit 60-l is head-selected for write access, the group activation control circuit 8
0 is the disk mechanism section 14- of the group unit 60-1.
A power-on command is issued to 1 to 14-4, and the disk mechanism units 14-1 to 1 of the remaining three group units 60-2 to 60-4 are brought into operation by supplying power.
For each of 4-4, a power-off command is issued to stop the power supply.

Since the switching control unit 20 provided in the controller 100 has a function of determining when the disk is full, it detects when the disk of the group unit 60-l currently undergoing head selection becomes full. The determination is made and a determination output is generated to the group activation control circuit 80. Upon receiving this determination output, the group activation control circuit 80 selects the next group unit to be connected, for example, group unit 60-.
A power-on command is given to the disk mechanisms 14-1 to 14-4 of No. 2 to bring them into operation. Specifically, the servo circuit 40 shown in FIG. 4 is activated to control the spindle motor 32.
is rotated at a constant speed, and a standby state for head positioning control by the voice coil motor 30 is created.

Therefore, when the switching control unit 24 of the controller 100 determines that the disk of the group unit 60-1 is full and the multiplexer 22 selects the head of the group unit 60-2 from the next write access, , the disk mechanisms 14-1 to 14-4 of the group unit 60-2 are already in operation and can immediately respond to bit access from the controller 100.

Furthermore, since the power supply to the disk mechanisms belonging to the group unit in which the disk is in an empty state is stopped, the power consumption of the entire apparatus can be sufficiently reduced. Note that read access is performed randomly for group units for which disk writing has already been performed, so that the operating state of the disk mechanism is maintained thereafter.

The above embodiments take as an example the case where one disk device is provided with four heads, but if, for example, the number of heads in one disk device is n, the embodiment shown in FIG. Alternatively, it can be generalized so that n disk devices 10-1 to 10-n are connected in parallel to the controller 100. Also, regarding the expansion system shown in Figure 6, if the number of heads in one disk device is n, then
The number of heads in one group unit is nXn.

Therefore, it can be generally expressed that a group unit consisting of n disk devices is connected in parallel to n controllers 100, and n×n bits are transferred in parallel to and from the controller 100 at the same time.

[Effects of the Invention] As explained above, according to the present invention, it is possible to set up a plurality of heads for each disk device for each disk device without impairing the structure and operation of the existing disk device. High-speed access is achieved by selectively connecting the read/write circuits that are connected to each other and performing parallel bit transfer with the host device.

In addition, during write access, by cutting off the power supply to the disk mechanism corresponding to an empty disk that has not been head-selected, even if multiple disk devices are connected in parallel to the host device, the device Overall power consumption can be significantly reduced.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention; Fig. 2 is a block diagram of a first embodiment of the present invention; Fig. 3 is a block diagram of the multiplexer shown in Fig. 2; Fig. 4 is a schematic diagram of the disk mechanism used in the present invention. Figure 5 is a configuration diagram of a second embodiment of the present invention; Figure 6 is a configuration diagram of a third embodiment of the invention; Figure 7 is an explanatory diagram of the switching state of the embodiment of Figure 6; A configuration diagram of a fourth embodiment of the present invention: FIG. 9 is a configuration diagram of a conventional device; FIG. 10 is a configuration diagram of another conventional device. In the figure, 10-1 to 10-n: Disk devices 12-1 to 12-n: Write/read circuit (read/write circuit) 14-1 to 14-n: Disk mechanism units 16-1 to 16-n: Head 18.22: Switching means (multiplexer) 20.24:
Switching control means 28-1 to 28-n: Interface 30: Voice coil motor 32: Spindle motors 34-1 to 34-4: Disk 40: Servo circuit 42: Servo logic 44: Speed control circuit 46: Position control circuit 48: Coarse/fine switching circuit 50.56: Power amplifier 52: PWM control circuit 54: Motor control circuit 70: Starting control circuit 80: Group starting control circuit 100: Host device (controller)

Claims (1)

[Claims] (1) When the number of bits transferred in parallel with the host device is n, the number of disk devices (
10-1 to 10-n) are connected in parallel to a host device, and each of the disk devices (10-1 to 10-n) has at least the heads (16-1 to 16-n) corresponding to the number n of bits.
(14-1 to 14-n))
and a write/read circuit ((12-1 to 12-n) provided in each disk device (10-1 to 10-n), and further includes a write/read circuit ((12-1 to 12-n)). 1 to 12-n)
and a switching means (18) for selectively connecting the heads (16-1 to 16-n) belonging to any one of the disk mechanism sections (14-1 to 140n); Write/read circuit (12-1 to 12
-n) belonging to a specific disk mechanism section (14-i) according to a predetermined switching order (16-1 to 16-n).
) and writes data until the disk is full, and at the time of read access, the head (16-i) belonging to the specific disk mechanism section (14-i) corresponding to the access is
-1 to 16-n) to the write/read circuits (12-1 to 12-n).
-n) for parallel readout.
) and; Ultra high-speed disk device. (2) In the ultra-high speed disk device according to claim 1, among the disk mechanism sections (14-1 to 14-n) of the plurality of disk devices (10-1 to 10-n), the switching control means (20), the write/read circuits (12-1 to 12-
n) Supply power only to the disk mechanism connected to the disk mechanism to bring it into operation, and immediately before the disk in that disk mechanism becomes full, power is supplied to the disk mechanism that will be switched next to be connected. 2. The ultra-high speed disk device according to claim 1, further comprising a start control means (22) for starting at least the spindle motor. (3) n disk devices each (10-1 to 10-n)
n groups are connected in parallel to a host device as one group, and a total of n×n bits are transferred in parallel between each group and the host device in units of n bits, and the plurality of groups are Disk devices (10-1~
10-n) each includes a disk mechanism section (14-1 to 14-n) equipped with heads (16-1 to 16-n) for at least n parallel transfer bits, and each disk device (10-n).
Write/read circuits (10-1 to 10-n) provided for each
2-1 to 12-n), and further includes a plurality of write/read circuits (12-n) belonging to a specific group.
2-1 to 12-n) to one of the heads (16-1 to 16-n) of the disk mechanism units (14-1 to 14-n) belonging to the same group or another group. Switching means (24): During write access, one disk mechanism unit (14-1) belonging to a group selected according to a predetermined switching order.
Write/read circuits of the same group (12-1 to 12-n)
At the same time, connect the heads (16-2 to 14-n) of the remaining disk mechanisms (14-2 to 14-n) belonging to the selected group.
1 to 16-n) are write/read circuits (12-n) of other groups.
-1 to 12-n) are connected in groups and data is written until the disk is full. During read access, the disk mechanisms (14-1 to 14-n) belonging to the specific group corresponding to the access are Head (16-1
16-n) to write/read circuits of all groups for parallel reading; and a super high-speed disk device. (5) The ultra-high speed disk device according to claim 1, further comprising a disk mechanism section (14-1 to 1
4-n) A super high-speed disk device characterized in that a spindle synchronization circuit is provided for synchronizing the rotation of spindle motors of each disk mechanism section. (6) In the ultra-high-speed disk device according to claim 3, a group of disk mechanisms (14-1 to 14) selectively connected by the switching control means (24) among the plurality of groups of disk mechanisms. -n) to bring it into operation, and immediately before the disks in the group become full, power is supplied to the disk mechanisms (14-1 to 14-n) of the other groups that will be switched and connected next. An ultra-high speed disk device characterized in that it is provided with a start control means (26) for starting at least each spindle motor.