JPH039427A - Microprogram controller - Google Patents

Abstract

PURPOSE:To attain optimum overlay control by providing the controller with a physical address conversion circuit converting a logical address into a physical address, then comparing a non-resident microprogram(muP) logical address loaded to an overlay area with the logical address of an address register used for the current access. CONSTITUTION:The address register 1 holds a physical address capable of accessing a logical area including a control storage device 3 and an external memory 8 and a physical address converting circuit 2 converts the logical address into a physical address. At the time of confirming a non-resident muP is not stored, a comparator 6 executes control for storing the logical address included in a resident area 15 in the address register 1 and a load control means 7 controlled by an overlay control muP read out from the resident area 15 in accordance with the logical address loads the relevant non-resident muP from the external memory 8 to the overlay area 10. Thus, the address including the control storage device 3 and the external memory 8 can be used to attain control.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control device, and particularly to a microprogram control device employing an overlay control method.

[Conventional technology]

The storage area of the control storage device is transferred to the resident microprogram (
The overlay area is divided into a resident area that stores a microprogram (hereinafter referred to as μP) and an overlay area that stores non-resident μPs. An overlay control type μP control device has been proposed which aims to effectively utilize an expensive control storage device and increase the total amount of μP by loading.

Conventionally, this type of μPi! In the II control device, an address register that holds an address (physical address) with a number of bits that can be accessed by the number of words in the control storage device is used, and the control storage device is accessed using the physical address. And overlay control was executed as follows. First, the start address of the subroutine that performs overlay control stored in the resident area of the control storage device, that is, the overlay system? The starting address of the III μP is indicated in the previous step of its overlay control μP, and at the same time, the starting address of the overlay area holding the μP loaded from the external memory is pushed onto the stack. and,
After loading μP from external memory into the overlay area by executing the overlay control μP, the pumped start address is popped in the final step of the overlay control μP, and μP execution starts from the pumped start address in the overlay area. It is controlled so that it is carried out. In order to enable the above operations, firmware coding must be done with overlay control in mind.

[Problems to be Solved by the Invention] The μP control device using the conventional overlay control method described above stores in an address register a physical address with a number of bits that can access only the number of words in the control storage device. Since the resident area and overlay 2M area are accessed, it is not possible to specify the μP to be loaded from external memory under overlay control using only the address held in the address register. In other words, since there is no address system that includes the control storage device and external memory, and the physical address for the control storage device is always held in the address register, it is possible to load μP from external memory into the overlay area and execute it. The address register is an address that points to the overlay area of the control storage even when the overlay is in progress, and it is not possible to tell which μP among the overlay target μPs is being executed just from the address held in the address register. . For this reason, it is no longer possible to effectively control debug processing or the like by stopping the operation when the address held in the address register matches a predetermined address. Similarly, certain types of information processing devices have a function to measure the μP words actually executed by the check program that checks the validity of the μP (firmware coverage measurement function), but such a function is also incomplete. shall be. Further, in the firmware coding work, it is necessary to code with strong awareness of overlay control, and this increases the number of firmware steps, leading to a decrease in the performance of overlay control and, by extension, a decrease in the performance of the μP control device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a μP control device using an overlay control method that can perform control using addresses that include a control storage device and an external memory in order to solve such conventional problems. be.

[Failure to solve the problem]

In order to achieve the above object, the present invention provides an overlay type μP comprising a control storage device having a resident area for storing resident μPs and an overlay area for storing non-resident μPs, and an external memory storing the non-resident μPs. The control device includes an address register that holds a logical address with a number of bits that can access a logical area including the control storage device and the external memory, and the logical address held in this address register as an address for the control storage device. A physical address conversion circuit that converts to a certain physical address, a logical address register that holds the logical address of the non-resident μP loaded in the overlay area, and a comparison between the output of this logical address register and the output of the address register. A comparator that performs control to hold the logical address of the overlay control μP in the resident area in the address register when it is determined that the non-resident μP to be executed is not held in the overlay area, and control of this comparator. The overlay control μP read from the resident area according to the logical address held in the address register by
and load control means for loading the corresponding non-resident μP from the external memory into the overlay area.

[Effect]

In the μP control device of the present invention, the address register holds logical addresses of the number of pits that can access the logical area including the control storage device and external memory, and the physical address conversion circuit stores the logical addresses held in the address register. is converted into a physical address that is an address for the control storage device. On the other hand, a comparator holds the non-resident μP to be executed next in the overlay area by comparing the output of the logical address register that holds the logical address of the non-resident μP loaded in the overlay area with the output of the atros register. If it is confirmed that the overlay control μP in the resident area is not
A load control means controlled by the overlay control μP that is read out from the resident area according to the logical address held in the address register stores the logical address of the non-resident μP in the corresponding non-resident μP. is loaded from external memory into the overlay area.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of essential parts of an embodiment of the μP control device of the present invention. The μP control device of this embodiment includes an address register 1, a physical address conversion circuit 2, a control storage device 3, a read register 4, and a logical address register 5.
, a comparator 6 , a load control circuit 7 , an external memory 8 , a selector 9 and a selector 14 . Each has the following configurations and functions.

O-control storage device 3 consists of a resident area 15 and an overlay area 10. For example, its capacity is 8KW, and as shown in Fig. 3, it has a physical space of 0000 (ゎ ~ IFFF +. It is allocated to area 15. Overlay control μP is allocated to resident area 15.
and other resident μPs are stored. Additionally, a non-resident μP loaded from the external memory 8 as described later is stored in the overlay area 10. In this example, the overlay unit is a maximum of 256W in hardware,
The overlay area 10 can be divided into a plurality of overlay areas. Therefore, the overlay unit is also 2.
As long as it is within 56W, the number of words can be determined arbitrarily.

O External memory 8 Stores non-resident μP. For example, its capacity is 8KW, which is the same as the control storage device 3.

O address register 1 The logical space shown in FIG.
A logical address of the number of bits (14 bits) that can be accessed (16KW) is stored. Here, to explain the relationship between physical space and logical space with reference to FIG. 3, the logical space indicated by the logical address is oooo□, ~3 F F F
on 16KW, of which o o o o
8KW of fllll ~ I F F F ,,, coincides with the physical space, and 2000 on ~ 3FFF (Ill
8KW is allocated to the external memory 8. That is, either the control storage device 3 or the external memory 8 is selected based on the value of the most significant bit (0th bit) of the 14-bit logical address held in the address register 1, and
The 5th bit output divides the capacity (8KW) into 32 units of 256W, and the 6th to 13th pin outputs divide the 256W into 256W units.
Access inside. 2000+ by overlay control described later. The non-resident μP in the logical space of ~3 F F F ,... is in the overlay area 10 of the control storage device
It is loaded as appropriate.

O Physical address conversion circuit 2 This is a circuit that inputs the logical address held in the address register 1 and converts it into a physical address used for accessing the control storage device 3. An example thereof is shown in FIG. The physical address conversion circuit 2 in the figure converts the inverted value of the most significant bit (0th bit) of the address register 1 and the
The Nant gates 21 to 25 each take the NAND condition with the inverted value of the value of the bit, and the outputs of the Nant gates 21 to 25 and the output of the 6th to 13th bits of the address register 1 are combined to form a 13-bit configuration. It is composed of a synthesis circuit 26 that generates physical addresses. When the value of the 0th bit, which is the most significant bit of address register l, is "1", that is, 2000+ゎ~3FFF (When accessing the external memory 8 located in Ml, the logical address and physical As shown in the correspondence diagram with addresses, control is converted into a physical address that accesses the overlay area 10 of the storage device 3, and if the most significant bit is r□, it is converted into a physical address that accesses the resident area 15. .

O logical address register 5 2000 ++n ~ 3 F F F (Works to hold only the logical address that accesses the logical area of Ml. In other words, the logic of μP loaded or held in the overlay control time area 10 This is a register that holds addresses.

O comparator 6 When the most significant bit of address register 1 is "1", compares the upper 6 bits of address register 1 (0th to 5th pin bits) with the upper 6 bits of logical address register 5. Then, it is detected whether the non-resident IP of the logical address held in the logical address register 5 is already held in the overlay area 10. If they do not match, the corresponding non-resident μP is not held in the overlay area 10, and therefore an indexing signal 11 for the first address of the overlay control μP stored in the resident area 15 is generated. The starting address of the overlay control μP is a fixed address, and in response to the index signal 11, the selector 9
is arranged to select that fixed address and write it to address register l.

○Load control circuit 7 is activated by the index signal 11 output from the comparator 6, and during overlay control, loads the non-resident μP pointed to by the logical address held in the address register 1 from the external memory 8 into the overlay area 10 in overlay units of 256W. This is a circuit that controls loading. This load control circuit 7 is controlled by an overlay control μP read from the control storage 3 and supplied via the read register 4. Note that a write signal 12. is sent from the load control circuit 7 to the control storage device 3. The write data 13 is output, and the non-resident μP is loaded by these data.

O selector 9 This is means for selecting the starting address, the output of the logical address register 5, and the starting address of an overlay control μP (not shown) and inputting them to the address register 1.

O selector 14 selects the output of the address register 1 and the output of the logical address register 5 using the index signal 11 as a select control signal and inputs it to the 'ζ logical address register 5, and the logical address register 5 is stored in the overlay area 10. It functions to hold the logical address of non-resident μP.

Next, the operation of the μP control device of this embodiment configured as described above will be explained.

When the logical address of μP is set in the address register 1, the physical address conversion circuit 2 converts it into a physical address, and the control storage device 3 is accessed using this physical address. The μP read from the control storage device 3 is sent to the read register 4, and known operations such as decoding are performed thereon.

In parallel with the above operation, the output of the logical address register 5 holding the logical address of the non-resident μP stored in the overlay area 10 and the output of the address register 1 are input to the comparator 6. At this time, address register 1
2 if the most significant bit output from
000. The access will be in the range of □ to 3 F F F , . . . If the two values match, the corresponding non-resident μP has already been stored in the overlay area 10 and a valid readout has been performed. , the index signal 11 which is the output of the comparator 6 is not valid, and the fixed address of the overlay control μP is not determined.

Therefore, the overlay area 10 of the control storage device 3 is
The μP that had been read from is executed.

On the other hand, if a mismatch is detected in the comparator 6, the index signal 11 of the comparator 6 is enabled, the load control circuit 7 is activated, and the first address of the overlay control μP is transferred to the address register 1 via the selector 9. is set to

Note that the logical address originally set in the address register 1 is transferred to the logical address register 5 via the selector 14.
At the same time, the load control circuit 7 is notified.

Next, at °C, the first address of the overlay control μP written to address register 1 is transferred to physical address conversion circuit 2.
The control storage device 3 is accessed by converting it into a physical address, and the overlay control μP is stored in the read register 4.
is set. The load control circuit 7 is controlled by the overlay control μP set in the read register 4, and the load control circuit 7 starts load control. That is, the external memory 8 is accessed, the non-resident μP in the external memory 8 pointed to by the notified logical address is read out in overlay units (256W), and the write signal 12
．． The overlay area 10 of the control storage device 3 is loaded by the write data signal 13 .

When the above loading is completed, the logical address that has been written to the logical address register 5 is set to the address register 1 via the selector 9, and the physical address conversion circuit 2 converts the logical address into a physical address and stores it in the control memory. The device 3 is accessed and the loaded non-resident μP is read into the read register 4. At this time, the logical address register 5 is holding the logical address set in the address register 1, and therefore the comparator 6
The comparison result between the output of the address register 1 and the output of the logical address register 5 at is a match. That is, it is confirmed that the overlay area 10 stores the non-resident μP corresponding to the logical address held by the address register 1, so the read register 4 stores the read μP.
P will be validly executed without being invalidated.

〔Effect of the invention〕

As explained above, in the μP control device of the present invention, by providing a physical address conversion circuit that converts a logical address into a physical address, the logical address including the control storage device and external memory can be held in the address register. This makes it possible to perform controls such as overlay control. As a result, it is possible to identify all μPs, including non-resident μPs related to multiple overlay modules stored in external memory, using only the addresses held in the address register, making debugging processing and firmware coverage measurements effective. It becomes possible to implement it. In addition, firmware coding can be done without being too conscious of overlays, reducing firmware steps during overlay control and improving the performance of the μP control device. Furthermore, by comparing the logical address of the non-resident μP loaded in the overlay area in the control storage device with the logical address of the address register related to the current access, it is determined whether the non-resident μP that should be executed is held in the overlay area. The target non-resident μ is already in the overlay area.
If P is loaded, it can be executed as is, so there is no wasted loading operation, and the overlay unit can also be varied, making it possible to realize efficient and optimal overlay control.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a main part of an embodiment of the present invention, FIG. 2 is a diagram showing an example of the configuration of a physical address conversion circuit, and FIG. 3 is a diagram showing the correspondence between logical addresses and physical addresses. In the figure, 1... Address register 2... Physical address conversion circuit 3... Control storage device 4... Read register 5... Logical address register 6... Comparator 7... Load control circuit 8...External memory 9.14...Selector 10...Overlay area 11...Identification signal 12...Write signal 13...Write data signal Main block of main part of ψj of all dates and months Figure 1 Figure 15...Resident area

Claims (1)

[Scope of Claims] An overlay type microprogram control device comprising a control storage device having a resident area for storing a resident microprogram and an overlay area for storing a non-resident microprogram, and an external memory storing the non-resident microprogram. an address register that holds a logical address with a number of bits that can access a logical area that includes the control storage device and the external memory; and a physical address that is an address for the control storage device, and a physical address conversion circuit that converts the address into an address; a logical address register that holds the logical address of the non-resident microprogram loaded in the overlay area; a comparator that performs control to hold a logical address of an overlay control microprogram in the resident area in the address register when it is determined that a non-resident microprogram to be executed is not held in the area; load control means that is controlled by the overlay control microprogram read from the resident area according to a logical address held in the address register and loads a corresponding non-resident microprogram from the external memory into the overlay area; A microprogram control device characterized by comprising: