JPS58213349A - Information processor - Google Patents

Abstract

PURPOSE:To improve the reliability of processing, by storing a copy of a control storage on a main storage, and using a data of the same address on the main storage if the data of the control storage is failed, and maintaining the continuity of the processing. CONSTITUTION:A microprogram muPG is stored in the control storage 1, this address is designated with an address control unit 13, the muPG read out from the storage 1 is stored tentatively in a register 2 and then the muPG from the register 2 is executed with an execution unit 4. A main storage unit 7 is controlled with a main storage access control unit 6 so as to store the same muPG as that stored in the storage 1. An output of the register 2 is checked at an odd/even number check circuit 20, and when an error is detected, the execution of the execution unit 4 is interrupted, the unit 13 changes the address of the muPG in error of the storage 1 into the address of the same muPG of the main storage, reads out the same muPG from the main storage 7 via the unit 6 and performs the execution again by applying the address to the execution unit 4 via the register 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Description of the technical field to which the invention pertains] The present invention relates to a microprogram control information processing device. In particular, it relates to an automatic data correction circuit when there is an error in microprogram data.

[Description of prior art]

Conventionally, in order to maintain the reliability of information processing, various check circuits have been added to information processing equipment, and retry processing, automatic correction processing, fallback processing, etc. have been performed regarding the errors detected by these check circuits. is being carried out. In particular, recent information processing devices have become mainstream with microprogram control systems called firmware, from the perspective of improving flexibility in hardware design and converting software technology into hardware to speed up processing. Ta. Moreover, microprograms are becoming more and more complex, and the number of program steps is also increasing. Correspondingly, control memory for storing microprograms has also become faster and has a larger capacity. For this reason, storage elements used for control storage are becoming highly integrated.

However, on the other hand, it is necessary to take measures to prevent the reliability of control memory from decreasing due to high-speed, large-scale copying. Therefore, error checking and correction (ECC) codes are added to control memory to automatically correct data errors. Alternatively, detection is being carried out. However, the ECC code check circuit and correction circuit are complicated, and the circuit delay of this circuit becomes severe, resulting in an increase in hardware and disadvantages in speeding up the device. The drawback is that it requires hardware. There is also a method that simply adds parity pits to the control memory to detect data errors, but in this case, error correction cannot be performed, which is likely to be fatal to the device.

[Detailed description of the invention]

The present invention improves this point by storing the same data as the data stored in the control memory in the main memory, and in the event of an error in the data in the control memory, the data at the same address in the main memory is stored. The purpose of the present invention is to maintain continuity of processing, increase the reliability of processing of an information processing device, and provide a highly reliable information processing device.

[Summary of the invention]

The present invention includes a control storage unit that stores a microprogram, an execution unit that executes control according to instructions of the microprogram, a main storage unit, a main storage access control unit, and a control storage that controls addresses of the control storage unit. an information processing apparatus comprising a control unit, means for storing and holding data identical to the microprogram data stored in the control memory in a specific area of the main memory; and a register for storing the microprogram data read from the control memory; means for storing data from main memory; means for performing an error check upon adding an error check bit to the microprogram data and storing it in the register; means for interrupting the execution of the error storage control unit and instructing the side storage control unit to read the same data as the microprogram data in which the error was detected stored in the main memory; () and means for resuming execution of the microprogram in accordance with the storage instruction.

[Explanation with drawings]

This will be explained in detail based on the drawings.

FIG. 1 is a block diagram of main parts of a conventional microprogram control information processing device. In Figure 1, 1 is control memory;
2 is a register for storing microprogram data, 3
1 is a control memory address control unit, 4 is an execution unit, 5 is an error detection/correction circuit, 6 is a main memory access control unit, and 7 is a main memory unit. now,
The execution unit 4 performs the necessary operations by reading microprogram data from the control memory 1 via the data line 9, storing it in the register 2, and decoding the output of the register 2. At the same time, the next address of the control memory 1 is calculated by the address control unit 3 using the data line IO, and the address il! 11 accesses the control memory 1.

On the other hand, the error detection and correction circuit 5 checks the contents of the register 2, and if there is a large error, the signal line 12 becomes "0" and setting of the next microprogram data in the register 2 is not inhibited. If there is an error, only the signal line becomes "1" and the execution of the microprogram is interrupted. At the same time, the error detection and correction circuit 5 usually detects the erroneous bit in the contents of the register 2 only in the case of a 1-bit error, and by inverting it, the contents of the register 2 are rewritten through the data line 13.

When the rewriting is completed, the suspension of execution is canceled and the execution unit 4 performs the necessary operations. If the error is 2 or more bits and cannot be corrected, it is trapped in the error processing routine and appropriate error processing is executed.

The signal line 14 is an access request from the execution unit 4 to the main memory unit 7, and data@15 means the address and data of the main memory unit 7. The data line 16 is the microprogram data and execution instruction to the execution unit 4, and the signal M17 is the control line for the address of the control memory 1 and is used to instruct the error trap address, interrupt address, etc.

The signal line 18 is used when the microprogram is stored in the main memory unit 7 instead of the control memory 1, and indicates a read instruction and address for the main memory unit 7, and the data line 19 is used when the microprogram is stored in the main memory unit 7. Used for replying microprogram data. Normally, access to the main memory unit 7 is several times slower than access to the control memory 1, so infrequently used microprograms such as exceptional processing are often stored in the main memory unit 7. The area is guarded so that it cannot be accessed by software.

As described above, it is becoming common for conventional microprogram-controlled information processing devices to be equipped with an automatic correction circuit such as the error detection and correction circuit 5 for errors in microprogram data. No. 5 requires a large number of exclusive OR (EX'OR) circuits and a large number of gate circuits for correction, which is disadvantageous in that it increases the amount of hardware. Furthermore, there is a disadvantage that the delay time from when data is stored in the register 2 to when a check signal is outputted through the error detection and correction circuit 5 becomes long.

Further, in order to eliminate the above-mentioned disadvantage, there is a method in which the data check circuit performs an odd-even test, but with this method, data errors cannot be corrected.

FIG. 2 is a block diagram of main parts of an embodiment of the present invention. Compared to the conventional example shown in FIG. The main storage unit 7 is characterized in that it issues an access instruction to the main storage unit 7, that the contents of the control storage 1 are held in the main storage unit, and that the address control unit 3 is configured as shown in FIG.

Other points are similar to the conventional example shown in FIG. 1, and the same reference numerals indicate the same parts.

FIG. 3 shows an address control unit 3 which is a feature of the present invention.
and FIG. 5, which is a detailed diagram of the odd-even check circuit 20,
δ is a register that stores the current address of the control memory 1, and this output is led to a counter 26 that counts +1. The output of this counter 26 is led to an information switching circuit r and a register 28 that stores the return address of the subroutine of the microprogram.

This information switching circuit 27 includes the register 28 and the register 2.
and the output of the register 29 which stores the return address from the index interrupt destination when an index interrupt occurs in the microprogram. This output is led to a register 29 and an information switching circuit 30.

Further, the output of the index interrupt address generation circuit 31 and the output of the register 25 are guided to the information switching circuit 30, and the output is guided to the signal a11, the register 25, and the main memory access address generation circuit 32.

The output of the fixed address generation circuit section is also led to this main memory access address generation circuit 32.

Further, the contents of the register 2 are led to the odd-even check section, and the output thereof is led to the flip-flop 36 and one input terminal of the OR circuit M. The other input terminal of this OR circuit 37 is led to the output of the flip-flop.

FIG. 4 is an explanatory diagram of the main memory unit 7.

The storage areas of the main memory include a microprogram area A1 on the main memory, an area A2 that stores the same microprogram as the microprogram on the control memory, and a software area M.
It is composed of A3.

With this longevity circuit configuration, the information switching circuit n% (9) selects an address for accessing the control memory 1.

That is, the information switching circuit γ divides the address specified by the microprogram data (microinstruction) stored in the register 2, and in the case of a conditional branch, the address determined by the branch condition a given from the execution unit 12. Select whether to use the contents of register fi29 as the address in the case of interrupt processing, to use the contents of register fi29 as the address at the end of the subroutine, or to use the address incremented from the current address indicated by the counter 26 as the address. do. This selection condition is an address switching condition, and this condition is specified by a microprogram during the operation of the information processing device. In addition, the information switching circuit (material) receives the output of the information switching circuit n, the output of the indexing interrupt address generation circuit 31 that stores a fixed address when an indexing interrupt condition occurs, and the odd-even check error of the microprogram data. When this occurs, a switching circuit selects the output of the register, and the output C is sent to the address line 11 and becomes an address for accessing the control memory 1.

In addition, the odd-even number check section performs an odd-even check on the microprogram in register 2, and when an error is detected, the output G becomes a logic
1”. At this time, flip-flop 36 is set. OR circuit a is the above output G and 7 lip 70 lip 3
The output d of 6 is logically summed and outputted to the execution unit 4 through the entire execution interrupt instruction signal e signal line 12. In addition, the output d of the flip-flop 36 requests the main memory to read the microprogram, and the information switching circuit 30t register 2
5 outputs are selected.

Further, if there is an odd-even check error, the fixed address generation circuit 33 instructs the upper bit of ml to access between the A2 areas m1 and m2 of the main memory in FIG. 4. The main memory address generation circuit 32 is a circuit that mixes the address specified by the output C with the contents of the fixed address generation circuit and converts it into a main memory address. It is used for addressing microprograms that reside in A and can operate at relatively low speeds. When specifying area A1, the fixed address generation circuit is set to "0" as shown in FIG.

Now, the case where an odd-even check error occurs in the microprogram data while the information processing device is operating will be explained in detail with reference to the time chart shown in FIG.

In Figure 5, CL is the clock, R2 is the contents of register 2,
ADD is the control memory address, R25 is the address stored in the register δ, G is the output of the odd/even number check section, d is the output of the flip-flop 36, main memory data reply signal, and e is the output of the OR circuit 37, respectively. show.

If an odd-even check error occurs when data D2 is stored in register 2, an error signal G is output,
An execution interruption instruction e is issued. As a result, at the next clock OL, the contents of the register 2 do not change, and the execution unit 4 does not perform any calculations. Next, the flip-flop section is set and a request is issued to the main memory unit 7 to read the microprogram data. The main memory address at this time is ((higher of m) + R2), and the same data as the data in the fi'I control memory 1 previously stored on the main memory unit 7 is read out, and the main memory data reply is Data D2' is set in register 2 by signal f. At the same time, the flip-flop is reset. Here, the contents of register 25 a2
does not change, and operates so that the next address a5 is set at the next clock after the suspension of execution is canceled, and arithmetic operations in the execution unit 4 are also executed at the same clock. Thereby, even if the data in the control memory 1 has an error, the information processing apparatus can continue to operate using the data in the alternative main memory unit 7.

Here, although the method of the present invention uses a large amount of main storage area, this problem is no longer a problem in terms of the capacity occupied by the entire information processing device due to the recent high integration and low cost of dynamic memories for main storage. In addition, the method of storing microprogram data in a specific area of the main memory can be easily done using conventional technology such as the method of storing it from external storage (disk file, etc.) at the time of initial setting of the information processing device, and accessing this area by a software program is possible. Measures to prevent destruction can also be easily achieved using conventional techniques.

In this embodiment, an odd-even check circuit is used to check the microprogram data, but it may also be an error detection and correction circuit. The reliability can be improved compared to conventional equipment.

[Detailed description of the invention]

As explained above, according to the present invention, by simply holding a copy of the control memory in the main memory and adding a simple circuit, all errors detected by parity checking of microprogram data can be treated as correctable errors. This has the excellent effect of improving the reliability of information processing equipment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts of a conventional example. FIG. 2 is a block diagram of a main part of an embodiment of the present invention. FIG. 3 is a detailed diagram of the address control unit and the odd-even check circuit. FIG. 4 is an explanatory diagram of the main memory unit. Figure 5 is an operation time chart. 1... Control memory, 2.25.28, 4... Register, 3... Address control unit, 4... Execution unit, 5... Error detection and correction circuit, 6... Main memory access Control unit, 7... Main memory unit, 20...
- Odd-even number check circuit, r130 --- Information switching circuit. Patent Applicant: Memoto Electric Co., Ltd. Agent and Patent Attorney: Naotaka Ide

Claims (1)

[Claims] (1) A main memory unit, a control memory that stores a microprogram, an address control unit that controls the address of this control memory, a memory circuit that temporarily stores the microprogram read from the control memory, and this memory circuit. In the information processing apparatus, the main memory unit K is controlled to store the same microprogram as the microprogram stored in the control memory, and the main memory unit K is controlled to store the same microprogram as the microprogram stored in the control memory, and an odd-even number check circuit for checking an error check bit provided in the memory circuit, and a circuit for changing the address of the microprogram in the memory circuit to the address where the microprogram is stored in the main memory unit; When an error detection signal is sent from the circuit, execution in the execution unit is interrupted, and the same microprogram as the microprogram in which this error was detected is read from the main memory unit at the address of the circuit to be changed and stored in the memory. An information processing device characterized in that it is stored in a circuit and is stored in a circuit so as to perform malicious operations.