JPH0391383A - Field index device - Google Patents

Abstract

PURPOSE:To obtain a field discrimination output and to attain interlace display by varying a phase of a generated signal as a field index signal when the infor mation of phase comparison result is dissident consecutively for N fields. CONSTITUTION:Field index information in 30Hz is capable being obtained from two systems of this circuit, a system of the side of a quantity comparator 18, and a system of the side of a frequency divider 20, but a field index output used actually is obtained from an output of the frequency divider 20. This is because that the result of phase comparison shows an error over plural fields, a phase correction circuit 21 controls the frequency divider 20 to invert the phase thereby obtaining a normal field index signal. Thus, the result of phase comparison from a phase comparator circuit 19 is inputted to the circuit 21. Plural consecutive fields of result of comparison are stored in the circuit 21. When error information consecutive for plural fields is stored, the circuit 21 inverts the output of the frequency divider 20 to make the field index signal normal.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention relates to a display in which pixels constituted by liquid crystal, plasma, light emitting elements (EL), fluorescent elements, etc. are arranged in a matrix. The present invention relates to a field index device used in a matrix drive display device and the like for displaying images on a screen using an interlace method.

(Prior Art) In recent years, in image display devices such as television receivers and computer displays, flat panels with a matrix arrangement of pixels, such as liquid crystals and plasma, have been used as substitutes for cathode ray tubes. It is becoming more and more used. Because flat panels are thin and compact, their applications are becoming wider, such as in-vehicle multi-vision.

Taking the LCD for television receivers as an example, due to technical and economical reasons, the screen size is 2 to 2 inches, and the number of pixels is 300 to 800 in the horizontal (row) direction and 200 to 200 in the vertical (column) direction.
The mainstream is about 240, and most of them use a non-interlaced display method.

Compared to the interlaced display method, the non-interlaced display method is more efficient in the column direction (in the case of a delta array, in both the matrix and column directions).
However, this is hardly a problem on a liquid crystal panel with a screen size of several inches. However, as screens have recently become larger and more precise, the reduction in resolution has become more noticeable. In this case, in a normal television system, by increasing the number of pixels in the column direction to 440 to 480, interlaced display in the NTSC system becomes possible, and the display section can achieve vertical resolution comparable to that of a cathode ray tube. Become.

However, in this case, in order to perform interlaced display,
It is necessary to distinguish between even and odd fields and drive pixels according to the field.

Figure 7 shows two consecutive NTSC television signals.
It shows the waveforms before and after the vertical synchronization pulse for one field.

The front part of the vertical synchronization pulse in FIG. 7A is a -even field, and the rear part is an odd field. The same figure (7B) is
These are the waveforms before and after the next vertical synchronizing pulse following the vertical synchronizing pulse shown in FIG. 7A, and the relationship between even and odd fields is reversed.

FIG. 8 shows vertical synchronization pulses VD and horizontal synchronization pulses HD obtained by passing the video signals of FIGS. 7A and 7B through a synchronization separation circuit.

The signals (8A) and (8B) in FIG. 8 correspond to the video signals (7A) and (7B) in FIG.

As described above, the phase of the horizontal synchronizing pulse is different from that of the vertical synchronizing pulse in odd-numbered fields and even-numbered fields.

By utilizing this phase difference, it is possible to distinguish between odd and even field signals.

Figure 9A is a field index circuit;
Figure B shows the signal waveforms of each part.

The horizontal synchronizing pulse HD is applied to the data input section of the D-type free-flop circuit 91 and the exclusive OR circuit 92.
one terminal of the D-type flip-flop circuit 9
3 clock input. The clock input section of the D-type flip-flop circuit 91 is supplied with a clock Cp having a sufficiently high frequency. Vertical sync pulse VD
are supplied to the data inputs of D-type flip-flop circuits 93 and 94.

From the exclusive OR circuit 92, FIG.
) pulses are obtained. This pulse is used as a clock for D-type flip-flop circuits 94 and 95, and is also supplied to an AND circuit 97 via an inverter 98. D type flip-flop circuit 94.95
The output of is input to an AND circuit 96, and the output of this AND circuit 96 is input to an AND circuit 97. The output of the AND circuit 97 is the D type flip-flop circuit 99.
clock input. The output of the previous flip-flop circuit 93 is input to the data input section of this flip-flop circuit 99 .

(9C) to (9g) in Fig. 9B are the signal waveforms of each part in the first field, and (9h) to (91) in Fig. 9B
are the signal waveforms of each part in the second field.

The above circuit utilizes the fact that the timing at which a latch pulse for latching the output of the flip-flop circuit 93 is obtained differs between even and odd fields.

The field index signal is obtained at a high level for even fields and at a low level for odd fields.

Another way to obtain the field index signal is
The time from the rise of the vertical synchronization pulse to the rise of the first horizontal synchronization pulse is 45.5 μs and 10.5 μs in even and odd fields, respectively, so there is a method for detecting and determining the difference in time. There is also. Furthermore, if a somewhat complicated circuit configuration is allowed, it is also possible to perform field detection and field discrimination by counting the equalization pulses before and after the vertical synchronization pulse.

However, all of the field discrimination methods described above are based on the premise of field discrimination of standard signals, which have jitter, pseudo-vertical synchronization), playback output signals of video tape recorders (VTRs) in which pulses may be inserted, and field discrimination of standard signals. No field discrimination device has been put into practical use that can accurately discriminate map playback signals from a CDROM in an in-vehicle multi-vision system where there is no difference between signals, or signals whose waveforms have been disturbed by external noise in weak electric field areas. .

For this reason, for example, in a VTR, it is necessary to provide a volume that can vary the insertion timing of the pseudo vertical synchronization pulse, and to allow the user to adjust it to avoid any problems. If these measures are not taken, fields may be displayed in reverse, resulting in vertical image jitter, overwriting of only one field, or even random swapping of even and odd fields. occurs.

FIG. 10 shows a problem on the screen when fields are replaced. FIG. 10(A) shows the state of pixels when video signals are applied reversely to even and odd rows, and FIG. 10(B) shows a normal case.

(Problems to be Solved by the Invention) As described above, in the conventional matrix drive display device, the field index device is a standard NTS
This assumes that a C format signal is input, and it may become unstable if the video signal has a pseudo synchronization signal.
Furthermore, when a non-standard signal is input, there is a drawback that a field discrimination output cannot be obtained reliably, and the non-standard video signal cannot be displayed in an interlaced manner.

Therefore, the present invention is capable of obtaining a stable field discrimination output not only for field discrimination of standard system signals, but also for pseudo signals or still image signals that are not compatible with increment, and also for a wide range of non-standard signals. It is an object of the present invention to provide a field index device capable of obtaining a field discrimination output even for signals of various methods.

[Configuration of the Invention (Means for Solving the Problem) This invention provides a horizontal synchronization or similar horizontal information pulse, a vertical synchronization or similar vertical information pulse,
A clock pulse having a sufficiently higher frequency than the horizontal information pulse is input, and a time information detecting means for detecting time information from a vertical information pulse to a first horizontal information pulse in a certain field; and a clock pulse detected by the time information detecting means. A time information holding means that holds time information compares the time information held by this time information holding means with the time information detected by the time information detection means in the next field, and outputs this result. a magnitude comparison means; a signal generation means for repeatedly outputting a high level and a low level using the vertical information pulse or a pulse at the same period as the vertical information pulse and deriving it as a field index signal;
Phase comparison means compares the phase of the signal generated by the signal generation means and the comparison result output output from the magnitude comparison means, and the phase comparison result information obtained by the phase comparison means is divided into N fields (N> 0) Phase correction means for changing the phase of the signal generated by the signal generation means to output a field index when there is a continuous mismatch.

(Function) With the above means, first, a signal repeating high level and low level is obtained unconditionally from the signal generating means using the vertical information pulse or a pulse having the same period as the vertical information pulse. This signal is phase-compared with the result output of the magnitude comparison means, and if the phase of the signal does not have a predetermined relationship with the comparison result for N fields continuously, the phase that refers to multiple phase comparison result errors is detected. The correction means corrects (inverts) the phase so that it always maintains a constant relationship with the magnitude comparison result output (so that the field judgment is correct). Furthermore, during video signal processing using a non-standard method, the phase comparison result may randomly become normal or error, so the phase of the index signal from the signal generating means is not corrected and is maintained as a stable output.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. A clock with a frequency sufficiently higher than the horizontal frequency is supplied to the input terminal 11, a vertical synchronizing signal 1 or a frequency signal similar to this (hereinafter referred to as vertical information pulse) is supplied to the input terminal 13, and a clock signal having a frequency sufficiently higher than the horizontal frequency is supplied to the input terminal 12. is supplied with a horizontal synchronizing signal or a similar frequency signal (hereinafter referred to as horizontal information pulse).

The vertical information pulse VD is supplied to a reset input terminal of a counter 14 that measures time, and is also supplied to a pulse generator 15. The counter 14 has a vertical information pulse V
When D is input, high-speed clock Ck is counted. on the other hand,
The pulse generator 15 obtains an output synchronized with the horizontal information pulse HD when the vertical information pulse VD is input.
This output becomes high level every time the vertical information pulse VD is input, and becomes low level after a predetermined period.

The output of this pulse generator 15 is D as a latch means.
It is used as a clock for type pre-flop circuits 16 and 17. The output of the previous counter 14 is supplied to the flip-flop circuit 16. As a result, the flip-flop circuit 16 latches the number of clocks (time information) during the period from when the vertical information pulse VD is input to when the first horizontal information pulse HD is input. The output of the flip-flop circuit 16 is the output of the flip-flop circuit 1
7. Therefore, flip-flop circuit 1
Outputs 6 and 17 provide time information before and after one field.

This time information is supplied to the magnitude comparator 18, and the magnitude comparison is performed. This comparator 18 obtains a high level output when the - is larger, and obtains a low level output when the other is larger.

The output indicating the result of this magnitude comparison will always repeat high and low levels for each field if odd and even fields arrive alternately (for example, at 30 Hz).
). This is because, as shown in FIG. 8, the time interval of the first horizontal synchronization pulse that arrives after the vertical synchronization pulse is different between odd and even fields.

The output of the magnitude comparator 18 is supplied to a phase comparator 19. and the phase is compared with the output from the frequency divider 20.

The frequency divider 20 divides the frequency of the output of the pulse generator 15, and repeats high and low levels each time the output of the pulse generator 15 is supplied. The output of this frequency divider 20 is
If the field frequency is 60Hz, it is 30Hz.

Therefore, this circuit can obtain 30 Hz field index information from two systems: the system on the magnitude comparator 18 side and the system on the frequency divider 20 side. Circulator 20
The output of is used.

This is because if the phase comparison result is an error over a plurality of fields, the phase correction circuit 21 controls the frequency divider 20 to invert the phase and make the field index signal normal. Therefore, phase correction circuit 2
1, the phase comparison result from the phase comparator 19 is input. This comparison result is stored in the phase correction circuit 21 for a plurality of consecutive fields. The output (60 Hz) 4 of the pulse generator 15 is used as the clock for storage. When continuous error information is stored over multiple fields, the phase correction circuit 21 converts the frequency divider 20
The field index signal is made normal by inverting the output of the field index signal. Furthermore, if the phase comparison result is unstable, such as randomly outputting high and low levels, the error determination logic in the phase correction circuit 21 will not hold, and the current output phase of the frequency divider 20 will not be established. is output as a field index signal while remaining stable.

FIG. 2 shows the above circuit in more detail.

Components corresponding to the circuit in FIG. 1 are given the same reference numerals as in FIG. The detailed part is the pulse generator 15
, phase comparator 19, frequency divider 20 and phase correction circuit 21
This is the part.

The pulse generator 15 and the frequency divider 20 are each constructed from a flip-flop circuit, and the phase comparator 19 is constructed from an exclusive OR circuit. The phase correction circuit 21 also performs an AND circuit 21g that takes the ANDs of the outputs of the flip-flop circuits 21a to 21f connected in series with the outputs of the flip-flop circuits 21a to 21c, and an AND circuit 21g of the outputs of the flip-flop circuits 21e to 21f. AND circuit 21h1 AND circuit 21
a NAND circuit 21i that obtains negative logic of the outputs of g and 21h;
It consists of an AND circuit 21j that obtains the logical product of the output of the NAND circuit 21i and the output of the pulse generator 15.

The output (high level or low level) of the phase comparator 19 is output in flip-flop circuits 21a to 21f.
Transferred field by field. Here, if the phase comparison result is an error (high level) 6 times in a row (over 6 fields), the output of the NAND circuit 21i will be low level, so at this low level timing, the pulse Even if a pulse is output from the generator 15, the frequency divider 2
No pulse can be given to 0. Therefore, the inversion timing of the output of the frequency divider 20 is shifted by one field, and the phase is corrected.

Figures 3 and 4 show the above field in 6 A timing chart of the index circuit is shown.

(3a) to (3r) in Fig. 3 are the signal waveforms of each part drawn in the circuit of Fig. 2, and this example shows the case where the phase comparison result is an error six times in a row, and the third It shows the progress from the occurrence of an error until the phase is corrected.

The area surrounded by the square dotted line indicates the point in time when the phase was corrected.

FIG. 4 is a timing chart that further shows the counting output of the counter 14 in detail. The figure (4a) shows the vertical information pulse, and the figure (4b) shows the clock Ck.

4c shows each bit output (8 bits) of the counter 14. (4d) in the figure is the horizontal information pulse, and (4e) in the figure is the output of the pulse generator 15. Furthermore, the same figure (
4f) and (4g) show the outputs of the flip-flop circuits 16 and 17 by each bit. The figure (4h) shows the comparison result output.

As mentioned above, according to this field index circuit, normally an index signal is obtained from the frequency divider 2o that repeats high and low levels for each field, while vertical information pulses and horizontal information in the adjacent field 7 are obtained. By comparing each time interval with the pulse, a signal that repeats low and high levels is created. Then, the phases of both signals are compared, and the phase of the frequency divider output is controlled so that the comparison results are constant.

Next, the function of this index circuit when used in a matrix drive display device will be explained.

Generally, in a matrix drive display device, for a certain series of video signal system inputs, the upper and lower parts are omitted,
Only the center part of the screen is displayed. Therefore, in the case of standard format video signals or similar video signals, it is not important to judge whether the signal input for one field is an odd field or an even field, and each horizontal signal information It is important that the vertical relationship between fields is maintained between fields.

Even if information from an even field is mistakenly displayed on an odd line, as long as the vertical relationship is not disrupted, the entire screen is equivalent to being scrolled by one line, and there is no visual problem. These eight conditions are shown in FIG. ODD is an odd numbered row, and EVEN is an even numbered row. Figure 5 (A) is the normal state and Figure 5 (B)
is an image in which the field discrimination is incorrect but the upper limit relationship is maintained, and the entire image is shifted in the vertical direction.

Furthermore, the relative timing relationship between horizontal information pulses and vertical information pulses between multiple systems of video signals may have random differences, but if we focus on one of these signal systems, the horizontal information pulses and vertical information pulses between each field The timing relationship is V
It is about the same as the jitter component of TR and is relatively stable.

FIG. 6A shows the phase position of the horizontal information pulse of the odd field (ODD-FIELD) and the horizontal information pulse of the even field (EVEN-FIELD) with respect to the vertical information pulse VD. In this case, the same figure (C
) images can be obtained in the normal position as shown.

FIG. 2B shows a case where the phase of the vertical information pulse is shifted due to jitter or the like. In this case as well, since the vertical relationship of the lines is maintained by the phase correction, the entire screen is only shifted by one vertical direction, and the image does not become distorted as shown in FIG. 4(D). TOI and TO2 are time differences in odd fields, and TEI and TE2 are time differences in even fields.

Therefore, if the phase of the field index signal obtained from the frequency divider is monitored by comparing the time information of the vertical information pulse and the horizontal information pulse in adjacent fields as in this embodiment, stability can be achieved. It is possible to obtain an index signal with a normal phase. That is, by determining the comparison result and the phase (level) of the inter-sock signal in advance, it is possible to perform phase correction on the index signal of a normal phase.

Next, a case where a non-standard video signal is processed will be described. For example, a video signal with no difference between fields, such as map information on a CD-ROM, will not have an improved vertical resolution even if it is interlaced. Therefore, since we only need to avoid overwriting the same line, we can write any odd number,
All you need to do is obtain the even field determination output. When a video signal with no differences between fields, such as map information on a CD-ROM, is processed,
The output of the comparator will repeat random and meaningless noise level and low level due to the effect of pulse jitter. Therefore, in this case, if the phase correction circuit works effectively and no phase comparison error occurs continuously for, for example, 6 fields, the output phase of the frequency divider will not change and will be stable. You will get the index output.

[Effects of the Invention] As explained above, according to the present invention, it is possible to perform field determination of not only standard format signals, but also a wide range of non-standard format signals such as pseudo signals or still image signals that are not compatible with interlacing. It is also possible to obtain a field-discriminated output even for 3D images and to enable interlaced display.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the circuit of FIG. 1 in more detail, and FIGS. 31 and 4 show signal waveforms of each part of the circuit of FIG. 2. 5 is an explanatory diagram showing an example of an image shown to explain an example of the operation of the circuit of this invention. FIG. 6 is also a synchronous pulse timing chart shown to explain an example of operation of the circuit of this invention. FIG. 7 is an explanatory diagram of a television signal, FIG. 8 is an explanatory diagram of a synchronization signal, FIG. 9A is an explanatory diagram of a conventional field index circuit, and FIG. 9B is an explanatory diagram showing examples of images.
This figure is a timing chart shown to explain the operation of the circuit shown in FIG. 9A, and FIG. 10 is an explanatory diagram of a screen caused by an error in field discrimination. 14...Counter, 15...Pulse generator, 16.
17... Flip-flop circuit, 18... Size comparator, 19... Phase comparator, 20... Frequency divider, 21...
...Phase correction circuit.

Claims (1)

[Claims] A horizontal synchronization or similar horizontal information pulse, a vertical synchronization or similar vertical information pulse, and a clock pulse having a sufficiently higher frequency than the horizontal information pulse are input, and the vertical information pulse in a certain field is time information detection means for detecting time information from to the first horizontal information pulse; time information holding means for holding time information detected by this time information detection means; and time information held by this time information holding means. and time information detected by the time information detection means in the next field, and outputs the result; a signal generating means for repeatedly outputting the signal and deriving it as a field index signal; a phase comparing means for comparing the phase of the signal generated by the signal generating means with the comparison result output output from the magnitude comparing means; The phase comparison result information obtained by the comparison means is N
1. A field index device comprising: phase correction means for changing the phase of a signal generated by the signal generation means to output a field index when fields (N>0) are continuously inconsistent.