JPH0381881A - Parallel pipeline image processing system - Google Patents

Abstract

PURPOSE:To attain the rapid processing of an image by absorbing a speed difference between the clock of an I/O image and a clock to be processed by the internal by means of I/O image buffers in an image processor. CONSTITUTION:The input image of one frame is divided into units each of which consists of several lines, one image processor is allocated to the units and two I/O image buffers 26, 29 are connected to the image processor. During the writing of the picture elements of an allocated area in one input image buffer, the image of the just preceding frame are sent from the other input image buffer to an arithmetic part 27 based upon a control signal synchronized with an internal clock phi. During the writing of a computed result in one output image buffer, the computed result of the just preceding frame is read out and outputted from the other output image buffer.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art and Problems to be Solved by the Invention Means for Solving the Problems Action Examples Effects of the Invention [Summary] Like a high-resolution image Regarding an image processing method that processes moving images with a large number of pixels in one frame at the video rate, we have developed a method to process moving images with a large number of pixels in one frame at video rate without significantly increasing the amount of hardware. The purpose is to connect multiple image processing processors in parallel, and to each image processing processor, divide one frame of image into units of several lines, for example, so that each area overlaps, and input it. , each image processing processor is provided with an input/output interface having a plurality of image buffers, and when the input interface is writing image data into one image buffer at the input image clock (Φ), In the other image buffer,
The image data of the previous frame is sent to the arithmetic unit at the pipeline pitch of the internal clock (φ) of the image processing processor, and the output interface sends the image data to one image buffer.
When the above calculation result is written using the internal clock (φ) of the image processing processor, the calculation result of the previous frame is outputted using the output image clock (Φ〉), and each image processing processor writes the above calculation result every few lines. The images are configured to be pipeline processed and output in parallel.

[Industrial application field]

The present invention relates to an image processing method for processing a moving image with a large number of pixels in one frame, such as a high-resolution image, at a video rate, that is, at the speed of an input image clock Φ.

With the recent advances in computer technology, there is a demand for image processing devices that process images obtained from television cameras at video rates in the fields of factoriotomesis (FA) and television (TV). .

In particular, in microfabrication technology in the field of factory automation (FA) and high-resolution technology represented by high-definition in the television (TV) field, there is a trend toward an increase in the number of pixels per frame input from a TV camera. Therefore, there is a need for an image processing device that can process images with a large number of pixels at a video rate.

[Prior art and problems to be solved by the invention] FIG. 4 is a diagram illustrating a conventional parallel image processing system.

Conventional image processing devices use pipeline methods,
A method for processing images at high speed using a parallel processing method has been proposed.

Pipeline image processing devices are designed to speed up image processing by converting basic calculations of image processing into hardware in units of modules, operating each processing module with a basic clock, and connecting them with a pipeline.

On the other hand, the parallel image processing method achieves high speed by accessing image data in parallel and processing them in parallel.

For example, when performing similar processing on each pixel, as shown in this figure, each processor element is connected in a grid pattern, one processor element is assigned to each pixel, and parallel operation is performed. The configuration of a fully parallel processor is
Most importantly, you can expect faster speeds.

However, in the pipeline method described above, the pipeline pitch, which determines the speed of image processing, is most affected by the speed of the processing module that requires a long time for image processing. Because the number of pixels is large, the pipeline pitch must be made faster,
Current device technology is currently at its best at handling current image sizes.

As described above, the pipeline method has a problem in that even if the clock of the pipeline pitch is simply made faster, when the number of pixels increases, it is not possible to process all the pixels in time.

On the other hand, the above-described parallel image processing method has the problem that not only the number of image processing processors (processor elements) becomes enormous, but also that inputting and outputting between the image processor and external data takes a large amount of time.

For example, an image input from the outside must be sequentially transferred and distributed to the image processing processor corresponding to each pixel, and when outputting, the processing results of the image processing processor corresponding to each pixel are sequentially transferred to the image processing processor corresponding to each pixel. This is because it is necessary to output the data to the outside by transferring it.

In general, images from external input/output devices such as external memory, television cameras, and monitors basically have a so-called one-dimensional data structure, and if parallel access to the external data is not possible, it takes time to input and output the data. time is required, response response is reduced, and man-machine interface (MHI)
) became worse.

In view of the above-mentioned drawbacks of the conventional art, the present invention is capable of processing moving images with a large number of pixels in one frame, such as high-resolution images, at video rates without significantly increasing the amount of hardware. The purpose of this invention is to provide an image processing method that can process video images.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle configuration of the present invention.

The above problems are solved by an image processing method configured as follows.

In a digital image processing device that processes moving images, a plurality of image processing processors 28 to 2z are connected in parallel,
Each image processing processor 2a to 2z is assigned and inputted with one frame of image divided into several lines, for example, so that each area overlaps, and each image processing processor 2a to 2z is , an input/output interface with a plurality of image buffers, and a timing signal (fraa+e, aline) that controls the human output interface 26°29 in synchronization with the human image clock Φ or internal clock φ. Tie control signal generation circuits 21 to 24 are provided, and when image data is being written into one image buffer using the control signal synchronized with the clock Φ of the human image, the input interface is configured to generate tie control signal generation circuits 21 to 24. Then, the image data of one frame before is sent to the calculation unit using the control signal synchronized with the internal clock φ of the image processing processors 28 to 2z,
In the output interface, when writing the above calculation result to one image buffer using a control signal synchronized with the internal clock φ of the image processing processors 2a to 2z, the calculation result of one frame before is synchronized with the clock Φ of the output image. each image processing processor 2.
8 to 2z are configured to perform pipeline processing on the images every several lines in parallel and output them.

[Operation] In other words, in the present invention, -dimensional image data such as images from a television camera is processed in a practical manner by focusing on the suitability of the pipeline method and the high speed of parallel processing. Parallelism refers to the range of calculation speed of each image processing processor connected in parallel (for example, 512 pixels, 12
It is intended to produce m-element television images.

That is, an image of one frame is divided into several lines, one image processing processor is assigned to the divided area, and each image processing processor processes the assigned image at the pipeline pitch of the internal clock. Pipeline processing is performed only on the pixels that fill the area.

The internal clock φ is fast enough to perform various image processing even with current pixel processing processors, and is currently fast enough to process, for example, 512 pixels×512 pixels. Therefore, in the above-mentioned high-definition image, if one line has 1024 pixels, it is possible to have up to 256 lines, which means that it can be processed by, for example, two image processing processors.

If the degree of parallelism is increased, the processing speed of each image processing processor may be correspondingly slower.

In order to convert the input image to that speed, the present invention provides, for example, a human output interface in each image processing processor with two image buffers, where one image buffer is connected to the input image clock. When writing with control signals (*PRAMIE, *LINE) synchronized with Φ, the other image buffer writes the image data of one frame before with control signals (this frai+e, *l 1ne) synchronized with the internal clock φ. The configuration is such that the data is sent to the calculation unit at a pipeline pitch of .

Similarly, when the output interface is writing the calculation result to one image buffer using a control signal synchronized with the internal clock φ, the other image buffer writes the calculation result of the previous frame in synchronization with the output image clock φ. The configuration is configured so that the control signal is output using the specified control signal.

Since it operates in this way, the input/output image clock Φ in the input/output image buffer in the image processing processor,
By absorbing the speed difference with the internally processed clock φ, even with current device technology image processing processors, it is possible to increase the number of pixels in one high-resolution frame by simply increasing the number of image processing processors within a practical range. It also has the effect of allowing high-speed processing of images.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram showing the principle configuration of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention, where (al, a2) shows an example of the overall configuration, and (bl) An example of the configuration of the internal line clock generation circuit is shown, (b2) is an example of the configuration of the internal frame enable generation circuit, <b3> is an example of the configuration of the internal line enable generation circuit, and (b4) is the input buffer write enable. An example of the configuration of the generation circuit is shown, (b5
) shows a configuration example of the input address control circuit, (b6) shows a configuration example of the input buffer circuit, (h7) shows a configuration example of the output address control circuit, and (b8) shows a configuration example of the output buffer circuit. FIG. 3 shows an operation time chart of image processing according to the present invention, in which one frame of input image is divided into units of several lines 7, and one image processing processor is applied to each divided area. 2a~ is allocated, and each image processing processor 2a~ is provided with two input/output image buffers, and the pixels of the allocated area are transferred to an internal clock generated based on the internal clock φ of the image processing processor 28~. Based on the line clock (*1ineCLK), internal frame enable (main frame), and internal line enable (*1ine), one input image buffer 261, for example, receives an input image using a control signal synchronized with the input image clock Φ. While writing, the image data of one frame before is sent from the other input image buffer 262 to the calculation unit (IPU) 27 using a control signal synchronized with the internal clock φ, and the one frame, for example, the output image buffer 291 When the calculation result of the calculation unit (rPU) 27 is being written to the output image buffer 292 using a control signal synchronized with the internal clock φ, the calculation result of the previous frame from the other output image buffer 292 is written in synchronization with the output image clock φ. A means for reading and outputting a control signal is a necessary means for carrying out the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, FIG. 2 will be described with reference to the principle diagram of FIG. 1.

The parallel pipeline image processing method of the present invention will be explained with reference to FIG.

First, the host computer 1 connects each image processing processor 28 to
Parameters (separation area settings, internal line clock (this 1ine-CLK), internal frame enable (*frame), parameters necessary for generating the internal line enable (this 1ine)) were set in the various registers and memory in the memory. After that, each image processing processor 28 is activated.

Images from a television (TV) camera are input manually to the image processing processors 28 to 28 shown in the principle diagram of FIG. Execute and output the result.

The image reconstruction circuit 3 reconstructs the images output from each of the image processing processors 2a to the original one-frame image.

First, the overall general operation will be explained based on the block configuration of the image processing processor 2a shown in FIG. 2 (al, a2).

The internal line clock generation circuit 21 generates an internal image synchronization signal (i.e.,
The internal line clock (this 1ine-CLK) for generating the above-mentioned internal frame enable (main fraw + eL internal line enable (this 1ine)), that is, the number of pixels processed in one line by the image processing processor 2a (one line An internal line clock (with an internal line enable period corresponding to the number of pixels x internal clock φ)
1ine-CLK).

and the next internal frame enable generation circuit 23.

The internal line enable generation circuit 24 generates a synchronization signal (internal frame enable (*frame) + internal line enable (main)) of the images processed by each image processing processor 2a based on the internal line clock (*1ine-CLK). 1ine)).

The input buffer write enable generation circuit 22 and the input address control circuit 25 transfer the image data held by each image processing processor 2a to the input buffer circuit 26.
buffer write enable signal (manual ride enable) (IME) and buffer write address signal (input ride address') (IWAD
R) is generated.

The human-powered buffer circuit 26 has two human-powered image buffers 2.
For example, when one input image buffer 261 is capturing an input image using a control signal synchronized with the human clock Φ, the other input image buffer 262 is configured with a pipeline clock (internal clock). ) Image processing unit (IPU) with a control signal synchronized with φ
27, it operates to flow the image data of one frame before.

The image processing unit (IPU) 27 is, for example, a programmable image processing circuit, and is configured with a so-called digital signal processor (DSP) or the like that can perform various image processing by changing the firmware.

The results processed by the image processing unit (IPU) 27 are as follows:
The signal (output read address (ORADH)) of the output address control circuit 28 is sent to the output buffer circuit 29.
written based on.

The output buffer circuit 29 also includes the above-mentioned manual buffer circuit 26.
Similarly, it is composed of two output image buffers 291 and 292, one of which is, for example, output image buffer 29.
1 takes in the processed image from the image processing calculation unit 27 using a control signal synchronized with the internal clock φ, the other output image buffer 292 takes in the processed image from the image processing calculation unit 27 using a control signal synchronized with the output clock φ from the output address control circuit 28. Based on the signal, it operates to output the processing result of one frame before.

The detailed configuration and operation of each block constituting the image processing processor 28 will be described below with reference to figures (bl) to (b8).

In this embodiment, for convenience of explanation, one image processing processor processes a 1024 pixel/line image consisting of 2 pixels/line, 8 line pixels x 1024 pixels, for example.
6.32. - It goes without saying that this axis can be extended to the case where it is divided line by line and processed by each image processing processor. In addition, the above dividing line is created by, for example, considering the use of a logical filter etc. in the image processing.
It goes without saying that it is also possible to overlap and divide one line.

First, FIG.
The image synchronization signal (referred to as input image clock Φ) of the video image (image of 2 pixels/line, 8 lines) inputted via the frame synchronization signal (*FR
AME), a latch (FF) 210, an AND circuit (AND) 211, and an inversion circuit (INV) 2121
? , l synchronized with the frame synchronization signal (*FRAME)
Generates a pulse clear signal and sends a counter (Count
er) 213 is cleared (CLEAR).

As mentioned above, the host computer 1 inputs the internal line clock (main Pixel enable) period setting register 214 in advance.
LK) period (for example, 3 pixels) is set, and the pixel enable active (*Pixel enab
In the period setting register 215,
An active period for processing the two pixels/line (for example, a period for the two pixels) is set.

As mentioned above, in this image processing processor, out of the above-mentioned 2 pixels/line, 8-line image, it is only necessary to process the divided 2-line image, that is, 4 pixels, during one frame period. The internal processing speed of the image processing processor 2a is 4Φ=φ with respect to the clock Φ of the input image.
Based on the internal clock φ, an internal line clock (*1in.
e-CLK) is generated as follows. (Refer to the operation time chart "Φ" and "φ" in FIG. 3) The counter 213 counts the internal clock φ, and the pixel enable (this Pixel
The internal line clock (*1ine-CLK) period (for example, 3 pixels) is set in the pixel enable active (*Pixl enable active) period setting register 214, and the above two Since an active period for processing a pixel/line (for example, a period for two pixels) is set, the value (^) of the counter 213 in the comparator 217 is set as the pixel enable active (*Pixel e
During a period smaller than the setting value (B) of the period setting register 215 (=2) (that is, the period of 0, "1"), the value of the counter 213 (A) at the active level. When it reaches 2 degrees, it outputs an internal line clock (1ine-CLK) that becomes inactive.

On the other hand, in the comparator 216, the period in which the value (B) of the counter 213 is smaller than the setting value (A) (=3) of the pixel enable period setting register 214 is When the set value (A) becomes equal to the value (B) of the counter 213, a signal is generated to clear the counter 213.
In the internal line clock generation circuit 21, a counter 213 converts the internal clock φ into “
It is active while counting O", 'l", °
2, an internal line clock (*1ine-CL) that repeatedly becomes inactive is output.

The image processing processors 2a to 2a perform image processing, writing to the input/output image buffer, and reading from the input/output image buffer based on this internal line clock (ml 1ne-CLK).

Next, the detailed operation of the internal frame enable generation circuit 23 will be explained with reference to FIG. 2 (b2>).

The circuit configuration consists of the above-mentioned internal line clock generation circuit and the counting clock at the counter 233, which is the internal clock φ [phase] internal line clock (this l 1ne).
-CLK).

From the host computer 1, the frame enable active period (for example, 2 line clock (*1ine-C
LK) = 2) is frame enable active (*
Fravae enable active) is set in the frame enable period setting register 235, and the frame enable period (
For example, 3 line clock (1ine-CLK)
) is the frame enable (this frame enable
) By being set in the period setting register 234, it operates in the same way as the internal line clock generation circuit 21,
An internal frame enable shown as "r*fraa+e" in the operation time chart of FIG. 3 is generated.

Similarly, in the internal line enable control circuit 24 shown in FIG. (*1ine en
r*1ine J in the operation time chart of FIG. 3 by setting in the period setting register 244
Generates the internal line enable shown in .

In this way, the timing for controlling the image processing in the image processing processor 2a~ (in other words, in this embodiment, the internal frame (*
fraseL internal line (1ine)) is generated.

Next, details of the input buffer line enable generation circuit 22 shown in FIG. 2(b4) will be explained.

The basic configuration is the internal line clock generation circuit 2 described above.
Same as 1.

From the host computer 1, in advance, the image processing processor 2
The area of the image that a~ has is the starting line (line
) configuration register 224. And the end line (line)
By setting in the setting register 225, the TV (
TV) Line synchronization signal of the image input from Gamera etc.
*LINI is counted by a counter 223, and the line synchronization signal (*
Input line signal (this ILINE) that energizes the LINE
Output.

Based on this input line signal (*ILINB), (b
5) In the input address control circuit 25 shown in the figure, a manual ride address (IWADR), an input ride enable (IWE), and an input read address (i
radr).

First, in (a) of figure (b5), the frame synchronization signal of the human image (main PRAME) and the Wi image synchronization signal (Φ)
of the clear signal generated by the counter (
Counter) 251 is cleared, and thereafter, the receivers of the image processing processors 2a~ perform processing by counting the input line signal (this ILINE) that indicates the line synchronization signal (*LINE) of the input image of the area it has. Outputs the row address (row-adr) of the desired image.

Similarly, the above input line signal ($ILIN) is input.

The counter 252 is cleared by the clear signal (2) generated by the image synchronization signal (Φ), and thereafter, the receivers of the image processing processor 28 ~ count the image synchronization signal (Φ) of the input image of the area it has. By doing this, the column address of the image to be processed (column-a
dr) is output.

The row address (row-adr) + column address (colua+n-adr) output above is the selector (Se
At 253, the input ride address (IWADR) for the input image buffer 261 is generated by switching between active and inactive periods of the image synchronization signal (Φ) of the human image.

Further, the input line signal (umbrella ILINE), which is energized only when the input image is in the area that the image processing processor 28~ has, and the image synchronization signal (Φ) are ANDed, The input image buffer 261 or 262
The write enable (IME) is generated for the write enable (IME).

The input ride address (IWADH) and write enable (TWII) are signals synchronized with the image synchronization signal (input image clock Φ) of the human-powered image, so writing to the input image buffer 261 is performed using the input image. This will be done using the clock Φ.

(b5) Figure (b) shows that the image written in the input image buffer 261 is sent to the image processing unit (IPU) 27.
Generates an input read address (iradr) to be sent in synchronization with the internal clock φ.

That is, based on the internal frame signal (*frame) generated by the internal frame enable generation circuit 23 and the internal line signal (1ine) generated by the internal line enable generation circuit 24, the same logic as above is used. , input read address (irad) synchronized with internal clock φ
r).

Since this input read address (iradr) is address information synchronized with the internal clock φ, the image written to the input image buffer 261 in synchronization with the image synchronization output Φ of the input image is transferred to the image processing unit (IPU 27). The data is read out in synchronization with an internal clock φ that is compatible with the processing speed of the image processing unit (IPU) 27, and can be sent to the image processing unit (IPU) 27.

(b6) is a diagram showing details of the input buffer circuit 26.

In the present invention, the input image buffer includes two buffer memories (BUFI Memory, BUF2 Mem
ory) 261 and 262.

These two human-powered image buffers (BUFI Memor
y, BUF2 Memory) 261.262 is 1 due to the least significant bit signal ■ of the counter 260 that counts the internal frame signal (*frame) and the input ride enable (IME).
The input image buffer (BtlP1?1esory, BIJF
2 Memory) 261+262 is the address information given to Selector 263.
In H.264, the input ride address (IWADR) and input read address (iradr) are switched for each internal frame (BUPI Memory), so one input image buffer y (BUPI Memory) 2
61 is loading the input image (DATA) into the address area specified by the input ride address (IWADR) based on the input ride enable (IME) synchronized with the input image clock Φ, the other input image In the buffer y (BUF2 Memory) 262, the input ride enable (IME) is not activated, so a read operation is performed, and the image is read out based on the input read address (iradr) synchronized with the internal clock φ, and image processing is performed. The processing unit (IPU) operates to send out the input image written one frame before to the processing unit (IPU) 27.

(b7) The figure shows the details of the output address control circuit 28, and the output image buffer (BUF3 Mem
ory, BUF4 Memory) Address information (ORADR, owadr) and write enable (owe) for 29L292 are generated.

That is, the output image buffer y (BUF3 Memory
, BUF4Memory) 291, 292 are the above-mentioned human image buffers (BKo I Memory, BUF2M
Since it is necessary to operate in synchronization with 261 and 262 (emory), the input image buffer (BUFI Mem) generated by the input address control circuit 25.

ry, BUP2 Memory) 261.262, the input ride address (IWADR), input read address (i radr), and manual ride enable (IWE) are synchronized with the internal clock φ of the image processing processor 28 to the necessary clock. The address information (ORADR, owadr) and write enable (owe) are generated by delaying the address information (ORADR, owadr).

First, the output image buffer y (BUP3 Memory
, BIIF4Memory) 291.292, the write address (owadr) for the input image buffer y is synchronized with the internal write enable (this 1ine).
(BUFI Memory, BUF2 Memory)
A manual read address (iradr) that defines the read timing from H.261.262 is generated by delaying the processing time (an integral multiple of the internal clock φ) in the image processing calculation unit 7.

With similar delay timing, the output ride enable (ow
e) can also be generated.

Output image buffer (BUP3 Memory, BUF
The output read address (ORADH) for 4 Memory) 291.292 is the input image buffer y (BU
FI Memory, BIJF2 Memory) 2
Input ride address (IWADH) for 61.262
) within the active period of the internal frame (mfra■e), the output image buffer y (BUF3 ?lemor
ytB [IF4 Memory) 291. Timing when the contents of 292 (processing results in the image processing unit (IPU) 27) can be read (write to input image buffer → read pass image processing → write pass read to output image buffer) It can be generated by delaying it so that

(b8) The figure shows details of the output buffer circuit 29, in which the two output image buffers (BIIF3 Mem
.

ry, BUF4 Memory) 291, 292, and basically consists of the aforementioned manual buffer circuit 2.
Since it has the same configuration as 6, its operation is basically the same.

That is, the internal frame of the image processing processor 28 (
*1rase), one output image buffer y
(BUF3 Memory) 291 transfers the processed image (data) from the image processing unit (IPU) 27 to the output ride address (owa) synchronized with the internal clock φ.
dr) and other output image buffer y (BUF4 Mem
ory) 292 is an output read address (ORADR) synchronized with the human image clock Φ, which operates to output the processing result of one frame before.

FIG. 3 shows an image processing processor 2 operating as described above.
The operation time chart from 8 to 8 is shown.

In this figure, "Φ" is an image synchronization signal (input clock) of an input image, and "φ" is an internal clock generated by the image processing processor 2a.

In addition, rKo RAME J is the frame synchronization signal of the input image, r*LINE J is the line synchronization signal of the input image, and r DATA J is the image synchronization signal (Φ
) and input image data synchronized with the line synchronization signal (*LIllH).

As mentioned above, in this example, two images/line,
Since an input image consisting of 8 lines is taken as an example, the input image is at the timing shown in the figure.

Then, "fframe" is the main image processing processor 2a.
The above-mentioned internal frame enable generated within is shown, and r lines 1ine J show the internal line enable.

As mentioned above, in this embodiment, in one internal frame period,
Since only two lines of images are processed, only two (2 internal lines) of the internal line enable (this 1ine) are generated during the internal frame enable (this frame) period.

Next, BUF 1.2 is the input image buffer y (BUF
I Mem.

ry, BUF2 Memory) 261.262, and BUF 3°4 is the output image buffer y (BUF2 Memory) 261.262.
F3 Memory + BUP4 Memory) 29
1.292, and the numbers (°0" to °3") in the time chart indicate pixel numbers, and each subscript ('nZ'n-IZ"n-2") indicates the frame number. It shows.

In this figure, one input image buffer (BUFI
Memory) 261 contains the pixel (
°0°~°3゛) is being written in synchronization with the input image clock Φ, the other input image buffer (BLIF2
From 262, the previous frame (
n-1) pixels (0゛~°3゛〉) are internal line enable (1 inch
It is read out at the timing of e), and the image processing calculation unit (IP
U) It is shown that it is being sent to 27.

Similarly, one output image buffer (BUF3 Me
291, the image processing unit (IPU)
Pixel of the previous frame (n-2) at 27 (°0”
~ “3゛)” is being fetched by the control signal (owadr above) synchronized with the internal clock φ, the other output image buffer y (BUF4 Memory) 2, the previous frame (n -3) pixel (0”~
3”) is output in synchronization with the clock Φ of the input image.

By controlling in this way, an image consisting of 8 lines with 2 pixels/line can be divided into every 2 lines, and each area can be assigned to four image processing processors 28 to be processed in parallel. It is sufficient for each of the image processing processors 2a to perform pipeline processing on an image of a divided area of 2 lines and 4 pixels, and the image processing processors 2a to 2a can process 2 lines and 4 pixels in one frame time. Four units can process 8-line, 166-pixel images at high speed.

As described above, the present invention can process moving images with a large number of pixels in one frame, such as high-resolution images, at the video rate by dividing one frame of human-powered images into units of several lines.
One image processing processor 2a~ is assigned to each divided area, and each image processing processor 28~ has two
An internal line clock (*1i
neCLK), internal frame enable (this frai
ee) Based on the internal line enable (this 1ine), when an input image is being written to one input image buffer using a control signal synchronized with the input image clock Φ, one frame is written from the other input image buffer. The previous image data is sent to the calculation unit (IPU) 27 using a control signal synchronized with the internal clock φ, and the calculation result in the calculation unit (IPU) 27 is sent to one output image buffer in synchronization with the internal clock φ. The feature is that when writing using a control signal, the calculation result of one frame before is read out from the other output image buffer using a control signal synchronized with the clock Φ of the output image and outputted.

〔Effect of the invention〕

As described above in detail, the parallel pipeline image processing method of the present invention connects a plurality of image processing processors in parallel, and each image processing processor receives an image of one frame in units of several lines.

In addition, for example, each image processing processor is provided with an input/output interface having a plurality of image buffers, for example, two image buffers, and the input/output interface is configured such that each image processing processor is provided with an input/output interface having a plurality of image buffers, for example, two image buffers. Now, when image data is written into one image buffer using a control signal synchronized with the clock Φ of the input image, in the other image buffer, the image data of one frame before is written in synchronization with the internal clock φ of the image processing processor. At the output interface, when the above calculation result is written to one image buffer using a control signal synchronized with the internal clock φ of the image processing processor, The calculation result is output as a control signal synchronized with the output image clock Φ, and each image processing processor processes the image every few lines.
Since it is designed to perform pipeline processing and output in parallel, the input/output image buffer in the image processing processor absorbs the speed difference between the input/output image clock Φ and the internally processed clock φ. Therefore, even with image processing processors of current device technology, it is possible to process high-resolution images with a large number of pixels in one frame at high speed simply by increasing the number of image processing processors within a practical range.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention. FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is an operation time chart of image processing according to the present invention. FIG. 4 is a diagram explaining a conventional parallel image processing method. It is. In the drawing, 1 is the host computer. 2a to 2z are image processing processors. 21 is an internal line clock generation circuit. 22 is an input buffer write enable generation circuit. 23 is an internal frame enable generation circuit. 24 is an internal line enable generation circuit. 25 is an input address control circuit. 26 is an input buffer circuit. 27 is an image processing unit (IPU) or a calculation unit (IP
U). 28 is an output address control circuit. 29 is an output buffer circuit. Φ is an image synchronization signal or input image clock. Or the output image clock. φ is the internal clock. *FRAM[! is the frame synchronization signal of the input image.纺INIE is the input image line synchronization signal. ml 1ne-CLK is the internal line clock. DATA is input image data or input image. *fravae is internal frame enable. 1ine has internal line enable. LINE is the input line signal. IWADR is a human powered ride address. ■-E is human powered ride enable. 1radr is the input read address. 0RADR is the output read address. owadr is the output ride address. owe is output ride enable. 3 is an image reconstruction circuit. ■,■ are clear signals. are shown respectively. β γ δ (al) Diagram showing an embodiment of the present invention (Part 1)

Claims (1)

[Claims] In a digital image processing device that processes moving images, a plurality of image processing processors (2a to 2z) are connected in parallel, and each image processing processor (2a to 2z) has a
One frame of image divided into several lines is allocated and input, and each image processing processor (2a to 2z) has an input/output interface (26) with multiple image buffers.
, 29) and the input/output interface () in synchronization with the input image clock (Φ) or the internal clock (Φ).
A timing signal generation circuit (21 to 24) is provided to generate a timing signal to control the input interface (26, 29), and based on the timing signal output from the timing signal generation circuit (21 to 24), the input interface (26, 29) ), while image data is being written into one image buffer using the above control signal synchronized with the clock (Φ) of the input image, the other image buffer is writing the image data of the previous frame into the image processing processor (2a). The control signal synchronized with the internal clock (φ) of the image processing processor (2a to 2z) is sent to the arithmetic unit (27), and the output interface (29) inputs the internal clock (φ) of the image processing processor (2a to 2z) to one of the image buffers. When the above calculation result is written using the above control signal synchronized with φ), the calculation result of one frame before is outputted from the other image buffer using the above control signal synchronized with the output image clock (Φ), and each Image processing processor (
2a to 2z), the parallel pipeline image processing method is characterized in that the images of every several lines are subjected to pipeline processing in parallel and outputted.