JPH0356024B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a staff synchronization system for a multiplex converter used in a time division multiplex digital communication system.

Conventional multiplex conversion devices of this type usually employ staff synchronization using positive stability at the front stage in order to multiplex convert a plurality of low-order group signals that are asynchronous to each other into high-order group signals on the transmitting side. method is adopted.
This method has the advantage of extremely high system flexibility and easy device design. A staff synchronizer using this type of system generally includes a transmitting buffer memory, a first frequency divider for generating a clock for writing input data to the transmitting buffer memory, and a first frequency divider for reading data written in the transmitting buffer memory. The main elements are a second frequency divider that generates a clock, and a phase comparator that compares the phase difference between the output pulse of the first frequency divider and the output pulse of the second frequency divider. There is.
Here, the clock speed of the second frequency divider is chosen to be somewhat higher than the clock speed of the first frequency divider. During pulse stuffing operation, the phases of the write instruction pulse and the read instruction pulse to the transmission buffer memory are compared by a phase comparator, and when the phase difference becomes smaller than a certain threshold Λ, a stuffing request is issued. The stuffing is performed after sending the stuff control bit.

However, the above-described conventional method has the disadvantage that a considerable amount of sampling jitter occurs. This jitter component includes extremely low frequency components, so even if the jitter is suppressed using a phase control loop (PLL) on the receiving side, it cannot be completely removed, and the output This resulted in a reduction in signal quality. The occurrence of this sampling jitter is caused by the conventional staff synchronizer having a capacity M of the transmission buffer memory, as will be described in detail later.
The inventor of the present application has recently reasoned that this is due to the fact that the phase comparison is performed using one of the output pulses as a representative after the frequency has been divided into a ratio equal to (a multiple of 2). .

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a staff synchronization system for a multiplex converter that can eliminate the above-mentioned drawbacks and prevent sampling jitter from occurring during stuffing.

According to the invention, a transmission buffer memory means;
a first frequency dividing means for generating a clock for writing data into the transmitting buffer memory means; a second frequency dividing means for generating a clock for reading data written in the transmitting buffer memory means;
The staff of the multiplex converter includes phase comparison means for comparing the phases of the output pulses of the first frequency division means and the output pulses of the second frequency division means, and the staff is controlled by the output of the phase comparison means. In the synchronous method, the capacity of the transmission buffer memory is set to a prime value such as 5 bits, 7 bits, 11 bits, etc., and the frequency division ratio of each of the first and second frequency dividing means is set to the capacity of the transmission buffer memory. A staff synchronization method is obtained, which is characterized in that the staff synchronization method is selected to be equal to the prime value set for the target.

Next, in order to facilitate comparison with the present invention, a staff synchronizer in a conventional multiplex converter will be explained with reference to the block diagram of FIG. In the figure, 1 is a buffer memory on the transmitting side, 2 is a frequency divider that generates a clock for writing PCM input data to buffer memory 1, and 3 is a frequency divider that generates a clock for reading data written to buffer memory 1. 4 is a phase comparator that compares the phase of the output pulse of frequency divider 2 and the output pulse of frequency divider 3; 5 is a bipolar to unipolar waveform conversion circuit; 6 is a staff control circuit; 7
is an inhibit circuit, and 8 is a flip-flop.

To explain the operation of this device, first, the input PCM signal a is converted into a unipolar signal b by the waveform conversion circuit 5, which is controlled by the write clock pulse of the frequency divider 2, and has a capacity of, for example, 8 bits. Written to buffer memory 1. The information written in this buffer memory 1 is read by the read clock pulses of the frequency divider 3. Since the clock speed of divider 3 is chosen to be somewhat higher than that of divider 2, even if the input PCM signal being written is not synchronized with the clock pulses of the device, the PCM Once the signal enters the buffer memory 1, it is read out again in full synchronization with the timing system of the device. The phase difference between the output pulses of frequency divider 2 and frequency divider 3, caused by the difference in clock speeds, becomes small to the point where the information once read can be read again. The phase comparator 4 is supplied with output pulses whose frequencies have been divided by 8 from the frequency divider 2 and the frequency divider 3, respectively, and the phase differences between the output pulses are compared. When the phase of the output pulse of the frequency divider 3 catches up with the phase of the frequency divider 2, a stuffing demand is generated by the staff control circuit 6, and the output pulse of the frequency divider 3 is inhibited for one bit. This can prevent information that has already been read from being read again. More specifically, when stuffing is requested by the SD pulse of the output of the phase comparator 4, the stuffing control pulse of the frequency divider 3 is generated in the stuffing circuit of the multiplexing (MPX) unit. However, the staff command from the staff control circuit 6 is not immediately sent out in response to an SD pulse request. This means that the read-inhibited pulse position is
This is because it is predetermined for the signal. A stuff pulse is then generated in a time slot called a "variable slot." When the inhibition of one bit to the frequency divider 3 is controlled by the inhibition circuit 7, the reading of one bit is inhibited and a stuff pulse with no information is applied to the variable slot whose reading is inhibited.

Furthermore, regarding the operation when the transmitting side buffer memory 1 is accessed by the frequency dividers 2 and 3, the detailed block diagram in FIG. 1a and FIG.
This will be explained in detail with reference to the time chart shown in the figure. Generally, in order to multiplex a certain number of low-order group signals into a high-order group signal using the staff synchronization method, a transmission buffer memory is required to temporarily store input data for each low-order group signal. This transmission buffer memory is equipped with serial-to-parallel conversion and parallel-to-serial conversion functions. In the example of FIG. 1a, the transmission buffer memory 1 is composed of an 8-stage buffer, and therefore the frequency divider has a division ratio of 8 (8 times the clock period).
Indicates when set to . In the figure, a frequency divider 2 is driven by a write clock pulse _C1 extracted from input data, and write clock pulses W1 to W8 are generated. According to this write clock pulse _C1 , the input PCM signal is
They are sequentially written into the transmission buffer memory of MEM8 and temporarily stored. On the other hand, the frequency divider 3 divides the read clock pulse _C2 by 8, and R1 to R8
Generates 8-phase readout clock pulses up to 8 phases.
These clock pulses are connected to gate G1, respectively.
~G8, reads data stored in MEM1~MEM8 in order, and outputs it as output data. As mentioned above, the speed of the read clock pulse is set slightly higher than the frequency of the write clock pulse.

Here, we will analyze the cause of sampling jitter due to stuffing in the staff synchronizer configured as above, using the second-order group multiplex converter recommended in CCITTG742 as an example. I would like to clarify the difference from the present invention. The above-mentioned secondary group multiplex converter synchronizes four sets of mutually asynchronous 2.048 Mbps digital signals on the transmitting side using a positive shifter and multiplexes them bit by bit. This is a device that multiplexes and exchanges digital signals at a speed of 8Mbps (abbreviated as 8Mbps), performs demultiplexing on the receiving side, and destuffs them to reproduce the original low-order group signal. This frame structure is then divided into four sections each consisting of 212 binary digits, as seen in the format of FIG. The first 10 bits of the distribution of time slots in the first section constitute a frame synchronization information signal (1111010000). The next two bits (11th bit and 12th bit) are a bit for alarm transfer (11th bit) and a bit prepared for future use (12th bit). Remaining
200 bits are used to transmit information for each lower order group.
The second to fourth sections have the same configuration, and the first four bits of each section are staff control bits for indicating the staff status of each lower order group. Determination of the staff state is performed by majority voting on the control bits allocated to each lower order group of these three divisions. Subsequent time slots, similar to those of section 1, are used for transmitting information for each lower order group. The second group of the fourth section are variable time slots, in which dummy pulses are inserted instead of data during stuff time.

In this multiplex converter, the bit rate on the higher order group side is _h =8448000Hz±30ppm. According to the frame structure, 206 bits in one frame are used as information bits for one low-order group. The following equation is obtained for this bit rate _p .

_p = _h /848×206 ...(1) This is nominal _p = (206/848)・8448=2052・226k
It is Hz. In addition, since there is one time in one frame when stuffing is possible, the maximum stuffing possible frequency _n
is _n =8448/848=9.96226kHz. The bit rate of the low-order group input is _l =
2048000Hz±50ppm. Therefore, the average speed at which staff operation is actually required is _s = _p - _l . And the ratio ρ at which the statistics are actually performed
is ρ= _s / _n . This nominal value is ρ=0.4242, and considering the input/output tolerance range, ρ _nio =0.4078 and ρ _nax =0.4407.

By the way, the generation of jitter in a multiplex converter is basically caused by matching the symbolic speed of the low-order group input signals to a certain common speed in order to insert stuff pulses (dummy pulses) before multiplexing. and by aligning this matched signal into a higher order group frame. Therefore, jitter appears in the output of the phase comparator as a phase difference between the write clock and read clock of the buffer memory provided on the transmitting side. This jitter can be classified as follows.

(a) High frequency jitter: This is caused by the periodic insertion of service bits (synchronization bits, staff control bits, etc.), and the waveform is sawtooth.

(b) Status jitter: This is caused by staff operations, and can be further divided into status jitter and waiting time jitter.

The statue vine is a component generated by the statue itself, and its amplitude is 1 bitp-p. Latency jitter is a low frequency jitter caused by the queuing time between a staff request and staff fulfillment. Residual jitter, which is a problem in multiplex converters, is a component that passes through the low-pass filter of the phase synchronization circuit in the receiver, and is caused by waiting time jitter. This residual jitter is expressed as a function of the staff rate, and it is known that when the staff rate is expressed as an integer ratio (rational number), it reaches a maximum in the vicinity thereof. To summarize, the staff rate ρ is ρ= _p − _l / _n = q/P+d (0<ρ≦1)……(
2) When shown as , the jitter amplitude is 1/P (bitp-p)
The frequency is d·P/tm. Here, q/P: simple rational number d: deviation of the staff rate from the simple rational number. The relationship between the jitter generation point of this 8M quadratic group multiplex converter and the jitter amplitude obtained from equation (2) is as shown in FIG. 3.

In the phase comparator, the phases of the write pulse and the read pulse to the buffer memory are compared, and when this phase difference becomes smaller than a certain threshold Λ, a staff request is made, and after sending the staff control bit, Statfing is performed. The phase difference between the write pulse and the read pulse when the low-order group input frequency and the high-order group output frequency are respectively at their nominal values, and the normalized frame interval that indicates which information bit in which frame is to be read. When the relationship with the time of change is calculated, it becomes as shown in the graph of FIG. Here, the threshold Λ = 2 bits, the high-order group output frequency _h = 1/t _h = 8448000 Hz, and the low-order group input frequency _l = 1/t _l = 2048000 Hz. When analyzing low frequency jitter, t ^N ₁ shown in Figure 5 is used.
It can be easily inferred that it is sufficient to analyze the trajectory of . The locus of this point is: without staff, t ^N+1 ₁ = t ^N ₁ +212×4t _h −206t _l ...(3) with staff, t ^N+1 ₁ = t ^N ₁ +212×4t _h −205t _l ...(4) Here, _th is the pulse width of the higher order group bit,
t _l is the pulse width of the lower order group bit. This is normalized by _H = 2112000Hz, which corresponds to 1/4t _h , and T ^N ₁ = t ^N ₁
If you create a flowchart to find the locus of ×2.112×10 ⁶ , it will look like Figure 6. It goes without saying that the processing performed based on this flowchart is achieved by the functions provided in the phase comparator. In addition, Figures 4 and 5
The graph in the figure shows an example of calculation based on the conventional theory, and in the conventional theory, the factor of the capacity of the transmission buffer memory is excluded from the calculation target. The inventor of the present application has clarified that the capacity of the transmission buffer memory has an effect on the staff jitter generated in the staff synchronizer. In Figure 6, T ⁰ ₁
=5.0 and Λ=2, the calculation result will be as shown in FIG. 7, and the trajectory of t ^N ₁ as seen in FIG. 5 described above will be obtained. This becomes a standing wave with a repetition period of 33×t _n (t _n is one frame length). This means that at the point where the input/output frequency is the nominal value, the stuff factor ρ is ρ=
This is because the point is 14/33, indicating that stuffing is performed 14 times in 33 frames, and the period is 33t _n .

The phase comparator actually used compares the phase of one read pulse of one write pulse after dividing each clock pulse by a division ratio M determined by the capacity of the buffer memory. are doing. This means that the phase comparison is performed once every M times, and therefore the phase difference between the write clock and the read clock is sampled once every M times. In order to consider the status fluctuations of actual equipment,
This sampling effect, i.e.
It is necessary to take into account at what position in the frame the phase comparison for determining the presence or absence of a staff request is performed. This sampling jitter will be discussed below. Focusing on the quadratic group multiplex converter at 8 Mbps, the position where the final determination of the presence or absence of staff is made is limited to any one of #206-M+1 to #206 in the frame, taking buffer memory capacity into account. . Its position is n
I will show it as. Taking into account the sampling effect, the flowchart for determining the trajectory of T ^N ₁ is modified as shown in FIG.

By the way, the capacity of the transmission buffer memory is determined by the following items: (1) gaps due to the insertion of control bit pulses (frame synchronization signals, staff control pulses, etc.); (2) jitters in waiting time (the amount of time the staff performs after a staff request is issued); (3) Gap due to stuff pulse insertion (4) Jitter generated in the low-order transmission line (5) Determined by considering the tolerance to the circuit. Now, we are increasing the transmission memory capacity to 8 bits and 8 bits, which is a power of 2.
Let's consider the sampling jitter when choosing 6bit. First, the buffer memory capacity is
Consider the case of 8 bits (M=8). In this case, the position n at which the final determination of the presence or absence of staff is made is any one of #199 to #206. This n is the 9th
This is determined by the flowchart shown in the figure, and according to this, the shift occurs by 2 bits for each frame, and when stuffing is performed, the shift occurs by an additional 1 bit. The period of the value of n depends on the stuffing rate, but if we focus on the stuffing rate ρ=14/33, stuffing is performed 14 times in 33 frames. Therefore,
The number of shift bits at the time of final phase comparison is 2×33+14
= 80, which is a common multiple of 8 bits. This confirms that the value of n has a period of every 33 frames. It can be seen that in the generation of this stuff rate, the repetition period in which stuffing is performed and the value taken by n are synchronized. This state is called a synchronization phenomenon. In order to analyze the influence on this synchronization phenomenon, let us consider the case where the stuff rate ρ deviates slightly from 14/33.The point at ρ=14/33 is _l =2048000Hz when _h =8448000Hz.
Now, by substituting the high-order group output frequency _h = 8448000 Hz and the low-order group input frequency _l = 2048001 Hz into the flowchart of Fig. 8, the computer calculates T ^N _1.
Find the trajectory of. In this case, since T ^N ₁ has one period every 33 frames, it is divided into one block every 33 frames, the average value of the trajectory of T ^N ₁ is calculated for each block, and the change in value is I see. In this way, observing the transition of the average value every 33 frames means observing the low frequency component of T ^N ₁ , that is,
This is equivalent to observing the jitter waveform after it has been smoothed by the PLL on the receiving side. As a result of calculation, the trajectory of ₃₂ 〓 ^N=0 T ^N ₁ /33 has a jitter amplitude of 0.243 bitp−.
p, we suspected the existence of strong low-frequency jitter with a jitter frequency of 4.13Hz. Let the low-order group input frequency be _l =
The same calculation results were obtained when the frequency was set to 2047999Hz. The difference between the two is the slope of the jitter waveform. In the former, the jitter waveform increases with time, whereas in the latter, it decreases with time. The locus of the average value of T ^N ₁ for every 33 frames is shown in FIG. 10. This example shows a case where the capacity of the transmitting side buffer memory is M=8 (bits), and therefore the frequency division ratio of the frequency divider is also set to M=8, that is, at 8-bit intervals. In this figure, a shows the case where _l =2048001Hz, and b shows the case where _l =2047999Hz. Analyzing this calculation result, the jitter amplitude is 0.243≒8×1/33bitp-p, and as is conventionally known, the waiting time jitter amplitude is the stuff rate ρ=q/P+d (0<ρ ≦
It can be seen that the value is about 8 times that of 1/P=1/33 bitp-p in case 1). Also, its frequency is 4.13Hz≒d・P/t _n × 1/8, which is approximately 1/8 of the frequency of waiting time jitter.
The value has become 8.

Next, let's consider the case where the buffer memory capacity is set to 6 bits (M=6). In this case,
The position n at which the final determination of the presence or absence of staff is made is one of #201 to #206. This n is the first
According to the flowchart shown in FIG. 1, the data is shifted by -2 bits every frame, and if stuffing is performed, it is shifted by -1 bit. In short, the rotation direction is reversed compared to when M=8. Now, focusing on the point where the stuff rate ρ=8/19, stuffing is performed 8 times in 19 frames. Therefore, the number of shift bits at the time of the final phase comparison is -2.times.19+8=-30, which is a common multiple of 6. This confirms that the value of n has a period of every 19 frames. It can be seen that the repetition cycle performed with the stuff at the point where the stuff rate occurs is synchronized with the value of n. In order to analyze the jitter characteristics at this point, M
Let's try the same method as used in =8. ρ
= 8/19 point is _l = 2048031.777Hz when _h = 8448000Hz. Now, the higher order group output frequency
_h = 8448000Hz and lower order group input frequency _l =
Substitute 2048031Hz into the flowchart in Figure 8.
Find the trajectory of T ^N ₁ . In this case, since T ^N ₁ has one cycle every 19 frames, the average value for each block is determined and its transition is observed. As a result of calculation, in the trajectory of ₁₈ 〓 ^N=0 T ^N ₁ /19, a gap of 0.05 bit _pp ≒ 1/19 appears six times, and the total is about
It has an amplitude of 0.21 bit _pp and a frequency of 2.42 Hz. When M=8, a gap of 1/P×8 occurs at one time, whereas when M=6, a gap of 1/P appears distributed over six times. Therefore, the absolute amplitude A has a relationship of A<1/P×6. However, the frequency is 2.42≒d・P/t _n × 1/6, which is about 1/6 compared to the frequency of waiting time jitter.
It has become an extremely low frequency. The lower order group input frequency is _l
The same tendency appeared when = 2048033Hz.
The difference between the two is that, as in the case of M=8, if the low-order group frequency is lower than the critical point, the jitter waveform decreases with time, and if it is higher, it increases with time. The locus of the average value of T ^N ₁ for every 19 frames is shown in FIG. 12. This example shows a case where the capacity of the transmitting side buffer memory is M=6 (bits), and therefore the frequency division ratio is also M=8 (bits). In this diagram,
A is for _l = 2048031 Hz, and b is for _l = 2048033 Hz.

By analyzing the sampling jitter in the conventional device described above, it has been found that the staff period determined by the staff ratio matches the period taken by the final phase comparison position n determined by the frame length and frequency division ratio M. It will be seen that in this case (synchronized state), strong low frequency jitter occurs. and,
At that time, the maximum amplitude of the jitter is A≒1/P×M, and its frequency is F≒d·P/tm×1/M. This is brought about by phase comparison in the transmitter being performed once for every Mbit.

Next, an embodiment according to the present invention will be described with reference to the block diagram of FIG. In this figure, the only difference from the conventional configuration shown in Figure 1 is the capacity of the transmission buffer memory 1' and the division ratio of the frequency dividers 2' and 3'; other elements have the same symbols. As shown below, they each have the same function. In this example, the capacity M of the transmission buffer memory 1' is set to a prime number 11,
Furthermore, the frequency division ratios of the frequency dividers 2' and 3' are each similarly selected to be a prime number of 11. The operation of this embodiment is the same as that of the conventional example shown in FIG. 1 except for the following points, and therefore the description will not be repeated.

According to the above configuration, referring to the analysis of sampling jitter in the conventional apparatus described above, the position n at which the final determination of the presence or absence of staff is made in the case of M=11 is one of #196 to #206. This n is determined by the flowchart in Fig. 14, and shifts by 3 bits every frame.
If the stuff is performed, there will be a further shift of one bit. The number of shift bits at the time of the final phase comparison is 3×33+14=113, which is not a multiple of 11. Therefore, it can be seen that the repetition period performed by the staff and the value taken by n are not synchronized.

In this embodiment, if low frequency jitter occurs, it should occur at a point where the stuff factor ρ=14/33, and its amplitude should be 1/33 bit _pp .

However, since M=11 was selected, the above-mentioned asynchronous phenomenon occurred, and no jitter could be observed in the output of the low-pass filter with a cut-off frequency of about 20 Hz in the receiving side PLL. Furthermore, as a result of trying simulation using a computer by selecting the stuff factor near ρ = 14/33, we found that if the cutoff frequency of the PLL was chosen to be around 700Hz, jitter of about 0.1 bit _pp at maximum was observed;
By lowering the frequency to about 70Hz, the jitter component was smoothed and became weak, about 0.01 bit _pp . This means that by sampling the waiting time jitter with a sampling period of M=11, the 1/33rd jitter component that should originally appear is scrambled, making the stuff rate pseudo-equivalent to an irrational number. This is because it is converted to become . This is a scatter effect that appears in a random process.

In the above embodiment, the capacity M of the buffer memory 1' and the frequency division ratio M of the frequency dividers 2' and 3' are each selected to be 11.
It goes without saying that any prime value consisting of 11, 13, etc. may be selected.

Methods for evaluating the effects of the present invention include calculation methods and experimental methods. Experimental data when a transmission buffer memory of =11 is applied can be shown. The graph in Figure 15 shows this experimental data. According to this, the jitter amplitude does not exceed 0.1 bit _pp , and there is a large margin compared to the conventional example of transmission buffer memory M=8, which has a jitter amplitude of 0.243 bit _pp (just within the tolerance value). It will be clear that there is.

As is clear from the above description, the present invention provides the capacity M of the transmission buffer memory and the division ratio M of the write frequency divider and the read frequency divider to 5, 7, 11, 13.
The feature is that M is set to a prime value such as The occurrence of sampling jitter is greatly suppressed, and as a result, very low frequency jitter components on the receiving side are reduced, resulting in a significant effect of improving the quality of the received signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional staff synchronizer, FIG. 1a is a block diagram showing a more specific configuration of the transmitting side buffer memory and frequency divider in FIG. Time chart for explaining the operation of the circuit in the figure, Part 2
The figure shows the format of the frame structure of the applied quadratic group multiplex converter, Figure 3 shows the relationship between the jitter generation point and jitter amplitude of the 8 Mbps quadratic group multiplexer, and Figure 4 shows the relationship between the jitter amplitude at the nominal value. A graph showing the relationship between the phase difference and the time normalized by the frame interval. Figure 5 is a graph showing the trajectory of T ^N ₁ at _h = 8448000Hz, _l = 2048000Hz, and a staff rate ρ = 14/33. Figure 6 is a graph showing the relationship between the phase difference and time normalized by the frame interval. , T ^N ₁ in Fig. 5 =t ^N ₁ ×2.112×
The flowchart for finding the trajectory of 10 ⁶ , Figure 7, is
The calculation results for obtaining the trajectory of t ^N ₁ shown in Fig. 5, Fig. 8 is a flowchart for obtaining T ^N ₁ considering the sampling effect, and Fig. 9 is a frame of phase comparison in the case of M = 8. A flowchart for determining the position n. Figure 10 is a graph showing the locus of the average value of T ^N _{1 for every 33 frames in the case of M = 8. Figure 11 is a graph showing the trajectory of the average value of T N 1} for every 33 frames in the case of M = 6. A flowchart of the determination, FIG. 12 is a graph showing the locus of the average value of T ^N ₁ for every 19 frames in the case of M=6, FIG. 13 is a block diagram showing the configuration of an embodiment according to the present invention, and FIG. ,
FIG. 13 is a flowchart for determining the frame position n of phase comparison in the embodiment, and FIG. 15 is a graph showing experimental data when a transmission buffer memory of M=11 (bits) is applied to the quadratic group multiplexing device. . In the figure, 1 and 1' are transmitting side buffer memories, 2, 2', 3, and 3' are frequency dividers, 4 is a phase comparator, 5 is a waveform conversion circuit, 6 is a staff control circuit, 7 is an inhibition circuit, and 8 is a flip-flop.

Claims (1)

[Claims] 1. A transmission buffer memory means, a first frequency dividing means for generating a clock for writing data into the transmission buffer memory means, and a second frequency division means for generating a clock for reading data written in the transmission buffer memory means. and phase comparison means for comparing the phases of the output pulses of the first frequency division means and the output pulses of the second frequency division means, and performs staff control based on the output of the phase comparison means. In the staff synchronization method of the multiplex converter, the capacity of the transmitting buffer memory is set to an 11-bit prime value, and the frequency division ratios of the first and second frequency dividing means are set relative to the capacity of the transmitting buffer memory. A staff synchronization method characterized in that it is selected to be equal to a set prime value.