JP3031779B2 - Parallel staff synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stuff synchronization system in digital signal transmission and an apparatus related thereto.

[0002]

2. Description of the Related Art As a method of digitally transmitting a large amount of data, time division multiplexing is widely known. The signal to be subjected to time division multiplexing is a signal from a signal source (hereinafter, referred to as a low-speed signal). On the transmission side, a plurality of low-speed signals are time-division multiplexed into higher-speed signals (hereinafter, referred to as a high-speed signal). Convert. On the receiving side, the transmitted high-speed signal is separated into a plurality of original low-speed signals. By using such a method, the number of necessary transmission paths can be reduced. Further, unless <br/> directly time-division multiplexed audio signal converted into a digital signal, stepwise time division multiplexing is performed. In this case, signals of the same speed are time-division multiplexed stepwise by several lines. By doing so, a transmission speed of several Gbit / s is finally obtained as a transmission speed in a long-distance section.

Incidentally, a plurality of low-speed signals to be time-division multiplexed need to have exactly the same speed. That is, if the frequency of each low-speed signal is not synchronized, time-division multiplexing cannot be performed as it is, resulting in excessive or insufficient data during time-division multiplexing.

As means for avoiding such a problem and performing normal time-division multiplexing, there is a method of precisely synchronizing a clock source serving as a reference of each low-speed signal. However, in the case of high-speed transmission (several tens of Mbit / s to several Gbit / s), there are technical and economic difficulties in implementing this method. That is, since the clock source is different for each low-speed signal, the deviation of the signal speed related to each clock source is reduced to several tens ppm of the specified speed.
However, it is difficult to match the speeds as necessary for normal time division multiplexing.

[0005] Therefore, conventionally, a method has been developed in which signal transmission is performed by time-division multiplexing by pseudo-matching the signal speed. In other words, when the speeds of a plurality of low-speed signals to be time-division multiplexed are slightly different, the transmission side performs time-division multiplexing on the required transmission section and transmits them as a high-speed signal so that the speeds are pseudo-matched. On the receiving side, there is a method of separating the signal and restoring the original low-speed signal.

The stuff synchronization system is one of such systems. The stuff synchronization method is classified into a positive stuff synchronization method, a negative stuff synchronization method, and a positive / negative stuff synchronization method according to a stuffing method.

In the positive stuffing synchronous system, the speed of the high-speed signal is set to a value slightly higher than (the specified value of the speed of the low-speed signal) × (the number of time division multiplexing) in consideration of the speed difference between the low-speed signals. Then, (high-speed signal speed) / (time-division multiplex number)
Becomes faster than the speed of each low-speed signal. In the stuff synchronization method, so-called stuffing is performed to cope with this speed difference. That is, by adding a signal (stuff signal) which is meaningless as a signal to the low-speed signal on the transmission side, the speed of the low-speed signal after adding the stuff signal is equal to (high-speed signal speed) / (time-division multiplexing number). Then, the reception side deletes the stuff signal and reproduces the low-speed signal.

Conversely, in the negative stuffing synchronous system, the speed of the high-speed signal is set to a value slightly lower than (the specified value of the speed of the low-speed signal) × (the number of time division multiplexing). Then, (high-speed signal speed) / (time-division multiplexing number) becomes slower than the speed of each low-speed signal. In the negative stuff synchronization system, the speed of the low-speed signal is made equal to (speed of the high-speed signal) / (the number of time division multiplexing) by deleting the signal from the low-speed signal on the transmission side, and the deleted signal is inserted on the reception side. Play low-speed signals.

In the positive / negative stuff synchronization system, the speed of a high-speed signal is calculated by (specified value of the speed of a low-speed signal) ×
(Number of time division multiplexing). In this case, for a low-speed signal whose speed is lower than (high-speed signal speed) / (time-division multiplexing number), stuffing similar to the normal stuffing synchronization method is performed, and conversely, the speed is (high-speed signal speed) / (time-division multiplexing number). ) For a faster low-speed signal, the same stuffing as in the negative stuffing synchronization method is performed to reproduce the low-speed signal.

A method involving such stuffing is called a stuff synchronization method.

FIGS. 6 and 7 show the structure of an apparatus according to a conventional example. FIG. 6 illustrates the configuration of the transmission unit before the multiplexing circuit with respect to a single low-speed signal, and FIG. 7 illustrates the configuration of the reception unit after the separation circuit with a single low-speed signal. It is drawn about. These figures are all shown in "Easy Digital Transmission" (Fu Yamashita, Telecommunications Association, Ohmsha, 1984). Hereinafter, the conventional stuff synchronization method will be briefly described first with reference to these drawings.

First, a buffer memory 1 constituting a transmitting unit
Is a speed conversion memory. In the buffer memory 1,
An input signal a is written by a write clock b.
The write clock b is slow, so the input signal a corresponds to the slow signal described above.

Although only one buffer memory 1 is shown in FIG. 1, in an actual device, K buffer memories 1 (K ≧ 2) are provided, and each buffer memory 1 receives a different input signal a. Is entered. The frequency of the write clocks b for the respective buffer memories 1 is adjusted and set so as to fall within the standard value, but the frequencies do not match such that direct multiplexing is possible. Therefore, each input signal a is a signal whose signal speed is slightly shifted within the standard range.

A multiplexing circuit (not shown) is connected to the buffer memory 1. The multiplexing circuit includes a buffer memory 1
Is multiplexed by K: 1 and transmitted to the transmission path. At that time, as described above, each buffer memory 1
Since the speed of the input signal a written above is slightly shifted and not synchronized, the transmitting unit synchronizes the signals using a circuit described below. That is, the signal c is given to the multiplexing circuit as a low-speed synchronized output signal synchronized with the signal (high-speed signal) transmitted through the transmission path. The speed of the synchronization output signal c is set to (speed of high-speed signal) / K, and the multiplexing circuit time-division multiplexes the K synchronization output signals c from each buffer memory 1.

In order to convert a signal written in the buffer memory 1 into a synchronized output signal c which is synchronized with a high-speed signal and has a speed of (high-speed signal) / K, (high-speed signal speed) / A means for generating a read clock related to the speed of K is required. Furthermore, in order to perform normal time-division multiplexing despite the speed difference between the input signals a of the respective buffer memories 1, stuffing is performed according to the difference between (speed of the high-speed signal) / K and the speed of the input signal a. There is a need for a means to do this. The former generally includes a clock source 5 and a read clock generation circuit 4, and the latter generally includes a phase comparator 2 and a stuff control circuit 3.

First, the clock source 5 generates a clock having a speed equal to the speed of the high-speed signal. The read clock generation circuit 4 generates a read clock by dividing the high-speed clock from the clock source 5. When multiplexing is performed at K: 1 in the multiplexing circuit as described above, the division ratio in the read clock generation circuit 4 is set to K. As a result, the speed of the read clock becomes
(Speed of high-speed signal) / K.

When the normal stuff synchronization method is implemented, the speed of the high-speed signal is set to be slightly higher than (standard value of the speed of the input signal a) × K. When implementing the negative stuff synchronization method, the speed of the high-speed signal is set to be slightly lower than (standard value of the speed of the input signal a) × K. When implementing the positive / negative stuff synchronization method, the speed of the high-speed signal is
(Specified value of speed of input signal a) × K.
Therefore, the speed of the read clock = (the speed of the high-speed signal)
/ K is generally different from the speed of the write clock b.

The phase comparator 2 is means for detecting a speed difference between the read clock and the write clock b by comparing the phases of the two. When reading the input signal a written on the buffer memory 1 by the write clock b in the order of writing by the read clock, the stuff control circuit 3
If the phase comparator 2 detects that the phase relationship between the two has deteriorated, stuffing is performed.

For example, when the write clock b is slower than the read clock, when the phases of the two signals match or are close to each other, the signals are correctly read in the write order without any particular operation at the time of reading. However, if the phase relationship deteriorates, the same bit in the buffer memory 1 will be read if the reading is performed as it is. In such a case, the stuff control circuit 3
The stuff signal (stuff bit) is inserted into the read signal. That is, the main stuff synchronization is performed.

Conversely, if the write clock b is faster than the read clock, and the phase comparator 2 detects that the phase relationship has deteriorated, the stuff control circuit 3 outputs a predetermined signal ( Remove the stuff bit). That is, negative stuff synchronization is performed.

The position where the stuff bit can be inserted / deleted is only a predetermined position in the frame constituted by the synchronization output signal c. Furthermore, this frame includes a stuff designation bit indicating whether or not stuff bits have been inserted / deleted, whereby the receiving unit can know whether or not stuffing has been performed.

Further, the receiving section has a configuration as shown in FIG. This figure is a diagram illustrating a circuit subsequent to a separation circuit (not shown) for a single low-speed signal.

First, the receiving section has a buffer memory 8. This buffer memory 8 is a memory for speed conversion, converts the parallel synchronization signal d into an output signal f, and outputs it in the order of writing. The parallel synchronization signal d is a parallel signal obtained by separating a high-speed signal at 1: K by a separation circuit (not shown).
Input one of the parallel bits.

The receiving section includes a write clock generation circuit 6 and a destuff control circuit 7. The write clock generation circuit 6 synchronizes with the high-speed signal and receives the parallel synchronization input signal d by the reception clock e received from the transmission unit.
Is written into the buffer memory 8. At this time, since the stuffing is performed in the transmission unit, it is necessary to cancel (destuff) this stuffing in the reception unit. The destuff control circuit 7 is a circuit for that purpose,
The presence / absence of a stuff bit is determined based on the stuff designation bit. For example, in the case of the regular stuff synchronous system, the stuff bit is deleted and only the information bit is written into the buffer memory 8.

Since the parallel synchronization input signal d is a signal obtained by separating a high-speed signal, it is synchronized with the read clock of the transmission unit. Therefore, in order for the receiving section to reproduce the same signal as the input signal a to the transmitting section, it is necessary to perform speed conversion, not just destuffing alone. The output signal f is a signal obtained by converting the speed of the original input signal a and the same, the speed conversion is performed by reading and control of the clock speed from the buffer memory 8.

The speed control of the read clock from the buffer memory 8 is performed by controlling the write clock to the buffer memory 8 excluding the stuff bit (the received clock e after destuffing) and the speed of the buffer memory 8 generated by the voltage controlled oscillator 11. The phase comparison with the read clock and the oscillation frequency control of the voltage controlled oscillator 11 are executed. That is, although the frequency of the parallel synchronization input signal d and the write clock to the buffer memory 8 excluding the stuff bit are locally synchronized, they do not match as a long-term average. The write clock to the buffer memory 8 excluding the stuff bit is synchronized with the input signal a to the transmission unit on a long-term average. Therefore, compared with the write clock of the buffer memory 8 phase and the read clock phase by the phase comparator 9, and feeds back the phase comparison result to the voltage control oscillator 11. that time,
PLL (Phase Locked Loop) using low-pass filter 10
Is configured.

In this way, a plurality of input signals a which are not synchronized with each other and whose speeds are shifted within a standard range are pseudo-synchronized, time-division multiplexed, and reproduced by the receiving unit. It becomes possible.

Next, the configuration and operation of this conventional example will be described in more detail.

First, as described above, since the high-speed signal output from the transmission unit is a time-division multiplex of a plurality of input signals a, the low-speed signal is converted from the high-speed signal to the parallel synchronization input signal d on the receiving side. When separating, it is necessary to identify each low-speed signal. Also, the receiving section needs to identify the stuff signal added / deleted for each low-speed signal.
Therefore, when performing time division multiplexing of the input signal a at the transmitting unit, a high-speed signal respectively a repetition of frames that have a predetermined length includes a plurality of information bits, a signal for identifying each frame Add. Usually used as this signal is a frame synchronization signal, which is inserted at the beginning of each frame.

As described above, when a high-speed signal is composed of a plurality of frames, the receiving section can identify each low-speed signal only by establishing frame synchronization. To take the frame synchronization means to detect the frame synchronization signal and identify the head of the frame. Note that the transmission speed of the high-speed signal increases by an amount corresponding to the insertion of the frame synchronization signal.

Further, when the input signal a is time-division multiplexed,
If the frame length (the number of bits constituting the frame) is an integral multiple of the time division multiplexing number K, processing for separating a high-speed signal into a low-speed signal can be simplified. That is, the bit position in the frame and the system of the input signal a can be easily associated with each other. For the same reason, the number of bits of the frame synchronization signal is also set to an integral multiple of the time division multiplexing number K.

The frame length is set in consideration of the following two points. First, if the frame length is too short, the speed increase of the high-speed signal accompanying the insertion of the frame synchronization signal increases,
If the frame length is too long, fault detection and
It takes time to synchronize the frames when recovering . Therefore, the frame length is determined by a trade-off between the two, so that it is possible to secure the ease of frame synchronization while suppressing an increase in the speed of a high-speed signal. Usually, the frame length is hundreds to thousands of bits.

Further, in order to appropriately identify the position of the stuff bit in the destuff control circuit 7 of the receiving section, it is preferable that the position of the stuff bit in the parallel synchronization signal d can be known by frame synchronization. Therefore, the position of the stuff bit is defined in the frame. Whether or not a stuff bit is inserted at the predetermined position is indicated by a stuff designation bit. The destuff control circuit 7 of the receiving unit performs a stuff determination based on the stuff designation bit, and determines whether the stuff bit is inserted at a predetermined position (in the case of the main stuff) or whether the stuff bit is deleted from the predetermined position. (For negative staff). If the positions of the stuff bits are defined in the frame in advance, the positions of the stuff bits can be identified by synchronizing the frames. The number of stuff bits that can be inserted in one frame is usually one bit per low-speed signal system, and is limited to several bits at most. In addition, since the reception unit deletes the stuff bit after the stuff determination, the position of the stuff signal is set after the stuff designation bit. Further, since an error in the stuff determination leads to an identification error in all of the low-speed signals, an odd number of stuff designation bits is usually defined for each stuff bit, and the same value is inserted into the transmission unit by the transmission unit, and the reception unit Then, based on the information of the odd number bits of the stuff designation signal, the stuff is determined by majority decision. Thereby, more reliable determination can be performed.

By the way, in the frame of the high-speed signal, in addition to the stuff bit and the stuff designation bit, a monitoring control signal for monitoring and controlling a transmission error in the multiplexing section is inserted. The insertion positions of these signals are also specified in the frame. Therefore, when looking at each frame of the high-speed signal, even in a frame in which stuffing is not performed, prescribed signals such as a frame synchronization signal, a stuff designation signal, and a supervisory control signal are inserted. In this example, prescribed signals such as a frame synchronization signal, a stuff designation signal, and a supervisory control signal are inserted, and a stuff signal is inserted into a corresponding low-speed signal.

FIG. 8 shows an example of the frame configuration disclosed in the above "Easy Digital Transmission".
The example of the configuration of the frame shown in FIG.
2.064 Mb / s signal is converted to 9
It is a structural example of a frame multiplexed on a high-speed signal of 7.728 Mb / s.

The speed per low-speed signal is 32.57.
In the present configuration example, a unit in which three low-speed signals are multiplexed one bit at a time is referred to as a G unit. Also, 64 consecutive G units are collectively called a G frame, and the first G unit (3 bits) of each G frame
Are a frame synchronization signal, a stuff designation signal, and a signal for supervisory control, respectively. Further, six consecutive G units are collectively called an S frame, and this S frame is
This corresponds to the frame in the above description. The number of bits in one S frame of the high-speed signal is 1152 bits, and 1
The information signal per low-speed signal is 378 bits, the stuff signal insertion bit is one bit of the second G unit of the sixth G frame, and the stuff designation bit is three bits per stuff signal bit.

The frame synchronization signal is 6 bits, and a 3-bit monitoring control signal is specified. For a stuffed frame, the three stuff designation bits of the corresponding low-speed signal are set to “111”, and for a stuffed frame,
“000” is set. Also, the information signal in the frame of the stuffed low-speed signal has 377 bits. This frame structure is mainly used in Japan, but is also specified in the CCITT recommendation.

Next, a specific circuit configuration example of the conventional stuff synchronization method will be described with reference to the drawings.

Transmitter FIG. 9 is a block diagram of a transmitter of a conventional stuff multiplexing circuit. Let K be the multiplex number.

The clock source 14 generates a high-speed clock serving as a reference for the operation of each unit. In the K frequency divider 15,
A clock is generated by dividing the high-speed clock by K. The frame counter 16 generates a frame synchronization signal, a stuff designation bit, a stuff bit, and other timing signals for inserting a monitoring control signal. Frame counter 1
Reference numeral 6 is a reference of the frame configuration of the generated high-speed signal, and the insertion timing of the frame synchronization signal, the stuff signal, and the like is common to each low-speed signal. The pulse pattern generator 17 generates a pattern of a frame synchronization signal in the high-speed signal and a stuff designation bit. Speed conversion memory 12
(12-1 to 12-k, hereinafter simply referred to as a memory in this section), an input low-speed signal is temporarily written to the memory 12 using a low-speed clock synchronized with the signal as a write clock, and the K frequency divider 15 Is read from the memory as a read clock. The memory 12 is a kind of elastic memory having a capacity of several bits to several tens of bits, and is sequentially written,
Perform reading. However, due to the insertion timing signal from the frame counter 16, the reading from the memory 12 is not performed at the insertion timing of the frame synchronization signal or the like. Each of the input low-speed signals is a clock source 1
4 is written into the memory 12 asynchronously with the clock obtained by dividing the high-speed clock from the clock 4, the relative relationship between the write timing to the memory 12 and the read timing fluctuates. Then, the write timing and the read timing for the memory 12 are compared by a phase comparator (not shown), and if both timings are closer than a certain reference, the phase comparator outputs a stuff request. The stuff request is held in the next output frame until a stuff bit is inserted. In the frame next to the output of the stuff request, the stuff designation bit to be inserted in the corresponding low-speed signal is set to stuff insertion, and the stuff bit is inserted without reading from the memory 12 at the stuff bit insertion timing. By inserting stuff bits,
By not performing the read from the memory 12, the write timing and the read timing to the memory 12 are separated again. When the stuff bit is inserted, the stuff request is released. The K-system low-speed signals read from the memory 12 in this manner are quasi-synchronized, so to speak, with the clock from the clock source 14, and can be time-division multiplexed. The low-speed signals thus pseudo-synchronized are referred to as synchronized low-speed signals (# 1 to #K).
A K: 1 multiplexing circuit 13, which is a K multiplexer, time-division multiplexes the synchronized low-speed signals of the K system, and further inserts a frame synchronization signal or the like from the pulse pattern generator 17 so that the final output of the transmission unit is high-speed. A signal is obtained.

Receiver FIG. 10 is a block diagram of a receiver of a conventional stuff multiplexing circuit. The number of multiplexed high-speed signals to be received is K as in the transmission unit.

The frame head discriminator 21 detects the pattern of the frame synchronization signal from the received high-speed signal,
Detect the beginning of a frame. The frame counter 22 generates a separation signal for separating a high-speed signal into low-speed signals of each system with reference to the frame head detected by the frame head discriminator 21 and a frame synchronization signal inserted in the high-speed signal. Also, a delete timing signal for deleting a stuff designation signal, a supervisory control signal, and the like is generated. (K demultiplexer) 1: K separation circuit 18
In, a high-speed signal is separated into K-system low-speed signals based on the separation signal. The K frequency divider 20 divides the high-speed clock by K to generate a K frequency-divided clock. Each of the separated low-speed signals (# 1 to #K) is synchronized with the high-frequency clock divided by K, and includes a frame synchronization signal, a stuff designation signal, a monitoring control signal, and the like. In the speed conversion memory 19 (19-1 to 19-k, hereinafter simply referred to as the memory 19 in this section), each low-speed signal is written to the memory 19 using a clock obtained by dividing a high-speed clock by K as a write clock. At this time, according to the delete timing signal from the frame counter 22,
The frame synchronization signal, the stuff designation signal, the monitoring control signal, and the like are not written in the memory 19. In addition, the stuff determination is performed based on the stuff designation signal in each low-speed signal. As a result, in the frame determined to be stuffed, the stuff signal is not written into the memory 19 by the deletion timing signal from the frame counter 22. That is, the signal written to the memory 19 is only the low-speed signal input to the transmission unit.
Therefore, if the contents of the memory 19 are read by a continuous clock, a low-speed signal input to the transmission unit can be obtained. The memory 19 is a kind of elastic memory having a capacity of several bits to several tens of bits, like the transmission unit.
It is a memory that can write and read sequentially. Since the write clock to the memory 19 is a clock obtained by dividing the high-speed clock by K, the write clock is locally synchronized with the high-speed clock. However, since the frame synchronization signal, the stuff signal, the stuff designation signal, the monitoring control signal, and the like are not written in the memory 19, they are input to the transmission unit for a sufficiently long time, considering the number of clocks actually written by the write clock. The number of clocks is equal to the number of low-speed signals. Therefore, by averaging the write clock to the memory 19, a continuous read clock synchronized with the low-speed signal input to the transmission unit can be obtained. For clock averaging, a phase-locked oscillator (PLL, Phase Locked Loop)
) Is often used.

[0043] illustrates a block diagram of an example of a speed conversion memory of the transmitter to the block diagram 11 of a speed conversion memory of the transmitter. The speed conversion memory is provided with the same speed conversion memory for each low-speed signal of each system. Therefore, FIG. 11 is a block diagram of one of the speed conversion memories therein. The speed conversion memory is constituted by an edge-triggered D-type flip-flop,
In this example, the capacity is 4 bits. FIG. 12 is a timing chart showing the operation of the speed conversion memory.

In the write signal generator 24, the memory 23 (23-1 to 23-2) which is a D-type flip-flop
The write signal is generated by dividing the low-speed clock synchronized with the low-speed signal input to 3-4) by the capacity of the memory 23. Here, since the capacity of the memory 23 is 4 bits, the low-speed clock is divided by 4 to generate the 4-phase write signals 1 to 4 shifted by one clock. Each write signal sequentially writes low-speed data to the memory 23, which is a D-type flip-flop. Writing is performed sequentially from the memory 23-1 to the memory 23-4, one bit at a time during one low-speed clock.
At the next timing after the writing to the memory 23-4, the writing to the memory 23-1 is performed again. Therefore, the output of the memory 23, which is a D-type flip-flop, that is, the content of each memory 23 is obtained by converting the low-speed signal into four parallel signals, each of which is a signal having a period of four write clocks.

The clock obtained by dividing the high-speed clock by K is A
After being stopped by the ND gate 29 at the insertion timing of the frame synchronization signal, the stuff signal, etc., the signal is supplied to the read signal generator 25. The supplied clock is referred to as a read clock. The read signal generator 25 divides the read clock by the capacity of the memory 23 to generate a read signal. Here, similarly to the generation of the write signal, the clock is frequency-divided by four, and four-phase read signals 1 to 4 shifted by one clock are generated. Each of the read signals 1 to 4 has a length of one clock of the high-speed clock divided by K, and is stopped by the AND gate 29 at the timing of insertion of a frame synchronization signal, a stuff signal, etc., and has a length of two clocks. Have. The Q outputs of the memories 1-4 and the read signals 1-4 are
It is input to a two-input AND gate 20 (20-1 to 20-4). Then, each AND gate output signal is input to a 4-input OR gate 31. 4-input OR
At the output of the gate 31, a synchronized low-speed signal synchronized with a clock obtained by dividing the high-speed clock by K is obtained. Each memory 2
The content of 3 is a signal having a cycle of a length of four clocks of the write clock. In other words, the memory 23 uses the high-speed clock as the access time.
It suffices to satisfy a time four times the period of the divided clock.

The synchronization low-speed signal has a length of two clocks at the timing of inserting the frame synchronization signal, the stuff signal, etc., and inserts the frame synchronization signal, the stuff signal, etc., and outputs the K system synchronization low-speed signal. By dividing and multiplexing, a high-speed signal can be obtained.

The phase comparator 27 detects a phase relationship between a write signal and a read signal to the memory 23, that is, a time relationship between a write timing to a certain memory 23 and a read timing. When the interval between the two approaches a predetermined value or more, a stuff request is output from the phase comparator 27. In this conventional example, the phase comparator 27 is configured by a D-type flip-flop, and compares the phases of the read signal and the write signal of the memory 23-4.
As shown in the figure, a write signal to the memory 23-4 is input to a data input terminal, and a read signal from the memory 23-4 is input to a clock input terminal.
The operation of this phase comparator 27 is shown in FIG. As shown in FIG. 13A, when the write signal and the read signal are temporally separated (the phase difference is large), the value of the write signal at the rising timing of the read signal is “L”. Therefore, the output of the D flip-flop is "L". Since the read clock is faster than the write clock, the phase relationship between the two signals gradually changes with time, and the read signal approaches the write signal. Eventually, as shown in FIG. 13B, the time difference between the write signal and the read signal becomes 1
When the clock becomes equal to or less than the clock (when the phase difference becomes equal to or less than 90 degrees), the value of the write signal at the rising timing of the read signal becomes "H", so that the output of the D flip-flop becomes "H" and outputs a stuff request. When a stuff signal is inserted based on this stuff request, the write signal is delayed by one clock, so that the time difference from the read signal increases (the phase difference is improved), and D
Since the output of the flip-flop becomes "L" again, the stuff request is released.

When a stuff request is output in the middle of a frame, among the plurality of stuff designating bits specified in the frame as it is, the one near the top of the frame may have already been output. There may be a case where the value of the designated bit cannot be regarded as having the stuff signal inserted. Therefore, in such a case, the stuff request is temporarily masked by the stuff controller 28. Then, in the frame next to the frame in which the stuff request has been output, the pulse for stopping the clock input to the read signal generator 25 to insert the stuff signal by setting the stuff designation bit to be stuffed is generated. It is output by the controller 28.

[0049] a block diagram showing an example of a memory for speed conversion of the receiver to the block diagram 14 of a speed conversion memory of the receiver. The speed conversion memory is constituted by an edge-triggered D-type flip-flop, and its capacity is 4 bits. FIG. 15 is a timing chart showing an operation of an example of the speed conversion memory of the receiving unit.

The speed conversion memory of the receiving unit is hereinafter simply referred to as memory 32 (32-1 to 32-4). This memory 3
The synchronized low-speed signal input to 2 is synchronized with the high-speed clock, and includes a frame synchronization signal, a stuff designation signal, a stuff signal, other monitoring control signals, and the like. The stuff detector 34 determines whether a stuff signal is inserted in the frame by monitoring the stuff designation signal. The stuff detector 34 is supplied with a stuff designation signal deletion timing signal in the elimination timing signal from the reception unit frame counter 22, and the stuff detector 34 can know the timing of the stuff designation signal by this signal. At this time, a plurality of stuff designation signals in the synchronized low-speed signal are detected, a majority decision is made, and it is determined whether or not a stuff signal is inserted in the frame. When it is determined that the stuff signal is inserted, a pulse for stopping the clock input to the write signal generator 33 is output from the stuff detector 34 in order to delete the stuff signal.

Thus, the high-speed clock divided by K is
The writing clock is generated by being stopped by the pulse deletion timing signal from the reception unit frame counter 22 or the stuff signal deletion timing signal from the stuff determination unit. This write clock is supplied to the write signal generator 33.

The write signal generator 33 generates a write signal by dividing the above-mentioned write clock by the capacity of the memory 32. Here, the clock is divided by 4 and 1
The four-phase write signals 1 to 4 shifted by a clock are generated. Each of the write signals 1 to 4 has a time difference of one high-speed clock divided by K, and has a time difference of two clocks at the deletion timing of the frame synchronization signal, the stuff signal, and the like. Synchronized low-speed data is written into each D-type flip-flop, that is, the memories 32-1 to 32-4, by the respective write signals.
Writing is performed bit by bit from the memory 32-1 to the memory 32-1.
-4, and at the next timing after the writing to the memory 32-4, the memory 3
2-1 is written, but the frame synchronization signal,
Writing is not performed at the timing when the stuff designation signal, the stuff signal, or the like is inserted. Therefore, among the signals included in the synchronized low-speed signal, only the signals constituting the low-speed signal input to the transmission unit are written in each memory 32 while maintaining the time order input to the transmission unit. I have. Therefore, by reading the content of each memory 32 as a continuous low-speed clock (of the same frequency as the low-speed clock used for writing in the transmission unit) as the read clock, the low-speed signal input to the transmission unit is output. can get.

The clock for writing each synchronized low-speed signal to the memory 32 of the receiving unit is generated based on a clock obtained by dividing the high-speed clock by K, and is inserted into each synchronized low-speed signal. The clock is stopped at the timing of the signal to be deleted (signal other than the low-speed signal). Therefore, although locally synchronized with the high-speed signal, for a sufficiently long period of time, it is synchronized with the low-speed signal input to the transmission unit, and by averaging each write clock, the signal is input to the transmission unit. A clock synchronized with each low-speed signal is obtained. Therefore, by using the obtained clock as a read clock, it is possible to reproduce the low-speed signal input to the transmission unit.

This clock averaging is performed using a PLL. FIG. 16 shows an example of the phase comparator 37 constituting the PLL. In this example, E is used as a phase comparator.
An XOR gate is used. The write clock and the read clock are each frequency-divided by 4, and the time during which the clock is “H” is equal to the time during which the clock is “L”. Respectively. When both signals are input to the two inputs of the EXOR gate, as shown in the figure, the duty (the ratio of time during which the signal is "H") changes according to the time difference (phase difference) between the two signals. A signal is obtained. This changing state is shown in FIGS.
It is shown in (c).

This signal is averaged by passing it through a low-pass filter, and is applied to the VCO inside the PLL, whereby an averaged read clock can be generated.

[0056]

Since the conventional stuff synchronization system is configured as described above, it is particularly tens of Mb.
When applied to the synchronization of a high-speed signal having a speed of at least it / s, a large number of elements that operate at a high speed are required, the power consumption is increased, and the heat generation is increased. As a result, there is a problem that the margin in circuit design is limited.

The present invention has been made in order to solve the above-mentioned problems, and has a stuff synchronization that can be applied to high-speed signal synchronization despite being configured using elements that operate at a low speed. The aim is to get the scheme. The purpose of the stuff synchronization method having such a configuration is to obtain a stuff synchronization method that consumes less power and generates less heat, and has an improved margin in circuit design.

[0058]

To achieve the above object, according to the present invention, a digital signal is synchronized with a clock independent of the digital signal by adding a stuff bit to the digital signal. A synchronizing signal, and a transmitting side for transmitting the synchronizing signal; and a receiving side for receiving the synchronizing signal and reproducing the original digital signal. A transmission-side storage unit that temporarily stores the digital signal, a transmission-side writing unit that sequentially writes the digital signal in the storage unit, and a transmission-side reading unit that simultaneously reads the digital signal of a plurality of bits from the storage unit. Comparing the timing of writing to the storage means with the timing of reading from the storage means, and based on the result of the comparison, By adjusting the read address side reading means, and a read control means for controlling the insertion of stuff bits, and outputs the parallel synchronization signal consisting of a plurality of bits from the transmitting side reading means,
The receiving side, a receiving side storage means for temporarily storing the parallel synchronization signal, a reception side writing means for simultaneously writing a plurality of information bits other than stuff bits to the storage means from the parallel synchronization signal, From the storage means,
Receiving side reading means for sequentially reading the written information bits, and writing control means for judging bits to be written and bits to be deleted from the parallel synchronization signals, and controlling the receiving side writing means; , And outputs a digital signal input from the receiving-side reading means to the transmitting side.

According to a second aspect of the present invention, by removing stuff bits from a digital signal, the digital signal is synchronized with a clock independent of the digital signal to obtain a synchronization signal, and the synchronization signal is transmitted. And a receiver that receives the synchronization signal and reproduces the original digital signal, wherein the transmission side temporarily stores the digital signal. Transmitting side writing means for sequentially writing the digital signal in the storage means, transmission side reading means for simultaneously reading the digital signal of a plurality of bits from the storage means, write timing to the storage means, And adjusts the read address of the transmitting-side reading means based on the comparison result. The Rukoto, and a read control means for controlling the deletion of stuffing bits, and outputs the parallel synchronization signal consisting of a plurality of bits from the transmitting side reading means, the receiving side, the parallel synchronization signal Receiving side storing means for temporarily storing, receiving side writing means for adding a stuff bit to the parallel synchronization signal and simultaneously writing the same in the storing means, and receiving side for sequentially reading the written contents from the storing means Reading means;
Writing control means for determining whether a stuff bit should be added to the parallel synchronization signal, and controlling the receiving-side writing means; anda digital signal input to the transmitting side from the receiving-side reading means. Is output.

According to a third aspect of the present invention, in the parallel stuff synchronization system according to the first or second aspect, the transmission side reading means is configured using a variable frequency divider. It is a type stuff synchronization method.

According to a fourth aspect of the present invention, in the parallel stuffing system according to the first or second aspect, the receiving side writing means is constituted by using a variable frequency divider. It is a type stuff synchronization method.

According to a fifth aspect of the present invention, in the stuff synchronization system according to the first or second aspect, the transmitting side comprises:
Parallel-to-serial conversion means for converting a parallel synchronization signal from the transmission-side reading means into a serial synchronization signal, outputting the serial synchronization signal, and the receiving side comprising: Serial-parallel conversion means for converting a signal into a parallel synchronization signal, and the converted parallel synchronization signal,
This is a parallel stuff synchronization method, which is written in the receiving side storage means.

According to a sixth aspect of the present invention, in the stuff synchronization system according to the third aspect, the transmitting side has a phase comparing means for comparing a phase of a write clock and a phase of a read clock, and the transmitting side reading means. Is characterized in that the write timing and the read timing are compared by examining phase difference information from the phase comparison means, and the division ratio of the variable frequency divider is switched according to the comparison result. It is a synchronous method.

[0064]

As described above, the stuff synchronization system according to the present invention comprises a transmitting side for transmitting and receiving a parallel synchronization signal and a receiving side.

The transmitting side reading means and the reading control means on the transmitting side simultaneously read a plurality of bits necessary for generating a parallel synchronization signal from the transmitting side storing means in which the input signal is written. Therefore, the serial synchronization signal
It is possible to operate the transmission-side readout unit and the readout control unit with a low-speed clock that is one-sixth of the clock signal synchronized with the clock signal.

On the other hand, the receiving-side writing means and the writing control means on the receiving side simultaneously write a plurality of bits necessary for reproducing the original digital signal in the simultaneously received parallel synchronization signal into the receiving-side storage means. Therefore, straight
The receiving-side writing means and the writing control means can be operated with a low-speed clock that is one-sixth of the clock signal synchronized with the column synchronization signal.

The above holds true in the so-called positive stuff synchronization system according to the first aspect and also in the negative stuff synchronization system according to the second aspect.

It is a simple technique to use a variable frequency divider as a transmission side reading means on the transmission side. Furthermore, it is a simple method to use a variable frequency divider also as a receiving side writing means on the receiving side.

In the above-mentioned parallel stuff synchronization system, the generated parallel synchronization signal is generally transmitted as it is in parallel. However, the parallel synchronization signal is converted into a serial signal by a parallel / serial converter and then transmitted. It is also suitable.

For comparison between the write timing and the read timing, it is a simple method to use a phase comparison means for comparing the phases of the write clock and the read clock.

[0071]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the drawings. First, the configuration and operation of the transmitting side will be described, and then the configuration and operation of the receiving side will be described.

[0072] The transmission side Figure 1 is a functional block diagram of an embodiment of a transmitting side of the present invention is shown. Let the number of bits of the parallel synchronization signal be N and the capacity of the storage means be M. FIG. 2 is a timing chart showing the operation when the stuff operation is not performed in the present embodiment. FIG. 3 is a timing chart showing the operation when the normal stuff operation is performed in the present embodiment. FIG. 4 is a timing chart showing the operation when the negative stuff operation is performed in the present embodiment.

The input signal a is first stored in the storage means 42 comprising a buffer memory having a capacity M. Then, the contents of the storage means 42 are read out means 44 comprising a variable frequency divider.
Is read by Further, the phase comparing means 2 compares the phases of the write clock b and the read clock. Based on this phase difference information, the read control means 43
By adjusting the address of the variable frequency divider 44, the stuff bit is inserted into the N parallel parallel synchronization signals c. The read clock generated by the variable frequency divider 44 is generated in synchronization with the clock generated by the clock source 5.

Next, the operation on the transmitting side will be described with reference to FIGS. 2, 3 and 4.

[0075] read and write to the storage means 42, in the 0~ (M-1) address, is done to address the order. The variable frequency divider 44 constituting the transmission side read means uses the clock of the speed of the N parallel synchronization signal c as the operation clock, and normally (when no stuff bit is inserted)
A count-up operation is performed every time. Under the control of the read control means 43, when it is necessary to insert a stuff bit, a count-up operation of 0 to (N-1) is performed. Since the output of the variable frequency divider 44 is used as an address of the storage means 42, the output is in the range of 0 to (M-1) in any case. That is, when the value becomes larger than M-1 by the count-up operation,
The output of variable frequency divider 44 wraps around to zero.

Each bit constituting the N-parallel parallel synchronization signal c is # 1 in ascending order of phase when converted into a serial signal.
To #N.

The input signal a is sequentially written to the storage means 42 having the capacity M by a write clock b synchronized with the input signal a.

Operation when Staff is Not Performed Operation when staff is not performed is shown in FIG. The input signal a is sequentially written to the storage unit 42 having the capacity M by a write clock b synchronized with the input signal a, as in the conventional configuration. The clock output from the clock source 5 is frequency-divided by the number of multiplexes, and further frequency-divided by N.
A read clock is generated at 1 / N of the speed of the serial synchronization signal c, that is, at the speed of the N parallel synchronization signals c.
As in the example shown in FIG. 2, if the output of the variable frequency divider as the transmission side reading means is n at the output timing not including the stuff bit, n of the memory 1
The contents of the storage means 42 of the Nth to (n + N-1) th consecutive bits are read out and output to the N-parallel synchronization signals # 1 to #N in the order of writing timing. At the next output timing, the variable frequency divider 44
Is counted up by N to become (n + N), and the consecutive contents of N bits from (n + N) th to (n + 2N-1) th of the storage means 42 are read out, and similarly output as N parallel synchronization signals c. I do.

Operation When Correct Stuff is Performed The operation when correct stuff is performed is shown in FIG. If the speed of the input signal a is lower than the speed of the read clock, a stuff bit is inserted into the synchronization signal c as follows. First, the phase comparison means 2 compares the phase relationship between the write clock b and the read clock. As a result, the phase relationship between the two clocks has deteriorated.
That is, if it is determined that the timing of writing to a certain memory and the timing of reading from that memory are closer than a predetermined threshold value so as not to cause an error, the storage unit 42 By controlling the reading, a stuff bit is inserted into the N parallel synchronization signals c. At the output timing at which one stuff bit is inserted, at the output timing at which the immediately preceding stuff bit is not inserted, the variable frequency divider 4
4 is n, the read control means 43 sets the increment of the variable frequency divider 44 to (N-1), and as a result, the output of the variable frequency divider 44 becomes (n + N-
1). Then, the (n + N-1) th to (n + 2N-2) th N-bit continuous memory contents are read from the storage means 42, and the N-parallel synchronization output signals # 1 to ## Output to N.
Accordingly, the # 1 output at the output timing is the same as the #N output at the immediately preceding output timing (n + N-
The 1) th memory content is output, and the stuff bit 1 is stored while the bit order of the input signal a is preserved.
The bit has been inserted. At the output timing following the timing at which the stuff bit is inserted, ie, at the output timing at which the stuff bit is not inserted, the output of the variable frequency divider 44 is incremented by N (n
+ 2N-1), and reads out the N-bit continuous memory contents from the (n + 2N-1) th to (n + 3N-2) th of the memory 1, and outputs it to the N parallel synchronization signal c as in the case described above. .

At the time of inserting the necessary frame synchronization bits, stuff designation bits, etc., the various bits can be inserted by controlling the increment of the variable frequency divider 44 in the same manner as described above. And an N-parallel synchronization signal c is obtained.

Operation when Negative Stuff is Performed The operation when negative stuff is performed is shown in FIG. If the speed of the input signal a is faster than the speed of the read clock, the input signal a is deleted as follows. First, the phase comparison means 2 compares the phase relationship between the write clock b and the read clock. As a result, the phase relationship between the two clocks is degraded, that is, the timing of writing to a certain memory and the timing of reading from that memory are separated from a predetermined threshold value so as not to cause an error. If it is determined that the input signal a is deleted by controlling the reading from the storage means 42. That is, at the output timing for deleting one bit of the input signal, if the output of the variable frequency divider 44 is n at the output timing at which the previous negative stuff is not performed, the variable frequency divider 44 44 is set to (N + 1), and as a result, the output of the variable frequency divider 44 becomes (n + N).
+1). Then, (n + N + 1) in the storage means 42
The contents of the storage means 42 of Nth to (n + 2N) th consecutive bits are read out and output to the N-parallel synchronization signals # 1 to #N in the order of writing timing. That is, the (n + N) th memory content is not read. Therefore, one bit is deleted while the bit order of the other input signal a is preserved. At the output timing next to the timing at which the negative stuff is performed, and at the output timing at which the negative stuff is not performed,
The output of the variable frequency divider 44 is incremented by N to become (n + 2N + 1), and the (n + 2N +)
The contents of the storage means 42 of N bits consecutive from 1) th to (n + 3N) th are read out and output as N parallel synchronization signals c as in the case described above.

At the time of inserting the necessary frame synchronization bits and stuff designation bits, the same memory contents are read out by controlling the increment of the variable frequency divider 44 as in the case of the positive stuff described above. As a result, an N-parallel synchronization signal c is obtained.

[0083] illustrating the receiving side then the receiving side of the structure and operation.

FIG. 5 is a functional block diagram of one embodiment of the receiving side of the present invention. It is assumed that the number of bits of the parallel synchronization signal is N and the capacity of the storage means is L as in the transmitting side.

The received parallel synchronization signal d is written into the storage means 47 comprising a buffer memory having a capacity L by receiving side writing means comprising a variable frequency divider. The timing of this writing is specified by the reception clock e. At this time, a determination for selecting a bit to be written from the parallel synchronization signal d is made by the write control unit 4.
6 is performed. The phase comparison means 9 compares the phase of the write clock generated by the variable frequency divider 45 with the phase of the reception-side read clock generated by the voltage controlled oscillator 11.
Done by This phase difference information is transmitted to the low-pass filter 10.
To the voltage-controlled oscillator 11 to control the output frequency.

Next, the operation on the receiving side will be described.

[0087] read and write to the storage means 47, in the 0~ (L-1) address, is done to address the order. The variable frequency divider 45 constituting the receiving side writing means uses the reception clock e at the speed of the N parallel synchronization signal d as the operation clock, and normally counts up by N each time (when no stuff bit is inserted). Perform the operation. When the stuff bit needs to be removed under the control of the write control means 46, a count-up operation of 0 to (N-1) is performed. Since the output of the variable frequency divider 45 is used as the address of the storage means 47, the output is in the range of 0 to (L-1) in any case. That is, when the value becomes larger than L-1 by the count-up operation, the output of the variable frequency divider wraps around to zero.

Each bit constituting the N parallel parallel synchronization signal d is referred to as # 1 to #N in ascending order of phase when converted into a serial signal as in the transmitting side.

Operation when stuffing is not performed At an input timing that does not include a stuff bit, assuming that the output of the variable frequency divider 45, which is the receiving-side writing means, is n, the variable frequency divider 45 outputs N parallel signals. Using clocks synchronized with the synchronization signal d, the N-parallel synchronization signals d # 1 to #N are stored in the storage unit 47 from the n-th position (n + N−
1) Writing is performed in the area of the storage means 47 in which the N-th consecutive bits are stored. At the next input timing, the output of the variable frequency divider 45 is incremented by N, and (n + N)
Similarly, the N-parallel synchronization signal d is written into the N-bit continuous memory from the (n + N) -th to (n + 2N-1) -th memory unit 47.

Operation When Correct Stuff is Performed When the correct stuff is performed, the write control means 46 determines the presence or absence of the correct stuff from the stuff designation bits in the N-parallel synchronization signal d. Is determined, that is, if the stuff bit is inserted, the stuff bit is deleted by controlling the writing to the storage means 47.

Assuming that the output of the variable frequency divider 45 is n at the input timing not including the previous stuff bit, the variable frequency divider 45 is incremented by (N-1) by the write control means 46, Its output is (n + N
-1). Of the N parallel synchronization signals d, (N-1) input signals excluding the stuff bit are converted to (n + N)
The (N-1) -th to (N-1) -th (N-1) -th bits are written in the continuous memory area 47. Storage means 4
No writing is performed on the (n + N-1) th of the seventh signal, and the written signal is stored at the previous input timing.

At the input timing that does not include the next stuff bit, the variable frequency divider 45 is incremented by N, and its output becomes (n + 2N-1), and the N parallel synchronization signal d is changed to the (n + 2N-1) th. To (n + 3N-
2) Write the data to the storage means 47 of N bits up to the first bit. By adjusting the increment of the variable frequency divider 45 in the same manner as described above, it is possible to write the parallel synchronization signal d into the storage means 47 excluding the frame synchronization bit and the stuff designation bit. Therefore, the bit order of the input signal is preserved, and the input signal a on the transmitting side is reproduced in the storage means 47.

Operation When Negative Stuff is Performed When negative stuff is performed, the write control means 46 determines the presence or absence of negative stuff from the stuff designation bits in the N-parallel synchronization signal d. Is determined, that is, if it is determined that the deleted signal exists, the writing to the storage unit 47 is controlled to insert the deleted signal again in the transmission unit.

At the input timing at which it is determined that there is no previous deleted signal, the output of the variable frequency divider 45 becomes n
, The variable frequency divider 45 is incremented by (N + 1) by the write control means 46, and its output is set to (n + N + 1). The N parallel synchronization signals d are
The (n + N + 1) -th to (n + 2N) -th N-bit continuous data are written in the area of the storage means 47. (N +
No writing is performed in the N) th memory, and the previously written signal is stored. If this part is regarded as a signal deleted in the transmission unit, it means that the signal deleted in the transmission unit is pseudo-inserted again.

At the input timing when the next deleted bit does not exist, the output of the variable frequency divider 45 is incremented by N, and the output becomes (n + 2N + 1). As a result, the N parallel synchronization signals d are (n + 2N +
The data is written in the area of the storage means 47 where N bits from the 1) th to the (n + 3N) th are continuous.

The frame synchronization bit, the stuff designation bit, and the like are adjusted by adjusting the increment of the variable frequency divider 45 in the same manner as described above, so that the parallel synchronization signal d is adjusted.
It is written to the storage means 47 pressurized et Installing except for. Therefore,
The bit order of the parallel synchronization signal d is preserved,
In FIG. 7, the input signal a on the transmitting side is reproduced as it is, except for the signal deleted and inserted again by the negative stuff.

As in the conventional configuration, the written parallel synchronization signal d is sequentially read by a read clock generated from a clock output from the VCO, and an output signal f is obtained. The phase comparing means 9 compares the phases of the write clock and the read clock. The comparison result is averaged by passing through the low-pass filter 10 and applied to the VCO. The oscillation frequency of the VCO is controlled by such a PLL circuit, and as a result, a clock synchronized with an input signal to the transmission unit is reproduced. Therefore, if reading is performed using this clock, an input signal to the transmission unit is obtained as an output signal.

Also, by multiplexing the output signals on the transmission side in bit sequence in time series, it is possible to easily obtain the same serial output signals as those obtained by the conventional stuff synchronization method.

The stuff synchronization method according to the present invention employs the following equation:
Even when applied to the synchronization of a high-speed signal having a speed of Mbit / s or more, since the actual operation speed of each component can be configured to be low, an economical device can be realized. is there.

[0100]

According to the present invention as described above, according to the present invention, that sends a plurality of bits of the low-speed digital signal written in the transmission-side storage unit to read out simultaneously. On the receiving side, the transmitted signals are received, written simultaneously in the receiving side storage means, and sequentially read out. Thus, while the operating speed of the component was maintained at a low speed, it has the effect that large stuff synchronization scheme heat transmission rate can be obtained.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of an embodiment of a transmitting side in a parallel stuff synchronization system according to the present invention.

FIG. 2 is a timing chart showing an operation when a stuff operation is not performed on the transmitting side shown in FIG. 1;

FIG. 3 is a timing chart showing an operation when a correct stuff operation is performed on the transmitting side shown in FIG. 1;

FIG. 4 is a timing chart showing an operation when a negative stuff operation is performed on the transmitting side shown in FIG. 1;

FIG. 5 is a functional block diagram of an embodiment of a receiving side in the parallel stuff synchronization system according to the present invention.

FIG. 6 is a functional block diagram illustrating a configuration of a previous stage of a multiplexing circuit of a transmission unit in a conventional stuff synchronization scheme.

FIG. 7 is a functional block diagram showing a configuration of a subsequent stage of a separation circuit of a receiving unit in a conventional stuff synchronization system.

FIG. 8 is a configuration diagram showing an example of a frame configuration in a conventional stuff synchronization system.

FIG. 9 is a block diagram of a transmission section of a conventional stuff multiplexing circuit.

FIG. 10 is a block diagram of a receiving section of a conventional stuff multiplexing circuit.

FIG. 11 is a configuration block diagram of a speed conversion memory of a transmission unit of a conventional stuff multiplexing circuit.

FIG. 12 is a timing chart illustrating the operation of the speed conversion memory of FIG. 11;

FIG. 13 is an explanatory diagram illustrating an operation of the phase comparator illustrated in FIG. 11;

FIG. 14 is a configuration block diagram of a speed conversion memory of a receiving unit of a conventional stuff multiplexing circuit.

15 is a timing chart illustrating the operation of the speed conversion memory of FIG.

FIG. 16 is an operation explanatory diagram of the phase comparator included in the PLL shown in FIG. 14;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 transmission side storage means 2 phase comparison means 3 read control means 4 transmission side read means 5 clock source 6 reception side write means 7 write control means 8 storage means 9 phase comparator 10 low pass filter 11 voltage controlled oscillator 42 storage means 43 read control means 44, 45 variable frequency divider 46 write control means 47 storage means

Claims (6)

(57) [Claims] 1. A transmitting side that synchronizes the digital signal with a clock independent of the digital signal by adding a stuff bit to the digital signal, obtains a synchronization signal, and transmits the synchronization signal. And a receiving side for receiving the digitized signal and reproducing the original digital signal. In the stuff synchronization system, the transmitting side includes: a transmitting side storage unit for temporarily storing the digital signal; Transmitting side writing means for sequentially writing digital signals, transmitting side reading means for simultaneously reading the digital signals of a plurality of bits from the storage means, and comparing write timing to the storage means and read timing from the storage means. By adjusting the read address of the transmission-side reading means based on the comparison result, And a read control means for controlling the insertion of bits, a plurality of bits from the transmitting side reading means
A receiving side storing means for temporarily storing the parallel synchronization signal; anda plurality of information bits other than stuff bits from the parallel synchronization signal. Receiving side writing means for simultaneously writing to the storage means; receiving side reading means for sequentially reading the information bits written from the storage means; bits to be written and bits to be deleted from the parallel synchronization signal. And a write control means for controlling the receiving-side writing means, and outputting a digital signal input from the receiving-side reading means to the transmitting side. 2. A synchronizing signal by synchronizing the digital signal with a clock independent of the digital signal by removing a stuff bit from the digital signal to obtain a synchronizing signal, and a transmitting side transmitting the synchronizing signal; And a receiving side for receiving the digitized signal and reproducing the original digital signal. In the stuff synchronization system, the transmitting side includes: a transmitting side storage unit for temporarily storing the digital signal; Transmitting side writing means for sequentially writing digital signals, transmitting side reading means for simultaneously reading the digital signals of a plurality of bits from the storage means, and comparing write timing to the storage means and read timing from the storage means. By adjusting the read address of the transmitting-side reading means based on the comparison result, Comprising a reading control means for controlling the deletion of Fubitto, and a plurality of bits from the transmitting side reading means
A receiving side storage unit that temporarily stores the parallel synchronization signal, and a stuff bit added to the parallel synchronization signal to the storage unit. Receiving side writing means for simultaneously writing; receiving side reading means for sequentially reading the written contents from the storage means; and determining whether or not a stuff bit should be added to the parallel synchronization signal. Writing control means for controlling the means, and outputting a digital signal input from the receiving-side reading means to the transmitting side. 3. The parallel stuff synchronization system according to claim 1, wherein said transmission side reading means is constituted by using a variable frequency divider. 4. The parallel stuff synchronization system according to claim 1, wherein said receiving side writing means is configured using a variable frequency divider. 5. The stuff synchronization system according to claim 1, wherein the transmission side has parallel / serial conversion means for converting a parallel synchronization signal from the transmission side reading means into a serial synchronization signal. And outputting the serial synchronization signal. The receiving side has serial-parallel conversion means for converting the serial synchronization signal into a parallel synchronization signal, and the converted parallel synchronization signal. Are written in the receiving side storage means. 6. The stuff synchronization system according to claim 3, wherein the transmission side has a phase comparison unit that compares a phase of a write clock and a phase of a read clock, and the transmission side read unit receives the phase comparison unit from the phase comparison unit. The write timing and the read timing are compared by examining the phase difference information of
A parallel stuff synchronization system, wherein a frequency division ratio of the variable frequency divider is switched.