JPH03500951A - Television receiver with switching signal in memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Has switching signal in memory television receiver The present invention generates special features like picture-in-picture and zoom. Digital Oh! (Relating to a television receiver having a ray function.

Recently, inexpensive digital 71-ware and memory have become more readily available. As a result, interest in digital television is increasing. The user Digital television allows you to convert the format of an incoming video signal. Ru. For example, a digital device with a picture-in-picture or PIF function. - In television, the secondary or secondary video signal SVS (e.g. The signal from the second detector of the cassette recorder) is the main or primary video Determined by the signal PVS (e.g. the signal from the second detector of the television) Define a small image on the display screen that is superimposed on the overall image.

Typically, the secondary video signal SvS is generated at a time determined by the sampling clock signal. Sampled and digitized. Dial representing the secondary video signal SvS The digital samples are then subsampled both horizontally and vertically to generate a series of samples representing the reduced image. Image size is 3:1 When reduced to 2 sample locations and 2 line locations, the Samples and lines in between are removed.

Data extracted during one field or frame of the secondary video signal SvS Digital samples are stored in memory. These samples display deflection signals (for example, the horizontal and vertical synchronization signal components of the τ-order video signal PvS) and the desired It is read from memory using the associated clock signal. read from memory The sample is an analog signal svs' representing a secondary image reduced in size. is converted to - secondary video signal PvS and reduced size secondary video; a video output switch having an input terminal coupled to receive the signal svs'; The switch responds to the fast switching signal FSS and selects the appropriate one of the two input signals. to a display device to generate small images within a larger image. McNealy (M cNeelY) and others with application number 087.060, and “TV A multi-input digital video component processing circuit for The patent application shows an example of a picture-in-picture television receiver. Ru.

According to the invention, the n-bit switching signal SS is connected to the m-bit secondary video signal S. Combined with vS. where m and n are positive integers greater than 1 (e.g., m −6°n=6). The combined digital signal is stored in memory and then displayed on the display. It is read from memory synchronously with the location.

Means coupled to receive the memory output is adapted to receive a pair of signals, i.e. A reconstructed secondary video signal svs' and a reconstructed switching signal SS' are generated.

coupled to receive the reconstructed switching signal SS'; A decoder responsive to signal CC8 generates a fast switching signal FSS. Lord's receiving the video signal PvS and the reconstructed secondary video signal SvS'; An output switch coupled to the fast switching signal FSS and responsive to the fast switching signal When switching signal FSS is conditioned to a first state and a second state, respectively, The primary video signal PvS and the reconstructed secondary video signal svs' are displayed on a display device. send to

According to another feature of the invention, the secondary video signal SvS is an odd field O This is an interlaced video signal consisting of F and even fields EP.

The memory stores odd and even fields of the secondary video signal SVS. It has two areas for each storage.

The value of the switching signal SS stored in two areas of the memory is the value of the switching signal SS stored in the two areas of the memory. The odd and even fields of the secondary video signal SvS are displayed as respectively. The value of the switching signal SS stored elsewhere in the memory is Indicates that the reconstructed secondary video signal is not sent to the picture tube.

For example, the 2-bit switching signal SS may be 10 and 01 in the area of memory that stores the field and even fields, respectively. set equal. The 2-bit switching signal SS is applied to the remaining area of the memory. is set equal to 00.

Odd and even fields of the secondary video signal are required for display. when the contiguous code signal CC8 is set equal to 10 and 01, respectively. ・It will be recorded. The decoder is in consonance with the switching signal SS read out from the memory. Correctly condition the high-speed switching signal FSS by comparing the Ru.

The fast switching signal FSS is: (1) odd fields are required and are removed from memory; When the switching signal SS to be reproduced has an even field equal to 10, and (2 ) an even field is required and the regenerated switching signal SS is equal to 01 is set equal to logic “1” when

Otherwise, the fast switching signal is set equal to logic “0” and the A video signal PvS is sent to a display device.

FIG. 1 shows a television receiver including video component processing circuitry in accordance with the principles of the present invention. FIG.

Figure 2 shows the analog/digital (A/D) converter, input section, and switching signal insertion. The block diagram of the video component processing circuit of FIG. This is a diagram.

FIG. 3 is a detailed block diagram of the A/D converter.

FIG. 4 is a detailed diagram of the input section.

FIG. 5 is a detailed block diagram of the switching signal insertion section.

FIG. 6 is a detailed block diagram of the timing and control section.

FIG. 7 is a detailed block diagram of the output section.

FIG. 8 is a block diagram of a circuit that generates a high-speed switching signal FSS.

Figure 9 shows useful timing for understanding the operation of the video component processing circuit in Figure 1. It is a diagram.

In each diagram, the lines interconnecting the various blocks represent simple lines carrying analog signals. Represents either a single-conductor connection or a bus that transmits binary digital signals . Values near diagonal marks that intersect an individual interconnect line indicate the parallelism of that line or bus. Represents the number of connections; the value in parentheses near an interconnect line indicates the number of connections on that interconnect line. Represents the pull repetition frequency.

Also, if the incoming video signal nominally conforms to the NTSC standard format. Assume that Example of a signal that nominally conforms to the standard format of the NTSC system as a video cassette recorder or video disc player. Examples include generated video signals (hereinafter referred to as non-standard video signals).

FIG. 1 illustrates the simultaneous processing of video signals from two unrelated sources 22 and 24. A memory-dependent television receiver 2σ is shown. source 22 (e.g. television (a second detector of a TV) provides a baseband first composite video signal C■1. supply. A second detection source 24 (e.g., a video cassette recorder (VCR)) a baseband second composite video signal CV2.

The first and second composite video signals CVI and CV2 are each connected to a pair of switches. 26 and 28. Switch 26 responsive to the selection signal has two inputs. One of the power signals CV1 and CV2 (hereinafter referred to as the main video signal PVS) and select the first switch of the third switch 80 (hereinafter referred to as the video output switch). Supplied to the input terminal. A second switch 28 responsive to another selection signal includes two One or the other of the two input signals CVI and CV2 (hereinafter referred to as secondary) This is called a secondary video signal SvS. ) decoder 30 and sync separator 32. Switches 26 and 28 are known as swap switches. There is.

As mentioned earlier, the main video signal PvS is displayed entirely on the television screen. A large image with a size of A small image of reduced size is superimposed. Two users come in Which of the video signals Cv1 and CV2 generates a larger image and which one is used to generate a small image.

The decoder 30 includes a low pass filter (LPF) and a band pass filter (B Contains PF). Approximately 1.5MH! low frequency with an upper cutoff frequency of The filter removes the chroma signal and produces a luma signal (hereinafter referred to as a sub-luma signal Y).

) to pass. Approximately 3.58MH! Bandpass filter with a band of ±0.5MH+ reproduces the chroma component C from the sub video signal SVS. Receive chroma signal C The chroma demodulator is coupled to generate a pair of baseband color difference signals U and ■ (e.g., R-Y and B-Y).

The sync separator 32 extracts horizontal sync signals HS and HS from the sub video signal SvS. Regenerate the vertical signal VSS.

Since the circuits used in decoder 30 and sync separator 32 are common, It will not be explained in further detail.

The output signals from this decoder and sync separator block (i.e., Y, U, V, HSS8 and VSS,) are the video component processing circuit (VFP) 10 of the present invention. 0. The y, u, v signals are sampled and digitized; A series of 4-bit digital signals are multiplexed and Generate a sample. The 4-bit sample is a video random access medium. It is sent to memory (VRAM) 900 and stored. Stored 4-bit sample is synchronized with the horizontal and vertical raster scanning signals HDS and VDS. 900 and then sent back to the video component processing circuit 100.

In the video component processing circuit 100, the 4-bit data read from the memory 900 is The sample is analog Y'.

The signals are converted back by U' and V' times. Analog Y', U' and V' doubles The signals Y', U' and Y' are supplied to a matrix circuit 70, where the signals Y', U' and Y' are , are converted into R, G and B signals, respectively. Receives R, G, and B signals and is responsive to the main video signal PVSO color subcarrier signal component CSS. Encoder 72 encodes the reconstructed sub-video representing the reduced-sized sub-image. Generate the signal svs' (which is in baseband composite form).

The reconstructed secondary video signal svs' is input to the second input of the video output switch 80. Power is supplied to the power terminal. The first input terminal of the video output switch 80 is the main video signal. PvS. A high-speed signal from the video component processing circuit 100 The video output switch 80 responsive to the switching signal FSS outputs the main video signal PV. S and the reconstructed secondary video signal svs', and output the signal to its output terminal. A picture-in-picture (PIF) video signal is generated. PIF's Bi The video signal is divided into a first region displaying the main video signal PvS and a reconstructed sub-video signal PvS. a composite image having a second area of reduced size displaying a video signal svs'; represents an image.

The PIP video signal from the video output switch 80 is transmitted to the television receiver 20. The signal is supplied to the main signal processing circuit 82. The main signal processing circuit 82 is a PIF video Generates red, green, and blue drive signals from the signal. These signals are the red of the picture tube 90, Supplied to each green and blue electron gun. The main signal processing circuit 82 further includes a picture tube 90. A pair of horizontal and vertical deflection signals H supplied to horizontal and vertical deflection windings 92 DS and VDS are generated. Each drive confidence The red, green, and blue electron beams in response to the signal and each deflection signal illuminate the screen 94. Star scan to generate the desired small image within the larger image.

The main signal processing circuit 82 also performs horizontal and vertical synchronization of the main video signal PvS. The signal components H3S and vSS are also regenerated. Display deflection signal HDS, and V DS is the horizontal and vertical synchronization signal component H85D and the main video signal PvS. and VSS.

The horizontal synchronization signal component H3S of the main video signal PvS has its phase and frequency is used to generate a first clock signal FC3 to which the clock signal FC3 is fixed. 1st black The nominal frequency of the clock signal FC3 is set to 1280 times the frequency FH of the H8S signal. be done. In the case of the NTSC system, the horizontal synchronization signal frequency FH is 3.58MH! color vice It is set to 2/455 times the carrier wave frequency. This makes FH approximately 15.734 K) is set to lI, and F is approximately 20MH! is set to

C3 As shown in FIG. 1, the first clock signal FC3 is divided by 1280 to generate the first clock signal FC3. Horizontal synchronization of the main video signal PVS with a phase aligned with the lock signal FCS A signal having a frequency approximately equal to the frequency FH of signal component H85D is generated. rank The phase detector 102 detects the phase of the FC8/1280 signal and the horizontal synchronization signal H3S, (te (Can be used to form a flyback signal from the horizontal deflection circuit of a revision receiver) , and the phase error signal PE5c (subscript "C" represents the clock) is obtained. Occur. The phase error signal PESC is low-pass filtered by a filter 40 and is filtered out by noise. The input frequency to the phase detector 102 is eliminated. low pass filter The waved phase error signal PE5c (LPF) is sent to a voltage controlled oscillator (VCO) 42. is supplied to the horizontal synchronizing signal component H3S of the main video signal PVS. A first clock signal FC3 of 20 MHx with a fixed wave number is generated.

The video component processing circuit 100 receives two clock signals, namely (1) the main video signal; The first clock whose phase and frequency are fixed to the horizontal synchronization signal component H85D of the signal PVS. Lock signal FC8 (main clock signal, system clock signal, display fixed clock signal) (also called lock signal or line-fixed clock signal), and (2) a second clock signal that is a phase-shifted clock signal of the first clock signal; SCS (also called skew shifted clock signal) is used. second The clock signal SC8 is a horizontal synchronization signal component H3S of the secondary video signal SvS. The phase is shifted horizontally for each horizontal line to match the phase between successive phase adjustments. The first clock signal FC3 has a period equal to the period of the first clock signal FC3.

The composite video signal is added to the horizontal sync component of the video signal (which is being sampled). Sample with a clock signal that is not phase-locked or line-locked The samples or pixels are vertically misaligned. display image This problem appears as jagged vertical edges in the skew error This is also called a phase error problem. In embodiments of the invention, a secondary video signal The signal SvS is the horizontal synchronization signal component H3 once per line to avoid skew errors. sampled by a second clock signal SO3 that is phase aligned with S8. .

The secondary video signal SvS is sampled by a phase-aligned second clock signal SO8. Once pulled, these samples become the horizontal sync signal of the secondary video signal PvS. is displayed in synchronization with the first clock signal FC3, which is fixed to the signal component H3S. Ru. Otherwise, H3S, (controls the timing of the display raster) and S Discrepancies between the OS clock signals (which control the timing of samples that determine the inserted image) Due to alignment, skew errors may occur in the displayed insert image.

As will be explained later, the video component processing circuit 100 receives a second clock signal SC8. A fixed first clip displays samples of the secondary video signal SvS occurring synchronously with Clock transfer circuit for converting into samples generated in synchronization with lock signal FC8 Contains. The aforementioned U.S. patent application filed by Mr. McNeely et al. (Application No. 087) , No. 060) describes the details of such a two-clock video signal processing system. Disclosed.

As shown in FIG. 2, the video component processing circuit 100 consists of the following sections.

・A/D section 300, ・Input section 400, - Signal insertion section 500, - timing and control section 600, ・Output section 700 We will first briefly explain each of these parts, and then refer to Figures 3 to 9. Explain in detail.

The main function of the A/D section 300 is to receive analog Y, U, and V signals from the decoder 30. receive them, generate them at the clock frequency of Fe2, and produce the following sequence: To convert it into a series of 6-bit digital samples with Y, U, where: Subscript 0, 1.2. ... is Sun91"' Represents the pull number. Further, the A/D section 300 controls each line of the secondary video signal SvS. HR3T representing the timing of the first sample or first vixel in , to the input section 400. (See FIG. 9.) The input section 400 is /Receives a 6-bit digital sample at a frequency of Fe2 from the D section 300. , converting them into a series of 4-bit nibbles generated at a frequency of FC8/H.

Here, N is an integer representing the sample reduction or sampling rate. For example, all To generate a small image that is 1/3 the size of the body image, N is equal to 3. Set. The 4-bit nibble format is given by:

Margin below the nail Table 1 ・Subscript subscript 0. N, 2N... represent sample numbers, ・The numbers in parentheses 0.1.2... represent the bit number of the 6-bit sample, ・X is a blank space for one of the 2 bits of the 2-bit switching signal SS. represents the

The switching signal insertion section 500 inputs each bit of the 2-bit switching signal SS. 400 in the blank space provided in the 4-bit nibble obtained from

The 4-bit output of the switching signal insertion section 500 is sent to the memory 900, and the following It has a form.

・Subscript subscript 0. N, 2N... represent sample numbers, - The numbers 0, 1, 2, etc. in parentheses represent bit numbers.

The 4-bit nibble stored in memory 900 is stored in timing and control section 600. is extracted in response to a 6-bit memory control signal from Ru.

The output section 700 receives the 4-bit nibbles and converts them into the next video signal PvS. A reduced size image displayed as an insert in the main image formed by are converted into analog luma signals and color difference signals Y', U', and V' representing the signals.

In addition to the y', u' and V' signals, the output section 700 supplies an output switch 80. A high speed switching signal FSS is supplied.

The timing and control unit 600 includes: - a secondary video signal PvS and a secondary video signal PvS; Receives horizontal and vertical synchronization signal components of signal SVS and performs 6-bit memory control generates a large number of control signals, including signals.

FIG. 3 shows an A/D section 300. Y, U, V components of secondary video signal SvS is supplied to each sample and hold circuit 302, 304 and 306. sample The hold circuit 302 outputs the luma signal at a time determined by the SCS/2 clock signal. The signal Y is sampled and its value is held for consecutive sampling points. SC An A/D converter 308 responsive to the S/2 clock signal The main signal Y is converted into a series of 6 bits at a frequency of SCS/2 (i.e. approximately 1OMHx). Convert to digital sample. The output of the A/D converter 308 for luma is multiplexed. The signal is supplied to a first input terminal of a lexer 310 (hereinafter referred to as "MUX").

Sample hole that responds to SO3/16 clock signal (approximately 1.25MHz) Code circuits 304 and 306 generate samples of the U and V signals. SO3/ The sampled U and V signals occurring at 16 frequencies are sent to multiplexer 31 2. Multiplexer 312 responsive to SC8/16 clock signals is generated at the frequency of S OS/8 (approximately 2.5 MH), and U, Vo, Ul, V +, UO 2. Generate a series of multiplexed samples with a sequence such as V2... do.

The A/D converter 314 that responds to the clock signal of S , V, ... into a series of 6-bit digital samples. Ru. 6-bit U generated from the A/D converter 314 at a frequency of SCS/8, Samples such as V, U, and vl are input to the second input of multiplexer 310. sent to the terminal. The first input terminal of the multiplexer 310 is connected to the frequency of S OS/2. 6-bit luma samples Y, Y, , Y, generated in numbers Y, Y,, Y,.

... etc. will be received. Multiplexer 3 responsive to the clock signal of S CS/2 10 is generated at the SCS frequency (approximately 20 MH), Y, U, Y, Uo, Y 2. UO, Y3゜U, Y, V, Y, V, Y, V, Y, VO40 50607 , Y, U, . . . generates a file.

The output of the multiplexer 310 is basically transferred in a first-in, first-out (FIFO) manner. The signal is sent to the clock transfer circuit 316, which is a device. first and second clock signals A clock transfer circuit 316 responsive to FC8 and SC8 receives the clock signal of SO8. A series of YUV samples generated in synchronization with the signal are synchronized with the Fe2 clock signal. into a series of YUV samples generated by By Mr. McNealy and others mentioned above The U.S. patent application (Application No. 087,060) has a lock transfer circuit that opens It is shown.

The A, /D sections 300 in FIG. 3 are for generating the second clock signal SC8. A skew shifter or phase matching circuit 318 is provided. skew - Shift circuit 318 requires a stable reference signal H8S'. This is shown in Figure 1. This is realized by the phase-locked loop 104 shown. Low-pass filtered phase error signal The voltage controlled oscillator (VCO) 52 that responds to the signal PE5H (LPF) is stabilized. generates a HSS' signal. (Here, the subscript “H” represents the horizontal synchronization signal. Was. ) The phase detector 106 compares the phases of the two signals H3S and H3S' II 11 and generates a phase error signal PE5H. The phase error signal PE5H is a low-pass filter. The signal is supplied to a voltage controlled oscillator 52 via a filter (LPF) 50.

The waveforms shown in FIG. 9 illustrate the operation of skew shift circuit 318. Emit SO8 signal The phase of the first clock signal FC8 is adjusted at each signal transition (e.g. The horizontal alignment of the secondary video signal SVS is such that there is a constant spacing δ between edges). It is shifted in response to each occurrence of a pulse of the period signal component H3S'. McNealy Filed by Mr. Lee (McNeelY) with application number 082.419 The US patent application titled “Signal Phase Matching Circuit” includes a suitable skew shift circuit. A path 318 is disclosed.

The clock transfer circuit 316 transfers samples generated in synchronization with the clock signal of SC8. In addition to converting the A secondary video signal shown in FIG. 9 and aligned with the first clock signal FC3. A reset signal HR8T, representing the first sample of the signal SvS, is generated. Figure 9 In , HR3T is a secondary video signal generated synchronously with the clock signal of SC8. Represents the timing of the first sample of signal SvS. Reset signal HR8T is For timing control of various signal processing operations in the video component processing circuit 100 used for.

FIG. 4 shows an input section 400. As explained earlier, the input section 400 FC8/N into a series of 4-bit nibbles or data occurring at a frequency of . here , N is the sample reduction rate. If you reduce the image size by 3:1, N becomes 3. equal. For this purpose, the 6-bit YUV signal from the A/D section 300 is demultiplexed. It is sent to Lexa (DEMUX) 402. Hoax responding to Fe2 clock signal Multiplexer 402 divides the incoming sample stream into two into two sample streams. One is the frequency of FC3/2 (approximately 10MH A series of luma samples Y, Y+, Y2..., the other one is F a series of chroma samples Uo occurring at a frequency of CS/8 (approximately 2.5 MHz), Vo, U, V, U2. V2-...

The 6-bit luma sample Y is supplied to the horizontal aliasing noise prevention filter 404 for luma. be done. The output of the horizontal aliasing noise prevention filter 404 is for vertical aliasing noise prevention for luma. A filter 406 is provided. Horizontal and vertical antialiasing filters 404 and 406 is the reduced size in picture-in-picture mode In order to reduce the effect of aliasing noise in the inserted image, Limit the highest frequency of the luma signal Y in the direction.

The block 406 of the vertical aliasing noise prevention filter for luma also includes a sampling circuit. There is. In picture-in-picture (Pix-in-Pir) mode. The luma sampling circuit stores samples every (N-1) in the horizontal direction. , stores every (N-1) line in the vertical direction. Intermediate pixels and In is thrown away. For example, the reduction factor N can be any integer value 2, 3.4, etc. You can take one of the following. Zoom mode or freeze frame mode In this case, the video signal stored in the memory 900 is not subsampled. , the reduction factor N is set to 1.

6 bits generated at the frequency of FC3/2N [i.e. (F CS/2) (1/N)] Tsuto's Luma Sample Yo.

The upper 3 bits and lower 3 bits of Y, Y, etc. are sent to the multiplexer 4. 08's first and second input terminals, respectively. F CS/2 N black A multiplexer 408 responsive to the clock signal generated at the frequency of FC3/N, Generate a 3-bit sample stream with the format:

5 thousand margins It is supplied to a flat aliasing noise prevention filter 410. Kuro-jin-1 ・Subscript subscript 0. N, 2N... represent sample numbers, - The numbers 0, 1, 2, etc. in parentheses represent the bit numbers of the 6-bit sample.

6-bit chroma sump JvU, V, U from demultiplexer 402 ,V,−(occurs at FC8/8(7) frequency) avoids the effects of aliasing noise. The circumference of chroma water C3/H that limits the highest chroma frequency in the horizontal direction wave number and generates a 4-bit nibble having the format given in Table 1.

The switching signal insertion section 500 shown in FIG. The data and the associated 2-bit switching signal SS are combined to create a signal in the format shown in Table 2. Generates a 4-bit signal. The 4-bit nibble is input to input section 400 or video media. Received from either Mori900. The data from the input section 400 is represents the incoming secondary video signal SvS which has been ringed and digitized. memo The data from the library 900 was previously sampled, digitized, and stored in memory. stored and then read out again to supply to the switching signal inserter 500. represents the secondary video signal SvS.

4-bit data from memory 900 is retransmitted to switching signal insertion section 500 There are several reasons. For example, take a block of data and then It may be desirable to duplicate it elsewhere in memory 900 ( ) to produce a montage-like effect. Another example is the data Read the block, change the 2-bit switching signal associated with it, and It may be desirable to store the data back to the same location in memory 900 or to a different location. be.

This latter function is used to insert alphanumeric characters into stored information. save The information provided is for each field type of the video signal representing a different program (e.g. 9). A formal one is fine. The characters may identify a channel number or any other suitable program. The information may be in the form of information (for example, the name of the broadcasting network). These characters are used for this purpose It is stored in a portion of memory 900 that is dedicatedly allocated for the purpose.

8 During quiet periods, these characters are read from memory 900 and the appropriate switching signal is activated. SS and then retransmitted to an appropriate location in memory, with the channel number Give identification.

The 4-bit data from input section 400 and video memory 900 is shown in FIG. is sent to multiplexer 502 in the manner shown. Data from input section 400 is FC Repeat at a frequency of 3/N. Here, N is the sample attrition rate. picture i In picture mode, the sample reduction rate N is the desired size of the inserted image. It is set to 2, 3, 4, etc. according to the reduction of . Zoom mode and In the zoom image mode, N is set to 1.

The data read from video memory 900 is multiplied at the frequency of FC3/ It is retransmitted to plexer 502.

The frequency at which memory 900 is read depends on the mode of the television receiver. Piku In picture and freeze picture modes, memory 900 is fully It is read out at the clock frequency of Fe2 (i.e., =1).

In zoom mode, memory 900 is read at a reduced frequency of FC8/ be done. where K is 2.3.4...etc. depending on the desired increase or expansion. Set.

For example, if a portion of the image is to be enlarged 2:1, K is set to 2.

Multiplexer 502 is responsive to control signals from timing and control section 600. and two input streams fed to the first input terminal of switching signal combiner 504. Select one of the groups. Another input terminal of the switching signal synthesizer 504 is It is coupled to receive a 2-bit switching signal SS.

The 2-bit switching signal SS can take on four states (00, 01.10.11 ). These four states can be assigned in many different ways. these In order to understand the state assignment of It is important to know how the status signal SS is used for this purpose. mentioned earlier , the status signal SS is the 4-bit data read from the video memory 900. It is played back from the data. The reconstructed state signal SS' is the contiguous code signal CC8. (supplied from timing and control section 500) for fast switching. Generates a signal FSS (eg, 0 or 1).

In the embodiment of FIG. 5, the upper field of the secondary video signal SvS, i.e. The number field is stored in a first designated area of memory 900. memory 900 1 of the switching signal SS (i.e. of the secondary video signal SVS) stored in the area of (related to the upper field) is assigned a value of 10.

The lower or even fields of the secondary video signal SVS are stored in memory 90. It is stored in the second specified area in 0. The cut data stored in the second area of memory 900 The switching signal SS (related to the lower field of the secondary video signal SVS) is 01 is assigned a value of

- the upper (i.e. odd) field of the secondary video signal PVS is displayed and The odd fields of the reconstructed secondary video signal svs' are used as insert images. When it is desired to display the timing and control unit 6° It is programmed to set the code signal CC8 equal to ten. This results in A designated first area of memory 900 (containing the odd fields of the svs' signal) The FSS signal becomes logic "1" only when the data is read out.

The lower (i.e. even) field of the primary video signal PvS is displayed; The even fields of the reconstructed secondary video signal svs' into a small image When it is desired to display the Set the quist code signal CC8 equal to 01. As a result, the memory 900 The defined second region (containing the even fields of the svs’ signal) is read out. The FSS signal is conditioned to be a logic "1" only when the

The value of the switching signal SS stored in the remaining area of the video memory 900 is 00. Set. When the reconstructed switching signal SS' is 00, the - next video signal PvS is sent to the picture tube 90. State 11 of the switching signal SS is not used in this embodiment. It won't happen.

In another embodiment of the switching signal system in memory, the video memory 900 is divided into three areas. Incoming sequentially of secondary video signals SvS The fields (i.e. odd, even, odd...etc.) are processed in a circular manner i.e. The information is sequentially stored in three areas of the memory 900 in a round-robin format. For example, the most In the first round, the first odd numbered file of the incoming secondary video signal SvS field, the second even field and the third odd field are stored in memory 9. 1st of 00. Second. and a third area, respectively. Around the second round , the fourth even field, the fifth odd field and the sixth The even fields of the first . Second. each stored in the third area. , and so on.

The advantage of a circular memory system is that no frame of the incoming secondary video signal SvS field (i.e., odd or even) currently being written to memory 900. The same type (i.e., odd or even Another field (number) is always present. For example, the fourth even number fields are currently being written to the first area of memory 900 (the second - around), between the first - around if an even field is needed for display. from memory the second even field previously written to the second area of memory It can be read out and sent to the picture tube 90.

Depending on the mode of the television receiver (i.e. PIF, zoom, etc.), the signal are written to and read from memory 900 at different speeds, It is important to avoid situations where areas are written and read at the same time. this state There should be no visible cracks in the displayed image at the point where the intersection between writing and reading occurs. generate.

The circular memory feature described above avoids this problem.

In order to realize a circular memory function, the first . Second. Third area The switching signals SS stored in are set to 01.10.11, respectively. Mail The switching signal SSO value or state stored in another location of memory 900 is 00. be. Timing and control section 600 is stored in three areas of memory 900 field information and code in a way that avoids intersection or image break problems. Set the value of the index code signal CC8.

Note that the in-memory switching signal system of the present invention has a variable associative function. I want to be The reconstructed switching signal SS' is itself a fast switching signal FS. Does not determine the state of S. The state of the FSS signal is determined by the timing of the video component processing circuit 100. In conjunction with the contiguous code signal CC8 supplied from the timing and control section 600, The switching signal SS' is determined by the reconfigured switching signal SS'.

In the embodiment of FIG. 5, multiplexer 506 has two inputs. One is , whether the odd or even fields of the incoming secondary video signal is stored in memory 900 and has two bits of either 10 or 01. The other is the IMBUS section 508 of the video component processing circuit 100. This is a 2-bit signal supplied from Odd fields of secondary video signal SVS is written in the memory 900, the least significant bit (L The L OWE R/WRI T E signal on the connection 510 that determines SB) becomes low. .

Inverting circuit 512 inverts the signal on connection 510 and outputs a switching signal on connection 514. (MSB) of SS, thereby setting the value of signal SS to 10. Set.

If the even fields of the secondary video signal SVS are written to the memory 900, LOWER/WRITE signal on connection 510 goes high and the signal on connection 514 goes high. signal goes low, thereby setting signal SS to 01.

As mentioned above, 1. of the embodiments of the in-memory switching signal system. in one , alphanumeric characters are part of the video memory 900 dedicated for this purpose. can be stored in The cut associated with the characters stored in this portion of memory 900 The switching signal SS is set to 00 so that when this part of memory is read , these characters are not displayed. Videos stored for the purpose of identifying the source of the program. Note these characters in order to insert them into each field of the output signal. These characters and the appropriate switching signal SS (i.e. 10 or 01) and is sent to the switching signal insertion unit 500 to synthesize it. is sent back to memory for storage. In this mode, IM BUS section 508 supplies desired switching signal SS to multiplexer 506.

Multiplexer 506 is responsive to the control signal and is configured such that a first input terminal selects a 4-bit video signal. A second input of switching signal combining circuit 504 is coupled to receive data. A desired 2-bit switching signal SS is applied to the power terminal. Supplied to synthesis circuit 504 The format of the 4-bit video data produced depends on its source. video data When it comes from the input section 400, its format is shown in Table 1. B When the audio data is from memory 900, its format is shown in Table 2. It's something like this.

The switching signal synthesis circuit 504 receives a clock signal (FC3/N or FCS/K ) in response to a series of states (8 in this example) in round-tropin fashion. It is a finite state circuit that is repeatedly ordered. Normally, switching signal synthesis circuit 5 04 is a counter for obtaining information on each state and a 2-bit switching signal SS. contains combinatorial logic to insert the 4-bit data stream into the 4-bit data stream. There is. The 2 bits of the switching signal SS are inserted at appropriate locations using the method shown in Table 2. Ru.

Preferably, video memory 900 is entirely filled with a border color (eg, blue).

For this purpose, the switching signal insertion section 500 is provided with an output multiplexer 518. Re. The first and second input terminals of multiplexer 518 are connected to the switching signal synthesis circuit. 504 and IMBUS section 508, respectively. IMBUS section 508 multiplexer 518 to define the desired border color when needed. supply to. Multiplexer 518 is responsive to the control signal and connects video memory 90. Select the appropriate one of the two input signals to send to 0.

A 4-bit nibble of the format shown in Table 2 is used to generate bits in response to a 6-bit memory control signal. is written to the video memory 900. Memory 900 has separate input ports and output ports. A self-ordering dual φ-vote memory with boats. memory 900 is organized as a grid of 4-bit storage locations or storage cells. Tele One complete field of vision signal (i.e. approximately 218 or 262.144 4-bit nibbles) from the 4-bit storage location. 28 (256) rows and 210 (1024) columns are required.

A detailed explanation of this kind of suitable memory can be found in Mr. Willis. “Semi-Synchronous Data Entry and Dual-Boat Video Memory System with Port and Data Outputs” This has been done in US patent applications. This memory is manufactured by Hitachi, Ltd. Model N (18M53051P) manufactured in integrated circuit format.

Write address WA and read RA are each 13 bits wide. 13 The upper 8 bits (28 or 256 positions) define the row address. Ru. The lower 5 bits (25 or 32 blocks) are 1 block in 32 columns. Define the address that specifies the address.

In picture-in-picture mode, the incoming video signal SVS is Write to memory 900 at reduced speed (e.g., FC3/N and FH/N) read from memory at full speed, i.e. Fe2 and Fll) It will be done. Therefore, the row address of write address signal WA (i.e., 13 bits) The signal component (i.e., the upper 5 bits) is Once reset to an appropriate row address, N horizontal lines (or horizontal sync signal) number pulse, where N(2, 3...) is the reduction rate. ) can be advanced once each time.

As mentioned earlier, in PIP mode, N is set to 2, 3, etc., and the zoom Set to 1 in normal mode. Column address component (all) of write address signal WA That is, the lower 8 bits) are set once per horizontal line in response to the horizontal synchronization signal. column value and is advanced once every N pulses of clock signal FC8. subordinate Therefore, the inserted image of reduced size (i.e., the subsampled quadratic digital samples representing the video signal) are stored in sequential locations I understand. Row and column addresses can be reset to various values. By storing a large number of reduced-sized fields in field-memory ( For example, 2) can be stored. For 3:1 reduction, three consecutive pictures Only one pixel in a cell and one of three consecutive horizontal lines is memory It can be stored at 900.

In picture-in-picture mode, the row address of read address signal RA The horizontal component is reset to an appropriate starting row address for each field, and You can proceed to The column address component is reset to the appropriate starting column address for each horizontal line. is set and advanced every clock cycle. This allows secondary video The number SvS is read out from the memory 900 in synchronization with the main image.

The correspondence between memory addresses and rasters, that is, display positions, is based on the start row address and and starting column address. Two different versions of the same downsized video image If a field is stored in two different locations in field memory, then , the starting row address value and the starting column address value are the same as the contiguous code signal CC8. Continuous field can be seen.

In zoom mode, the incoming video signal SvS is at full speed, e.g. e2. FII) but at a reduced speed, e.g. 8/K.

FH/K) is read from memory. Here, K is a magnification factor. For this reason The row address component of the write address signal WA is reset for each field, You can advance line by line. The column address component of the write address signal WA is set for each line. Reset and advanced every clock cycle.

In zoom mode, the row address component of read address signal RA is It is reset to the appropriate starting row address for each line, but advances once every K horizontal lines. It will be done.

The column address component is reset to the appropriate initial column address for each line, and ・Proceeds in each cycle. This allows each pixel and and each line is repeated several times at the output of memory 900.

The top left hand corner of the zoomed display area is the starting row address and starting column address. Determined by

As mentioned earlier, the self-ordering feature of video memory 900 allows Write address simultaneously with each sample written and each sample read from memory. There is no need to supply address and read addresses. Instead, write address W A and read address RA are initialized only when synchronization is required. sequential ad The response is automatically started from the last received address in memory 900. occurs in

As mentioned earlier, in PIP mode and zoom mode, information is reduced. For example, make a note of YPcs/N, F/N and FC9/, FH/K). data is written to the memory 900 and read from it. The means by which this is achieved is as follows: By using the number.

・CGW, clock gate write, ・WE, write enable, ・CGR, clock gate read, In PIF mode, every Nth sample is stored in a sequential memory location. The clock gate write signal CGW is applied once every N clock pulses to conditioned to be high. Write every Nth line to the memory 900, To skip the middle (N-1) line, clock gate the write signal C. GW becomes a logic “0” state every (N-1) line out of N lines. be conditioned to do so. Write enable signal WE remains high.

The same downsized video image is placed in two different locations in field memory. If stored, the write enable signal WE is the first pointer of the field memory. To store an odd field in a fixed area and an even field in a second specified area used.

In zoom mode, set the clock to repeat all samples times. The gate read signal CGR is conditioned to go high once every clock pulse. can be attached. To repeat every line times, each line address is is held constant with respect to

FIG. 6 shows how to control the timing of write and read operations of memory 900. Generates various control signals (for example, WA, CGW, WE, RA, CGR, etc.) A timing and control section 600 is shown. The timing and control section 600 timing block 602, output timing block 604, and serial add interface block 606.

Input timing block 602 is required for synchronization of memory 900 Vertical and horizontal used to reset row and column addresses when is coupled to receive reset signals VR8T and HR8T. two coming in When the secondary video signal SvS is stored in memory 900, the secondary video signal Direct synchronization signal component vss and HR3TF signal (aligned with Fe2 clock) (showing the first sample of the secondary video signal) is the input timing block. 602 as vertical and horizontal reset signals VR3T and HR3T. Each is used.

Video data from memory 900 is replayed to memory 900 in synchronization with the display deflection signal. being sent back (for example, copying a block of data to another location). - Vertical synchronization signal components VSS and HR3 of the secondary video signal PVS T, signal (aligned with the FCS clock in the video signal read from memory) ) is determined by input timing block 602 at V Used as R8T and HR3T signals respectively. Multiplexer 608 and and 610 are responsive to each control signal to generate appropriate vertical and horizontal reset signals VR3. Select T and HR3T.

Input timing block 602 is a serial address interface block. It generates a 1-bit write request signal WR to be supplied to the write address block 606. Update signal WA. Similarly, output timing block 604 provides read request Signal RR is provided to serial address interface 606.

Write address signal WA and write request from input timing block 602 Request signal WR is sent to serial address interface block 606. nine Lock gate write signal CGW and write enable signal WE are serial add is directly combined with the 3-bit output of address interface block 606.

Output timing block 604 provides vertical and horizontal timing of the secondary video signal PvS. In response to the synchronization signal component VSS and H85D, the read address signal RA and clock Generates lock gate read signal CGR and read request signal RR. readout 1 female signal RA and read request signal RR are connected to the serial address interface. is passed to block 606. Clock from output timing block 604 Gate read CGR is a 3-bit serial address ink-face block 606. Directly combined with the output of the

Connected to receive write addresses, read addresses, write requests, and read requests. The combined serial address interface block 606 has three 1-bit Generate a signal.

・SAS, address clock signal ・SAD, serial address signal ・TAS, address transfer signal Basically, SAS controls the rate of serial address data transfer to memory 900. This is a gated clock signal. SAD is a 13-bit write address. address signal, 13-bit read address signal, and 6-bit control information (i.e. It consists of a 32-bit packet consisting of (eg, flags, etc.). The TAS signal When it goes low, it affects the actual transfer of 32 bits of data.

The 3-bit output of the serial address transfer block 606 provides three 1-bit signals CGW. , WE and CGR to define a 6-bit memory control signal MCL. each A more detailed explanation of the seed memory control signals can be found in The above-mentioned U.S. patent application filed under Application No. 008,729 by Mr. Please refer to the application.

FIG. For this purpose, the 4-bit video data from memory 900 is converted into analog Y', This is an output section 700 that converts the signals into signals of U' and U'. As mentioned earlier, K is This is a large ratio and is set to 2°3.4... in zoom mode. PIP mode In this mode, K is set to 1.

A 4-bit video having the format shown in Table 2 and occurring at a frequency of FC8/ ・The upper 3 bits of data are connected in cascade, and both are connected to the clock signal to FC8/ is supplied to a pair of latches 702 and 704, which are driven by.

The first latch 702 synchronizes the data and the clock signal on FC3/.

The upper 3 bits at the input of latch 704 are the lower 3 bits at its output. A combined 6-bit luma sample Y is generated.

The 6-bit luma sample Y is transferred to a 16-stage shift register 706 with 6 bits in each stage. Supplied. The 16-stage shift register 706 inputs the clock signal to FO8/2. In response, the incoming luma sample Y matches the associated U' and V' samples The luma sample Y is delayed so that

Multiplexer 708 outputs a composite blank from output timing block 604. A desired black level is inserted into the luma signal Y' in response to the luma signal Y'. D/A converter 7 10 generates an analog luma signal Y' in response to the clock signal of FC8/2. Ru.

The least significant bit of the 4-bit video data from memory 900 is sent to FC3/. 8-stage shift register driven by a clock signal (serial human power - parallel output) 712 supplied to 8-bit shift register 712 outputs 8-bit samples. Occur. The lower two bits of the eight bits represent the reconstructed switching signal SS'. Was.

The upper 6 bits of the 8 bits from shift register 712 are divided into 6 bits in an alternating manner. Represents the U and ■ signals. Latch 714 is a 6-bit U and ■ sample. bring together. A pair of latches 716 and 718 hold samples of U' and U'. Separate each.

The outputs of latches 716 and 718 are provided to respective interpolators 720 and 722.

Interpolators 720 and 722 improve U′ and U′ by generating additional samples. Flatten the steep steps in the V' and V' signals. Multiplexers 724 and 726 creates the desired black level in the U' and v' signals in response to the composite blanking signal. insert. D/A converters 728 and 730 convert analog U' and V' multiplied signals. Occur.

FIG. 8 shows a decoder 80 that is part of the output section 700 of the video component processing circuit 100. Indicates 0. The decoder 800 is a reconfigured switch from the output section 700 of FIG. It receives the signal SS' and receives the contix code signal from the timing and control section 600. Receive number CC8. The output of decoder 800 is fed to video output switch 80 This is a 1-bit high-speed switching signal FSS. in the same way as described earlier , output switch 80 is responsive to the FSS signal to output the primary video signal PVS and the reconstructed video signal PVS. Switching between the secondary video signals svs’ created by Define a small insert image.

The 2-bit switching signal SS' switches the incoming SS' sample to FCS/8. A latch 804 is provided to align the K clock signal. Switching signal SS' The most significant bit and the least significant bit of the contiguous code signal CC8 are paired as to the first and second input terminals of AND gates 806 and 808, respectively. is supplied.

The outputs of AND gates 806 and 808 are provided to OR gate 810. ora The output of gate 810 is the FSS signal.

The inputs to the two AND gates 806 and 808 and the OR gate 810, their Each output is summarized as shown in Table 5 below.

Margin below (a) Exclude cases where SS' and CC8 are equal to 11.

(b) The output of OR gate 810 is a 1-bit FSS signal.

The most significant bit, the least significant bit and the least significant bit of the two signals SS' and CC8 If there is a match between the sets (e.g. number 1 and number 4 in Table 5), the or gate 81 The output FSS of 0 is a logic "1". Otherwise, the output F of the or gate sio SS is logic "0".

The output FSS of the OR gate 810 is determined by Y', U', and V associated with the FSS signal. ’, a pair of cascaded latches 812 and 814 and and a programmable delay element 816. programmable delay element The output of 816 is sent to video output switch 80.

Special table 13-500951 (15) Submission of translation of written amendment (Article 184-8 of the Patent Act) April 27, 1990 Yoshi, Commissioner of the Patent Office 1) Takeshi Moon 1 Display of patent application PCT/US88103018 2 Name of the invention Television receiver with switching signal in memory 3 Patent applicant Address: Indeben, Princeton, New Jersey, USA 08540 Dense Way 2 Names RCSNY Licensing Corporation 4. Agent Postal code 100 Address: Room 336, Iino Building, 2-1-1 Uchisaiwaicho, Chiyoda-ku, Tokyo September 22, 1989 6 List of attached documents 7 Target of correction Scope of claims of application translation 8 Contents of amendment 1. Scope of claims of the translated text of the application Paragraphs 1 to 13 of the translated text of the written amendment Reduce the first term to the 12th term. The contents are (1) Claims No. 1 of the translation of the application. Amend Paragraph 1, Paragraph 2, Paragraph 3, Paragraph 4, and Paragraph 5, and submit each paragraph as a written amendment. Replace with claims 1, 2, 3, 4, and 5 of the translated text. .

(2) Delete claim 6 of the application translation.

(3) Amend paragraphs 7 and 8 of the scope of claims of the application translation and supplement each paragraph. Replace the original translation with claims 6 and 7.

(4) The content of claims 9 and 10 of the application translation remains the same, but Replace each term with claims 8 and 9 of the translation of the written amendment.

(5) Amend claims 11, 12, and 13 of the translation of the application, and The respective terms shall be included in claims 10, 11, and 12 of the translation of the written amendment. Replace.

The scope of the claims 1. a source of a first video signal FVS; a source of a second video signal SVS; a clock coupled to receive the second video signal and having a frequency fcs; m (m is greater than 1) that occurs in response to signal FC3 and in synchronization with the clock signal. a sample that generates a digital second video signal sample with (positive integer) bits; Means including ring means and switching of n bits (n is a positive integer greater than 1) a source (60, 508) of the signal SS; bits of the n-bit switching signal and the sampled second video signal; a predetermined sample of the clock signal, and the sample generated in synchronization with the clock signal. means (500) for forming a digital composite signal comprising: responsively stores the sampled composite signal and synchronizes to the clock signal; memory means (9) for supplying the sampled composite signal to its output terminal; 00) and means for receiving the sampled composite signal. coupled to and responsive to the clock signal, the second video signal and the n means (702, 712) for reconfiguring the bit switching signal; a source (604) of the contiguous code signal CC8 and the reconstructed switching signal; (hereinafter referred to as ss'), and the contiguous code signal C C8, the reconstructed switching signal matches the content code signal. A fast switching signal that assumes the first state when the decoding means (800) for generating the signal FSS in synchronization with the clock signal; and, The first video signal FVS and the reconstructed second video signal (hereinafter Sv S') and responsive to said fast switching signal FSS. , the high speed switching signal FSS is in the first state and the second state, respectively. At some point, the first video signal FS and the reconstructed second video signal s and switching means (80) for generating vs' at its output terminal. Television (TV) signal processing system.

2. The second video signal SvS consists of an odd field and an even field. an interlaced video signal, in which odd frames of the second video signal SVS are interlaced; The memory includes two areas for storing an even field and an even field, respectively. and the switching signal SS stored in the two areas of the memory is connected to the switching signal SS. the odd and even numbers of the second video signal supplied to the output terminal of the switching means; switching signals respectively representing fields and stored in separate areas of said memory; SS from the memory to the output terminal of the switching means. The system of claim 1, characterized in that it represents non-passage of a video signal.

3. The second video signal SVS includes a luma signal Y and a pair of color difference signals U and ■. and the means including the sampling means receives the second video signal. They are combined in such a way that Y o, U o 1Y t, Uo1Y2, U o 1Y3, U o, Y 4, V o, Y 5.　V　o　　Y　s, V oXY7, V　o　,　Y　s, U1-(The subscript 0.1.2... is m-bit digital samples with a sequence (representing the sample number) (the samples occur at clock frequency FC3). 3. The system of claim 2, further comprising:

4. said means comprising said sampling means further comprises a second of said m bits; are combined to receive video signal samples of (m/2) + B (where B is equal to means for generating a stream of video signal nibbles (a small integer number) of bits; Ori, a first sample responsive to said m-bit luma samples and lower than said frequency fcs; a first sampler that generates m-bit luma samples at a high sampling frequency; and in response to the subsampled luma samples, the first subsampled luma sample. m/R bit luma sampling occurring at R times the sampling frequency (R is an integer) (Two consecutive m/R bit luma samples are the subsampling sequence of luma samples (with m/R mutually exclusive adjacent bits) of the luma samples means for generating a color difference sample of m bits and U and ■; occurs at a second sub-sampling frequency lower than the first sub-sampling frequency. A second sample that generates a sequence of alternating U and ■ color difference samples with m bits means and Mutually exclusive bits of the m-bit subsampled color difference samples is concatenated with the m/R bits of consecutive luma samples, and (m/R ) means for generating a nibble sequence of 10B bits; a regularly occurring predetermined nibble of is concatenated with said m/R bit luma sample. 4. The system according to claim 3, wherein the system does not include bits of the color difference sample that are Tem.

5. The means for concatenating the n-bit switching signal and the (m+R) In response to a +Bn bit nibble sequence, the bits of the n-bit switching signal are the predetermined nibble among the nibbles that does not contain the bit of the color difference sample; comprising means for concatenating to m/R bits of luma samples of 5. The system according to claim 4.

6. Reconstructed m-bit luma signal Y/, reconstructed pair of m-bit colors Generate difference signals U' and V' and reconstructed n-bit switching signal SS' Therefore, the reconfiguration means generates the (m/R)+ in synchronization with the clock signal. 6. The system of claim 5, wherein the system receives Bn bit nibbles.

7. The reconstruction means further comprises digital luma of the reconstructed mbi-sight. and clock difference signals Y', U' and V'; and means responsive to the signal for generating reconstructed analog luma and color difference signals. 7. The system of claim 6, further comprising:

8. The reconstruction means further comprises the reconstructed analog luma signal and color difference signal. said second video signal coupled to receive said video signal and supplied to said switching means; an encoder generating a reconstructed baseband composite video signal SvS' representing the 8. System according to claim 7, characterized in that it includes coding means.

9. The second video signal SVS is composed of alternating odd and even fields. an interlaced video signal consisting of a sequence of said second video signals SvS; at least one for storing subsequent incoming fields in circular or round-tropin format. The memory also includes three areas, and the memory is stored in the at least three areas. The switching signal SS is fixed to each one of several states of the switching signal. the switching signal SS, which is allocated to the is fixedly assigned to another state of the switching signal. The system of claim 1.

10. A video signal having a luma signal component Y and a pair of color difference signals U(ad) and V The source of the number and a source of a clock signal; coupled to receive the video signal components Y, U and V; and coupled to receive the video signal components Y, U and V; YUOゝ　0も YUYUYUYVY 1) 0 Asahi 2’ O’ 3’ O’ 4’ 0’5” O” 6” O” 7 ”　0’　”8”　1’　Y9’U],...(Subscript 0.1.2,... ・denotes a sample number) and synchronizes with the clock signal. The resulting 6-bit digital samples (samples are generated at clock frequency CK) sampling means for generating a stream of coupled to receive the 6-bit samples at the frequency of the CK; 4 bits occurring at a frequency of N (N is an integer greater than or equal to 1) means for generating a stream of digital nibbles and said 6-bit Y component sample; Generates a 6-bit Y component sample occurring at frequency CK/2N in response to a pull. a first extraction means; in response to the 6-bit U and V component samples occurring at frequency CK/8N. A second sampler generates an alternating sequence of 6-bit U and V component samples. 6 bits coupled to said first extraction means and occurring at a frequency CK/2N. 3-bit Y-component sample generated at frequency CK/N. above each of the 6-bit Y component samples occurring at a frequency of pull, CK/2N. An alternating 3-bit sample generated at the frequency CK/N, including the upper 3 bits and the lower 3 bits. means for generating a sequence of files; The 3-bit Y component sample and the 6-bit U generated at a frequency of CK/8N and the component samples of ■, and the U and V samples are a 4-bit nibble sequence; , mutually exclusive single bits of 6-bit U or V samples each each group of six consecutive concatenated samples. U or V in which predetermined samples among the 3-bit Y samples between loops are concatenated. bits, and includes memory means for storing said 4-bit nibbles. A television (TV) signal processing system characterized by:

11. a source of switching signals in the form of 2-bit digital samples; to receive the 4-bit nibble and the 2-bit switching signal sample. and in response to a clock signal of CK/N, the switching of the two bits is performed. each single bit of the signal sample and said predetermined sample among the 3-bit Y samples; 11. The system of claim 10, including means for coupling.

+2. a source of a 1-bit switching signal generated in synchronization with the clock signal; coupled to receive the 4-bit nibble and the 1-bit switching signal; , and in response to a clock signal of CK/N, the 1-bit switching signal sample to the plurality of 3-bit Y samples. 11. The system of claim 10, further comprising:

international search report +1'+j size+-low^””””’=　PCT/US　8810301B International Investigation report PCT/LI588103018

Claims (13)

[Claims] 1. A source (22) of a first video signal FVS and a source (22) of a second video signal SVS. 4), coupled to receive the second video signal, and a clock signal FCS; m(m is a positive integer greater than 1) bits of the digital second video signal. step by step, An n (n is a positive integer greater than 1) bit data generated in synchronization with the clock signal. Source of switching signal SS in the form of a stream of digital switching signal samples (6 0,508) and the sampled second video signal and the sampled switching signal; a synthesized digital signal consisting of samples generated synchronously with the clock signal. means (500) for forming a tall signal; In response to the clock signal and in synchronization with the clock signal, the synthesized sample a memory that stores the pull signal and generates the synthesized sample signal at its output terminal; means (900); coupled to receive the synthesized sample signal and responsive to the clock signal; means (702, 71) for reconstructing the second video signal and the switching signal; 2) and a source (604) of a context code signal CCS and said reconstructed switching signal; (hereinafter referred to as SS'), the context code signal CCS , and generates a high-speed switching signal FSS in synchronization with the clock signal. Coding means (800); The first video signal FVS and the reconstructed second video signal (hereinafter referred to as SVS') and responsive to said fast switching signal FSS. , the fast switching signal FSS is in a first state and a second state, respectively. At this time, the first video signal FVS and the reconstructed second video signal are connected to the output terminal. switching means (80) for generating a video signal SVS'; processing system. 2. The second video signal SVS is an image consisting of an odd field and an even field. an interlaced video signal, wherein the odd numbered features of the second video signal SVS are interlaced; Two areas are provided in memory to store the field and the even field, respectively. The switching signal SS stored in the two regions of the memory is activated by the switching means. the odd field and the even field of the second video signal supplied to the output terminal; the switching signals respectively representing a field and stored in the remaining area of the memory; SS of said switching means from said memory of said reconstructed second video signal; A system as claimed in claim 1, characterized in that it represents no passage to the output terminal. 3. The second video signal SVS may include a luma signal Y and a pair of color difference signals U and V. and the means including the sampling means is configured to detect the second video signal SV. coupled to receive S, Y0, U0, Y1, U0, Y2, U0, Y3, U 0, Y4, V0, Y5, V0, Y6, Y7, V0, Y8, U1 (subscript 0, 1, 2 ...represents the sample number, where the sample occurs at the clock frequency FCS). means for generating a stream of 6-bit digital samples having sequences 3. The system of claim 2, comprising: 4. The means including the sampling means further includes the 6-bit second video signal. FCS/N (where N is the sample reduction or is an integer representing the sampling rate) and has the form: claim characterized in that it includes means for generating a stream of video signal nibbles. The system according to item 3. ▲Contains mathematical formulas, chemical formulas, tables, etc.▼ ・Subscripts 0, N, 2N... represent sample numbers, ・The numbers 0, 1, 2... in parentheses represent the pit numbers of the 6-bit sample, ・X is a blank space for one of the 2 bits of the 2-bit switching signal SS. represents the 5. The switching signal is a 2-bit signal, and the combining means is a 4-bit signal. 2 video signal nibbles and said 2 bit switching signal SS coupled and responsive to a clock signal with a frequency of FSC/N, and with a frequency of FCS/N. is characterized in that it generates a sequence of 4-bit composite signal nibbles of the form: 5. The system of claim 4, wherein: ▲Contains mathematical formulas, chemical formulas, tables, etc.▼ ・Here, subscripts 0, N, 2N... represent sample numbers, - Numbers 0, 1, 2, etc. in parentheses represent bit numbers. 6. The memory means includes rows and columns of 4-bit storage cells or storage locations. The system according to claim 5, characterized in that: 7. A reconstruction means generates the 4-bit composite signal sample generated in synchronization with the clock signal. receive the sample, reconstructed 6-bit luma signal Y', reconstructed 6-bit luma signal Y', A pair of color difference signals U' and V' and a reconstructed 2-bit switching signal SS 7. The system according to claim 6, wherein the system generates . 8. The reconstruction means further includes the reconstructed 6-bit luma signal and color difference signal Y' , U' and V', and is responsive to said clock signal and configured to reconfigure and means for generating analog luma and color difference signals. 8. The system according to claim 7. 9. The reconstruction means further receives the reconstructed analog luma signal and color difference signal. the second video signal being coupled to the switching means; An encoder that generates a reconstructed baseband composite video signal SVS' representing 9. A system as claimed in claim 8, including means for downloading. 10. Is the second video signal SVS alternating odd and even fields? an interlaced video signal consisting of said second video signal SVS; for storing consecutive incoming fields in a circular or round-robin format. In each case, the memory includes three areas, and the memory is stored in the at least three areas. The switching signal SS is fixed to each one of several states of the switching signal. the switching signal S which is permanently assigned and stored elsewhere in the memory; S is fixedly assigned to another state of the switching signal. 2. The system of claim 1. 11. a video signal source having a luma signal component Y and a pair of color difference signal components U and V; , a clock signal source; coupled to receive the video signal components Y, U, and V; the clock; Y0, U0, Y1, U0, Y 2, U0, Y3, U0, Y4, V0, Y5, V0, Y6, V0, Y7, V0, Y 8, U1, Y9, U1... (Subscripts 0, 1, 2... represent sample numbers, The sample is a 6-bit digital signal with a sequence of sampling means for generating a stream of samples; coupled to receive the 6-bit samples at the frequency of the CK; 4-bit digit occurring at a frequency of N (N is an integer greater than or equal to 1) and means for generating a stream of 4-bit nibbles such that said 4-bit nibbles are A television signal processing system that takes the form ▲Contains mathematical formulas, chemical formulas, tables, etc.▼ ・Subscripts 0, N, 2N... represent sample numbers, ・The numbers 0, 1, 2... in parentheses represent the bit numbers of the 6-bit sample, ・X represents a blank space, - The memory means has a 4-bit memory cell, and responds to the clock signal to read the CK signal. The 4-bit nibble is stored at a frequency of /N. 12. A stream of 2-bit digital samples generated in synchronization with the clock signal. stream format switching signal source, and the switching of the 4-bit nibble and the 2-bit coupled to receive switching signal samples and responsive to a CK/N clock signal. , of 4-bit composite signal nibbles occurring at a frequency of said CK/N and having the form: 12. The system of claim 11, further comprising means for generating a sequence. Tem. ▲Contains mathematical formulas, chemical formulas, tables, etc.▼ ・Subscripts 0, N, 2N... represent sample numbers, - Numbers 0, 1, 2, etc. in parentheses represent bit numbers. 13. a 1-bit switching signal source generated in synchronization with the clock signal; coupled to receive the 4-bit nibble and the 1-bit switching signal; , in response to a clock signal of CK/N, occurring at a frequency of said CK/N, and having the following form: further comprising means for generating a sequence of 4-bit composite signal nibbles to take. 12. The system of claim 11, wherein: ▲Contains mathematical formulas, chemical formulas, tables, etc.▼ ・Subscripts 0, N, 2N... represent sample numbers, ・Numbers 0.1, 2... in parentheses represent the number of bits, ・Y is the switching of the 1 bit mentioned above. represents the space set aside for traffic signals.