JPH033014Y2 - - Google Patents

Description

[Detailed description of the invention] The invention relates to a television satellite broadcast receiver.
More specifically, the present invention relates to a television satellite broadcasting receiver equipped with a circuit for muting audio data when the audio data mode is changed.

(Prior Art) Basic decoding of a PCM audio signal after deinterleaving in a television satellite broadcasting receiver is performed by the configuration shown in FIG. That is, in FIG. 1, reference numeral 1 denotes a storage device for deinterleaving, which stores, for example, two frames worth of received codes. The received code de-interleaved in the storage device 1 is BCH (Bose-Chaudhuri-
Hocquenghem) (63, 56) is supplied to the single error correction/double error detection code decoding circuit 2 to correct the single error, and the audio data in the received code with the single error corrected is sent to the decompression circuit 3. The signal is supplied, expanded by range bits, converted to parallel audio data, and supplied as one input of the multiplexer 5. At the same time, the audio data in the received code is supplied to the serial/parallel converter 4 and converted to parallel audio data. Moreover, the parallel audio data is supplied as the other input of the multiplexer 5, so that the multiplexer 5 selects one input. The output of the multiplexer 5 is supplied to a latch circuit 6 to be latched, and the latch output is supplied to a digital/analog converter 7 to be converted into an analog signal.

On the other hand, the mode bits in the received control bits
CB ₀ is supplied to majority decision circuit 8 to decide whether the transmitted audio data is in A mode or B mode, and the output of majority decision circuit 8 is supplied to latch circuit 9 and latched. The output is supplied to the multiplexer 5 as a selection signal, and one input of the multiplexer 5 is selected and output.

However, in the past, as described above, the mode bit _CB0 among the control bits is determined by the majority decision circuit 8, for example, when there are many low potential mode bits _CB0 among the 15 bits, it is determined to be A mode, and when there are many high potential mode bits _CB0 . is determined to be the B mode, and the multiplexer 5 is controlled. Therefore, when the mode of audio data changes during reception, the multiplexer 5 is switched after a delay due to the majority decision operation of the majority decision circuit 8. As a result, during the delay due to the majority decision operation after the mode has changed, decoding is performed with the mode reversed for the audio data. For example, for A-mode audio data, the output of the serial/parallel converter 4 is Even though the audio data is selected in step 5 and the audio data is in mode A, no expansion is performed using the range bits, and even though the output of the expansion circuit 3 is selected in multiplexer 5 for the audio data in mode B, it is audio data in mode B. However, there was a problem in which unexpected shock noise was generated due to decompression operations being carried out regardless of the situation.

(Purpose of the invention) The present invention has been made in view of the above, and aims to provide a satellite broadcasting receiver that solves the above problems by muting audio data over a period of a predetermined number of frames when changing modes. purpose.

(Structure of the invention) The present invention is equipped with a majority decision circuit that considers received mode bits of a predetermined number of frames as one block, and determines the mode of received audio data by a majority decision on the polarity of the mode bits in one block. In a satellite broadcasting receiver to which audio data having two modes are input, the polarity changes occur in two or more mode bits consecutively within a block that is being judged by the majority decision circuit, and the majority decision circuit in that block is making a majority decision. When the judgment result is the same as the majority judgment result of the immediately preceding block, the period from the next frame in which the polarity change occurs until the majority judgment result of the next block is obtained,
The received audio data is muted, and the polarity changes occur in two or more consecutive mode bits within the block under majority decision by the majority decision circuit, and the majority decision result of that block is the same as the majority decision of the immediately preceding block. The present invention is characterized by comprising a muting means for muting the received audio data during a period from the next frame in which the polarity change occurs until the result of the majority decision in that block is output when the result is different.

The present invention will be explained below with reference to examples.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 2, components with the same reference numerals as in FIG. 1 are the same as those in FIG.
The explanation will be omitted.

FCK is a frame clock pulse, which is supplied to the majority decision circuit 8 as a reference pulse.

LTCK is a latch pulse, and one pulse is generated for every majority decision frame number, which is "15" in this embodiment. The latch pulse LTCK is supplied to the latch circuit 9.

In this embodiment, the latch output CBD ₀ of the latch circuit 9 and the mode bit CB ₀ are connected to the exclusive OR circuit 1.
The output CMB ₁ of the exclusive OR circuit 10 is supplied to the latch circuit 11 and latched by the frame clock pulse FCK.
CMB ₂ and the output CMB ₁ of the exclusive OR circuit 11 are supplied to an AND gate circuit 12. The output CMB ₃ of the AND gate circuit 12 is supplied to the latch circuits 13 and 14, and the output of the AND gate circuit 12 is
CMB ₃ is latched by the frame clock pulse FCK in the latch circuit 13, and is connected to the AND gate circuit 1.
The output CMB ₃ of CMB 2 is latched by a latch circuit 14 with a pulse obtained by inverting the frame clock pulse FCK by an inverter 15.

Output ₄ of latch circuit 13 is latch circuit 1
The Q output ₆ of the latch circuit 16 and the output ₅ of the latch circuit 14 are supplied to the AND gate circuit 17, and the output of the AND gate circuit 17 is
The HMM is supplied as a clear signal to the latch circuit 6, and during the period when the output of the AND gate circuit 17 is at a low potential, the latch output of the latch circuit 17 is set in a clear state to perform a mute operation.

Here, the latch circuits 13, 14 and 16 and the inverter 15 are provided in the AND gate circuit 17.
The purpose is to obtain an output through the latch circuit 14 and determine the mute start timing.
This is to obtain an output ₆ from the latch circuit 16 from the CMB ₅ , which determines the end time of the mute.

(Operation of the invention) The operation of an embodiment of the invention configured as described above will be explained.

The clock pulse FCK is as shown in FIG. 3a, and the latch pulse LTCK is as shown in FIG. 3b. The received mode bit _CB0 is as shown in FIG. 3c, for example, and is indicated as "0" and "1" in FIG. 3a.

Therefore, the output of the majority decision circuit 8 is set as a latch pulse.
The output _CBD0 of the latch circuit 9 latched by LTCK is as shown in FIG. 3d. This is because the majority decision circuit 8 determines the high potential or low potential of the output based on the majority decision of mode bits _CB0 for 15 frames.

The output CBD ₀ of the latch circuit 9 shown in FIG. 3d and the mode bit CB ₀ shown in FIG. 3c are supplied to an exclusive OR circuit 10. Therefore, the output CMB ₁ of the exclusive OR 10 becomes as shown in FIG. 3e.
In FIG. 3e, A is the output when mode bit _CB0 is erroneous by one bit. Latch circuit 1
The output CMB ₂ of the AND gate circuit 12 is as shown in FIG. 3f, and the output CMB ₃ of the AND gate circuit 12 is as shown in FIG. 3g.

In addition, the outputs ₄ of the latch circuits 13 and 14,
The CMB ₅ becomes as shown in FIG. 3h and i, the output ₆ of the latch circuit 16 becomes as shown in FIG. 3j, and the output of the AND gate circuit 17 becomes as shown in FIG. 3k.

While the output of the AND gate circuit 17 is at a low potential, the output of the latch circuit 6 is cleared and the inputs of the digital/analog converter 7 are all zero.
A mutating action is performed. In this embodiment, as shown in FIG. 3A, in the majority decision circuit 8, the latter mode bit CB ₀ and the 7th bit are in the B mode. In this case, muting is applied for a period of 22 frame clock pulses from the next frame clock when changing from A mode to B mode.

Furthermore, instead of the case where the second half mode bits, 7 bits, are in B mode, when 6 bits to 2 bits are in B mode, 22
The muting operation is performed over the period of 21 to 16 frame clock pulses instead of the period of the frame clock pulse.

Therefore, during the delay of the majority decision operation, the audio data is decoded with the mode reversed, but during the delay, the audio data is muted, so that the generation of shock noise is suppressed.

(Effect of the invention) As explained above, according to the invention, two or more mode bits successively change in polarity within a block under majority decision in the majority decision circuit, and a new mode is not established in the block. In this case, since the received audio data is muted during the period from the next frame when the polarity change occurs until the majority decision result of the next block is output, there is a delay in the majority decision operation in the majority decision circuit. Although the opposite mode of processing is performed on the audio data in between, shock noise no longer occurs.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional decoding system in a satellite broadcast receiver. FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 3 is a waveform diagram for explaining the operation of an embodiment of the present invention. 1... Storage device, 2... BCH (63, 56) single error correction/double error detection code decoding circuit, 3... Expansion circuit, 4... Serial/parallel converter, 5...
...Multiplexer, 6, 9, 11, 13, 14 and 16...Latch circuit, 7...Digital/analog converter, 8...Majority decision circuit, 10...Exclusive OR circuit, 12 and 17...And gate circuit.

Claims (1)

[Scope of utility model registration request] The audio data has two modes distinguished by the mode bits, and includes a majority decision circuit that considers received mode bits of a predetermined number of frames as one block and determines the mode of the received audio data based on a majority decision of the polarity of the mode bits in one block. In a satellite broadcasting receiver to which the majority decision circuit is making a majority decision, polarity changes occur in two or more consecutive mode bits within the block being decided by the majority decision circuit, and the majority decision result in that block is different from that of the immediately preceding block. When the result is the same as the majority decision result, the received audio data is muted during the period from the next frame where the polarity change occurs until the majority decision result in the next block is obtained, and the majority decision circuit is in the process of making the majority decision. When a change in polarity occurs in two or more consecutive mode bits in a block and the majority decision result of that block is different from the majority decision result of the immediately preceding block, the polarity change occurs from the next frame where the polarity change occurs. 1. A satellite broadcasting receiver comprising muting means for muting received audio data until a majority decision result in a block is obtained.