JPH11298335A - Error correction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output a correction bit string in a little time even in the case that an error is over many bits. SOLUTION: This error correction circuit for correcting the error of (n, k) codes received through a radio communication path is provided with a detection means 22 for detecting the signal level decline part of reception signals corresponding to the information bits (k) of the (n, k) codes, a specifying means 23 for specifying the position of the signal level decline part, a correction means 24 for correcting the specified position by considering the processing delay and processing contents of a reception system signal processing part and a correction means for correcting the error by bit-inverting the specified bit of the information bits (k) included in the position corrected by the correction means 24. Bit inversion is performed to a part of the information bits (k) of the (n, k) codes as an object and the error is corrected. Thus, the processing time of error correction is shortened compared to the one whose object is all of the information bits (k) like a conventional technique.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an error correction circuit, and more particularly to an error correction circuit for correcting a burst error with a simple circuit configuration.

[0002]

2. Description of the Related Art A digital signal is a signal in which information is represented by discrete (discrete) numbers, typically 0 and 1. This signal has the advantage of being more resistant to noise and interference than analog signals. However, even in the case of strong noise or interference, it is possible to avoid erroneously distinguishing 0 from 1 and 1 from 0. Therefore, it is indispensable to use a code error detection / correction technique based on coding theory.

FIG. 5 is a model diagram of a digital communication system in coding theory. Note that "communication" refers to sending information or recording information to a partner, sending information to carry information to a remote place, and recording means leaving information assuming reading at a later date ( Later) the transfer of information to time, and both are the same in "carrying information", so they are not distinguished in this specification.

[0004] Code theory deals with digitized information. The information to be transmitted is various such as digitalized audio and video signals or digital data from a computer. If the source of such information and the part that digitizes it are referred to as an information source, the digitized information uses two types of codes (numbers) 0 and 1. Are often represented as bit strings.
In the following description, it is assumed that information is represented by a bit string. That is, the information source of the illustrated model generates a bit sequence of 0 and 1 (information bit sequence) as information to be transmitted. The encoder handles the information bit string by dividing it into blocks of k [bits]. Report this block (massag
e). Hereinafter, the report is i = (i ₁ , i ₂ ,..., I _k )
Will be represented by

[0005] An encoder is a bit string w = (x ₁ , x ₂ ,...) Of n [bits] (n> k) corresponding to the message i.
, X _n ). That is, m = nk in the encoder
An extra bit (redundant bit) of [bit] is added. n is a code bit (code length), k is an information bit, and the code of the code bit n and the information bit k is an (n, k) code. w is a code word, and an operation of creating w corresponding to i is called encoding. When a problem specific notification i, refers to the channel code words fed into (channel) and the transmission word, the actual transmission and recording medium, for each bit x _i of transmission word, for example, 0 In the case, there is no pulse, and in the case of 1, there is a pulse. The signal waveform is sent out, but a specific waveform is not described here.

[0006] channel is the transmission word w is input, the received word y = a n [bit] _{(y 1, y 2, ···} , y n) and outputs a. If there is no influence of transmission / recording medium noise, w =
Although it is y, normally 0 or 1 of each bit in the transmission word is received differently with a certain probability due to noise or the like. This is called an error, and this state is represented by y = w + e on the assumption that an error has been added to each bit in the communication path. Here, the error of each bit is e _i, and e is a bit string e = (e ₁ , e ₂ ,.
, E _n ).

The decoder estimates which codeword has been transmitted based on y, and obtains an estimated value of the transmitted word w or an estimated value of the message i. Errors occurring in the communication channel are classified into random error, random error, burst error, and byte error. In particular, mobile phones, car phones, PHS
Mobile communications such as personal handy-phone systems are susceptible to masking phenomena due to strong noise and multipath due to building reflections, and burst errors (partially concentrated errors) occur frequently. Therefore, some countermeasures are required, but one of the conditions of the terminal used for the mobile communication is that it is small and lightweight, so that a large-scale error detection / correction technique cannot be used.

[0008] A cyclic code (cyclic c) which is a kind of linear code
ode) is a technique that is often used in the above applications because an encoder and a decoder can be made using an LSFR (linear feedback shift register), and the circuit scale is reduced.

The cyclic code has one generator polynomial G (x) peculiar to the code, and the calculation of a syndrome (an m-dimensional vector determined only by an error pattern e without being affected by a transmission word w) is performed by G One LSFR with connection (x)
Can be done. That is, it is only necessary to configure a polynomial division circuit by G (x). The result obtained by putting the receiving polynomial Y (x) into this division circuit is that Y (x) is G (x)
Y (x) = Q (x) G (x) + S (x) where the polynomial is S (x). In general, it is a practice of writing the part that focuses too much on mod, so that if written again, S (x) = Y (x) mod G (x). This is called the syndrome polynomial
ial). If the coefficient of G (x) is m-th order, the remainder S
(X) is a polynomial of degree m-1 or less. Code polynomial W
Since (x) is divisible by the generator polynomial G (x), S (x) = (W (x) + E (x)) mod G (x) = E (x) mod G (x). S (x) is determined only by the error polynomial E (x) regardless of the generator polynomial.

When only error detection is performed, as shown in FIG. 6, after calculating a syndrome polynomial S (x) (S1), it is determined whether or not the value of S (x) is 0 (S2). do it. This method is called CRC (cyclic redundancy check)
k). By the way, if retransmission (retransmission) of information is requested when an error is detected, the data transfer rate is substantially reduced. Therefore, it is desirable to perform correction at the same time as detection.

As a conventional error correction technique, the following is known. Now, in the (n, k) code, the syndrome polynomial S (x) of the reception polynomial Y (x)
Is not 0. That is, this is a case where the n or k bit string contains at least one bit error. Here, in order to simplify the explanation, k (information bit) is assumed to be 4 bits, and the original value of k is “000”.
It is assumed that the value is set to "0" and changed to "1111" (all bit errors) due to an error. A known prior art is to repeat error detection while sequentially performing bit inversion of k, and its flowchart is shown in FIG.

In the illustrated flow, j and f are variables for designating an inverted bit. When you start the flow,
First, initial values (j = 1, f = 0) are set to j and f, respectively (S11), and then the bits _ij to _if are inverted (S12). At this stage, j = 1, f =
0, and thus it will be reversed only i ₁ bit.
Next, error detection is performed using the inverted bit string (“0111”) (S13). Since the original value is “0000” as described above, the result of step S13 is Y.
ES (error). Next, it is determined whether or not the value of j + f matches k (the number of information bits to be inspected) (S14).
Is incremented by one (S15), and the process of step S12 and subsequent steps is repeated, that is, 1 bit from the beginning of k bits
The process of performing error detection while sequentially inverting each bit is repeated. As described above, since the error is all bits, even if such processing is performed, the result of step S13 remains YES (error exists). Here, since the result of step S14 after performing the inversion and error detection processing on the last bit of k bits is YES, next, f
It is determined whether or not the value obtained by adding 1 to k is equal to k (f + 1 = k) (S17). This determination checks the completion of inversion of all bits.

If no match is found in step S17, since the inversion of all bits has not been completed, an initial value (1) is set in j and f is increased by one (S1).
8) After that, step S12 and subsequent steps are repeated. That is, at this stage, i = 1 and f = 1, and step S
Since step 12 and subsequent steps are repeated, error detection is performed after inverting the two bits i ₁ and i _2. Even in such a case, the result of step S13 is still YES (error is present). . Results become to NO (the no error) Step S13, when it becomes i = 1, j = 3, i.e., is when performing the all-bit inversion from i ₁ to i _4, the bit inversion Error detection after operation (S1
Since no error is detected for the first time in 3), the inverted bit sequence is output as a corrected bit sequence (S16).

If the code string n contains an error, the result of step S13 remains YES (with error) even if i = 1 and j = 3. In this case, i + j
= K is determined, and another error correction processing is performed--the simplest method is a request for retransmission of the (n, k) code ---.

[0015]

The above prior arts are
For the entire (n, k) code, the first bit is inverted one bit at a time, the second bit is inverted two bits at a time,
... Finally, error detection is performed each time while inverting all bits, and the bit string when “no error” is output as a corrected (corrected or modified) bit string. This is useful in that error detection and correction can be performed at the same time --- it does not cause a substantial reduction in data transmission rate because it does not request retransmission-but, for example,
When an error spans multiple bits, there is a problem that it takes a considerably long time (overhead) to output a corrected bit string.

That is, in the above example, i =
When there is no error at the stage of 1, j = 0 (NO determination in step S13), a corrected bit string can be output by one process and the minimum overhead is required. This is because it cannot be determined that there is no error until i = 1 and j = 3, and at least step S18 must be executed three times. The actual information bit k is not a small value such as 4 bits but 100 This is because several tens of bits or more, and therefore, the execution of step S18 is performed hundreds or more times or more, which is a considerable overhead.

An object of the present invention is to provide an error correction circuit capable of outputting a correction bit sequence in a short time even when an error covers a large number of bits.

[0018]

The invention according to claim 1 is
In an error correction circuit for correcting an error of an (n, k) code received via a wireless communication path, a detection for detecting a signal level drop portion of a received signal corresponding to the information bit k of the (n, k) code Means, specifying means for specifying the position of the signal level lowering portion, correcting means for correcting the specified position in consideration of the processing delay and processing content of a reception signal processing unit, and correction means for correcting the specified position by the correcting means. And correcting means for correcting the error by inverting a specific bit of the information bit k included in the position.

According to a second aspect of the present invention, in the first aspect, the (n, k) code is a communication channel for mobile communication. According to a third aspect of the present invention, in an error correction circuit for correcting an error of a (n, k) code received via a wireless communication channel, a received signal corresponding to a code bit n of the (n, k) code is generated. Detecting means for detecting the signal level lowering portion, specifying means for specifying the position of the signal level lowering portion, and correcting means for correcting the specified position in consideration of the processing delay and the processing content of the receiving signal processing section And inverts a specific bit of the code bit n included in the position corrected by the correction means, and sequentially inverts the information bit k of the (n, k) code every time the inversion is performed. Correction means for correcting the error.

According to a fourth aspect of the present invention, in the first or third aspect of the invention, the specifying means preferentially specifies a position of the signal level lowering portion where the degree of reduction is large. . According to a fifth aspect of the present invention, in the first or the third aspect of the present invention, when an error is not corrected even though all bit inversions corresponding to the position of the signal level lowering portion are performed, It is characterized in that bits of a portion other than the position are included in the inversion target. The invention according to claim 6 is claim 1 or claim 3.
In the invention according to the above, despite performing all the bit inversion corresponding to the position of the signal level lowering portion,
If the error is not corrected, one or several bits before and after the position are included in the inversion target.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings, taking a PHS as one of mobile communication terminals as an example. In FIG. 1, 10 is a receiving circuit,
Reference numeral 11 denotes a transmission circuit, and reference numeral 12 denotes a duplex circuit for sharing the antenna 13 between the reception circuit 10 and the transmission circuit 11. The present invention relates to a technology for detecting and correcting an error in a received signal, and since the operation of the PHS itself is not directly related, the description of the configuration and operation of the transmission circuit 11 is omitted.

Hereinafter, the configuration of the receiving circuit 10 will be described.
The reception circuit 10 generally includes a reception unit 14, a demodulation unit 15, a synchronization unit 16, an error detection unit 17, a bit operation unit 18, a frame control unit 19, an audio output unit 20, a speaker 21, and a level detection unit 22. The function of each unit is as follows.

(1) Receiver 14 The high frequency (1.9 GHz) reception burst signal 30 fetched from the antenna 13 is converted into a low frequency signal (intermediate frequency signal 31 for convenience) which is easily processed by an internal circuit. In addition to the output, the power level or voltage level of the intermediate frequency signal 31 (or the received burst signal 30) or a signal correlated with these levels (level signal 32 for convenience) is output. (2) Demodulation unit 15 This performs signal demodulation operation corresponding to the PHS modulation method (π / 4 shift QPSK: quaternary phase modulation). The demodulated signal is referred to as a demodulated signal 33 for convenience. (3) Synchronizing section 16 This section performs signal processing such as frame synchronization and descrambling. The processed signal is referred to as a processed received signal 34.

(4) Error Detecting Unit 17 The error detecting unit 17 detects an error of a signal by the CRC, and there are two types of signals to be detected. That is, error detection is performed for each of the post-processing reception signal 34 and the bit inversion signal 35 (described later). From the error detection unit 17, "error exists"
Alternatively, a detection result signal 36 indicating any state of “no error” is output. (5) Level detection section 22 (see FIG. 3) Based on the level signal 32 from the reception section 14, a level drop portion (generally a spike) in the reception burst signal 30 or the intermediate frequency signal 31 is detected, and the drop is detected. It outputs a signal indicating the position of the portion (for convenience, the position specifying signal 37). The detection of the level lowering portion is to compare the signal level indicated by the level signal 32 with a certain threshold value, and determine a portion below the threshold value as a level lowering portion. The value is the average value of the signal level on the time axis --- for example, the average value of the signal levels of the reception burst signal 30 up to several times before including the previous reception burst signal 30 or the intermediate frequency corresponding to these burst signals It is desirable to use a variable threshold value that fluctuates in accordance with the average value of the signal level of the signal 31 --- the level of reduction from the average value is also variable. It is desirable to do. This is because the magnitude of the threshold value is set according to the state of the communication channel, so that it is possible to avoid inappropriate detection of a portion where the level is lowered.

(6) Bit operation unit 18 This is to generate a bit inversion signal 35 to be given to the error detection unit 17. The same bit inversion signal is generated in the related art at the beginning, but in the present embodiment,
It differs from the prior art in that only a part of the processed received signal 34 corresponding to one received burst signal 30 (the whole in the prior art) is subjected to bit inversion. Timing generator 23
Is to determine which part of the processed reception signal 34 (or the immediately preceding bit inversion signal 35) is to be subjected to bit inversion based on the position specifying signal 37 from the level detection unit 22. The bit inversion unit 24 performs bit inversion (1 to 0, 0 to 0) on the determined portion in the order described below.
To 1), and outputs the result to the error detection unit 17 as a bit inversion signal 35. When the detection result signal 36 of the error detection unit 17 is "no error", the bit inversion signal at that time is output. 36 (however, the bit inversion signal 3
If the received signal is not generated, the post-processing received signal 34) is output to the next-stage circuit (the frame control unit 19) as the corrected received signal 38.

(7) Frame control section 19 This section performs necessary information reproduction processing such as frame rearrangement of a signal after error correction (corrected reception signal 37). (8) Audio output unit 20 and speaker 21 The reproduced audio information is amplified in voltage and power and output as loudspeakers.

FIG. 2 is a flowchart showing the entire processing centering on the bit inversion operation. This flow shows a group of processed reception signals 34 corresponding to one reception burst signal 30, in other words, the processing of the same signal 34. Assuming that the sign bit is n and the information bit is k, it is activated in response to an input event of a group of (n, k) codes. That is, when an input event occurs (S21), first, the (n, k) code is taken into the error detection unit 17 to detect the presence or absence of an error (S2).
1, S22) If there is no error, the information bit value k of the (n, k) code is output to the next stage circuit (frame control unit 19) via the bit operation unit 18 (without bit inversion). On the other hand, if there is an error, the following processing is executed.

First, it is determined whether or not the level lowering portion is detected by the level detector 22 (S23). If it is not detected (NO in step S23), a separate error correction process suitable for the cause is executed (S2) because the cause is other than a burst error (for example, a random error or a byte error).
8). Now, it is assumed that the level detecting section 22 detects a level lowering portion (see symbols A and B) as shown in FIG. The positions in the (n, k) code of interest are codes C, D
Indicated by However, the same positions C and D are positions in the received burst signal 30 or the intermediate frequency signal 31, and are signals after processing such as demodulation, frame synchronization, descrambling (processed reception signal 34) and bit inversion signals. Since the position at 35 does not correspond one-to-one, position matching (positioning) is necessary. This can be achieved by calculating an appropriate delay time in consideration of the time required for the above processing and the content of the processing, and adding the delay time to the positions C and D. FIG.
The figure shown at the bottom of the figure schematically shows the (n, k) code after alignment.

In the (n, k) code after the alignment,
Two ranges E, schematically connected by dashed lines to positions C and D,
F is a target range of the bit inversion. Here, the range E
Is assumed to be four bits of bits 45 to 48, and the range F is two bits of bits 121 and 122. Of course, these bit numbers and bit numbers are for convenience of explanation.

As will be apparent from the following description, in the present embodiment, only the bits in these designated ranges are inverted. That is, in the bit inversion processing (S24) in the flow of FIG. 2, first, as the first stage, inversion processing is performed for each bit from the top of all bits in the specified range (total 6 bits of bits 45 to 48 and bits 121 and 122). Then, each time the error is output to the error detection unit 17, the presence or absence of an error is detected (S26). If the error continues, as a second step, for all bits in the specified range, two bits from the beginning are inverted, and the above processing is repeated.
If the error continues, the third step is to invert three bits from the beginning of all bits in the specified range and repeat the above processing. Further, when the error continues, the inversion process of 4 bits from the beginning, 5 bits from the beginning, and 6 bits from the beginning (ie, all bits) is sequentially performed, and the above process is repeated.

After the inversion of all bits, if the number of all bits in the designated range is N, the number of inversions reaches 2 ^N (YES in step S25). , If the error persists, due to factors other than burst errors (for example, random errors and byte errors),
A separate error correction process suitable for the cause is executed (S
28).

FIG. 4 is a bit inversion transition state diagram specifically showing the above processing. In this figure, it is assumed that the bit string (original bit string) before inversion is “101000” and the error bits are bits 45, 47, and 48. #
1 to # 64 are the number of inversion processes. In this example, the maximum number of bits is 6 because the number of bits in the specified range is ⁶ .
That is, it is 64.

Now, if the bit value subjected to the inversion operation is underlined, # 1 to # 6 are inverted one bit at a time from the beginning, and # 7 to # 21 are inverted two bits at a time from the beginning. Let me. In the last # 64, 2 ^N bits, that is, all bits are inverted.

As described above, the error bit is bit4
Since the bits are 5, 47 and 48, up to # 26 where these bits are inverted (# 1 to # 25), the results of error detection are all "errors". Then, after execution of # 26, “no error” occurs, and the bit string (“000100”) at that time is output to the next-stage circuit (frame control unit 19) as the corrected reception signal 38.

As is clear from the above description, in the present embodiment, the bit inversion operation is performed only in a specific range (6 bits of bits 45 to 48 and bits 121 and 122 in the example) of the (n, k) code. Therefore, as compared with the related art in which all of the information bits k are to be inverted, the waiting time (overhead) until outputting the corrected reception signal 38 (overhead)
Can be greatly reduced. The embodiment of the present invention is not limited to the above-described example. For example, various modifications as listed below are conceivable.

A. First Modification The bit inversion in the above embodiment is a signal of a communication channel (TCH) in a PHS. This is preferable because a higher-speed correction process at the time of communication or data transfer can be realized, and in particular, a substantial reduction in data transfer speed is not caused. b. Second Modification n of (n, k) Code, for example, CRC of CRC Correction Code
As a countermeasure when an error occurs in the CRC section, a means for detecting a signal level lowering section of the CRC section is provided, and when the signal level lowering section of the CRC section is detected, a bit in a designated range of the CRC section is corrected once. Each time, the processing of the above embodiment is performed once. This makes it possible to cope with the error of the code bit n in addition to the error of the information bit k.
k) It can cope with any error of the code (burst error).

C. Third Modification In the above-described embodiment (or the second modification), the greater the degree of decrease in the signal level, the higher the probability of occurrence of an error. If the error is not corrected even after performing the inversion processing, the bit inversion processing is performed on the next largest part. In this case, since a portion having a high error occurrence probability is processed first, the overhead can be further reduced.

D. Fourth Modification In the above-described embodiment (or the second modification), if all the bits in the target range are not inverted without error, bits other than the target range are added to the inversion target.
In this way, since all bits of the (n, k) code are finally subjected to inversion, it is possible to cope with a large burst error. e. Fifth Modification In the above-described embodiment (or the second modification), if all the bits in the target range are not inverted without error, one or several bits before and after the target range are subjected to inversion. Add to In this way, the error due to the response delay of the level detector 22 can be eliminated, and the accuracy of error correction can be improved.

[0039]

According to the first aspect of the present invention, in an error correction circuit for correcting an error of an (n, k) code received via a wireless communication path, an information bit of the (n, k) code is corrected. detecting means for detecting a signal level lowering portion of the received signal corresponding to k; specifying means for specifying the position of the signal level lowering portion; (N, k), because the correction means includes a correction means for performing correction in consideration of the above, and a correction means for correcting an error by bit inverting a specific bit of the information bit k included in the position corrected by the correction means. An error can be corrected by performing bit inversion on a part of the information bits k of the code. Therefore, the processing time for error correction can be shortened and the overhead can be reduced, as compared with the conventional technique in which all information bits k are targeted.

According to the second aspect of the present invention, since the present invention is applied to a communication channel of mobile communication, it is possible to prevent a substantial decrease in transfer speed particularly in data communication. According to the third aspect of the present invention, (n,
k) an error correction circuit for correcting a code error, detecting means for detecting a signal level drop portion of the received signal corresponding to the code bit n of the (n, k) code, and specifying the position of the signal level drop portion Specifying means for performing correction, correcting the specified position in consideration of the processing delay and processing details of a reception-system signal processing unit, and specifying bits of the sign bit n included in the position corrected by the correction means. Is bit-inverted, and each time the inversion is performed, the (n,
k) correcting means for sequentially inverting the information bits k of the code to correct the error, so that errors of the code bit n of the (n, k) code can be dealt with, and the performance of error correction can be improved. Can be planned.

According to the fourth aspect of the present invention, since the position of the signal level lowering portion where the degree of reduction is large is specified preferentially, a portion where an error easily occurs can be processed first, and the overhead can be further reduced. . According to the invention according to claim 5, when an error is not corrected even though all the bits corresponding to the position of the signal level lowering portion have been inverted, the bits of the portion other than the position are set as an inversion target. Since it includes, it is possible to cope with a large burst error in a wide range. According to the invention according to claim 6, when an error is not corrected despite all the bit inversions corresponding to the position of the signal level lowered portion,
Since one or several bits before and after the position are included in the inversion target, an error due to a response delay of the level detection unit can be eliminated, and the accuracy of error correction can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment.

FIG. 2 is a flowchart of the embodiment.

FIG. 3 is a timing chart of the embodiment.

FIG. 4 is a bit inversion transition diagram of the embodiment.

FIG. 5 is a model diagram of a communication system.

FIG. 6 is a flowchart of error detection.

FIG. 7 is a flowchart of a conventional bit inversion.

[Explanation of symbols]

 22 Level detection unit (detection unit) 23 Timing generation unit (specification unit, correction unit) 24 Bit inversion unit (correction unit)

Claims (6)

[Claims] 1. The method of claim 1, wherein (n,
k) an error correction circuit for correcting a code error, a detecting means for detecting a signal level drop portion of a received signal corresponding to the information bit k of the (n, k) code, and specifying a position of the signal level drop portion A correcting unit that corrects the specified position in consideration of a processing delay and a processing content of a reception signal processing unit; and a specifying bit of the information bit k included in the position corrected by the correcting unit. An error correction circuit, comprising: correction means for correcting an error by bit inverting the error. 2. The error correction circuit according to claim 1, wherein said (n, k) code is a communication channel for mobile communication. 3. The method as claimed in claim 3, wherein (n,
k) an error correction circuit for correcting an error of the code, a detecting means for detecting a signal level lowering portion of the received signal corresponding to the code bit n of the (n, k) code, and specifying the position of the signal level lowering portion A correcting unit that corrects the specified position in consideration of a processing delay and a processing content of a reception-system signal processing unit; and a specific bit of the sign bit n included in the position corrected by the correcting unit. And a correcting unit for sequentially inverting the information bit k of the (n, k) code and correcting an error each time the inversion is performed. 4. The error correction circuit according to claim 1, wherein said specifying means preferentially specifies a position of said signal level lowering portion having a higher degree of reduction. 5. The error correction circuit according to claim 1, wherein, even though all bits are inverted corresponding to the position of the signal level lowering portion, the error is not corrected. An error correction circuit characterized in that bits of other parts are included in an inversion target. 6. The error correction circuit according to claim 1, wherein the error is not corrected even though all bits are inverted corresponding to the position of the signal level lowering portion. An error correction circuit characterized in that one or several bits before and after are included in the inversion target.