JPH03297238A - Clock transmission method - Google Patents

Abstract

PURPOSE:To reduce radiation of an undesired electromagnetic wave by frequency-dividing a clock signal into 1/2<n> sent from a sender side to a receiver side, that is, decreasing the transmission frequency. CONSTITUTION:A D latch circuit 4 frequency divides the frequency of an original clock signal into 1/2. The clock signal is used at the transmission by the sender side (electronic equipment 100). A clock recovery circuit 10 at a receiver side (electronic equipment 101) recovers the clock signal received into the original clock signal. A D latch circuit 3 latches a data signal sent from the sender side synchronously with the original clock signal recovered by the circuit 10 and outputs the latched data to internal circuits. A delay circuit 1 of the circuit 10 delays the received clock signal by 1/4 period, an XOR circuit 2 takes exclusive-OR between the clock signal outputted from the circuit 1 and the received clock signal to obtain a recovered clock signal. Thus, the frequency of the clock signal is decreased and radiation of undesired electromagnetic wave is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock transmission method for transmitting a clock signal in, for example, a data signal synchronization method.

[Prior Art] Conventionally, when transmitting data signals in a synchronous manner, a method has been used in which a data signal that changes in synchronization with a clock signal and a clock signal are transmitted as they are. That is, in this method, if the clock signal is 10 MHz, the data signal changes in synchronization with the 10 MHz clock signal, and the data signal and the 10 MHz clock signal are transmitted as they are.

[Problems to be Solved by the Invention] However, in the conventional method, as the frequency of clock signals in digital circuits has become high (in recent years), and the data transmission speed between devices has become faster, Unnecessary electromagnetic radiation has increased with the transmission of signals and data signals.

Such unnecessary electromagnetic radiation radiation may cause other electronic devices to malfunction or have various negative effects, so
It has to be below a certain level. Officially, regulations against unnecessary radiation have been established under these social conditions. This is, for example, F in U, S, A.
These include CC regulations and, in Japan, VCCI regulations.

However, in the various electronic devices manufactured in recent years, emphasis is placed on external design, and plastic molded products are often used for the exterior. Therefore, because plastics allow electromagnetic waves to pass through them, there is an even greater amount of unnecessary radiation than when iron armor was used to shield electromagnetic waves.

Furthermore, recent computers and other electronic devices that operate on various digital circuits rarely work independently (and are often connected to other digital devices with cables, etc., and operate as complex devices or system devices). As a result, cables that connect electronic devices become antennas for unnecessary radiation of electromagnetic waves, electromagnetic waves leak from connectors that connect cables, and unnecessary radiation from individual devices overlaps, causing overall damage. It has been extremely difficult to prevent the amount of unnecessary radiation from exceeding regulatory values.Since various signals in digital circuits are pulses, they contain many harmonics in addition to the fundamental frequency. Since the waves had higher frequencies, it became more difficult to reduce unnecessary radiation.

The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and its purpose is to provide a clock transmission method that can reduce the emission of unnecessary electromagnetic waves.

[Means for Solving the Problems] In order to solve the above-mentioned problems and achieve the objectives, a clock transmission method according to the present invention includes a clock transmission method in which, at the time of transmission, the transmission frequency of the clock signal is reduced to 1 on the transmitting side. /2'', and further transmits the frequency-divided clock signal to a receiving side, and the receiving side reproduces the original clock signal based on the clock signal transmitted from the transmitting side. Features.

[Operation] According to this configuration, by frequency-dividing the clock signal transmitted from the transmitting side to the receiving side by 1/2n, that is, lowering the frequency by one frequency, it is possible to reduce the emission of unnecessary electromagnetic waves.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

<First Embodiment> FIG. 2 is a diagram showing the configuration of a data transmission system according to the first embodiment, FIG. 1 is a circuit diagram showing the configuration of main parts of the data transmission system according to the first embodiment, and FIG. The figure is a timing chart of each signal during data transmission in the first embodiment.

In FIG. 2, electronic devices indicated by 100 and 101 are:
Cable 102 that transmits data signals, clock signals, etc.
electrically connected. In FIG. 1 showing the main parts when the transmitting side is an electronic device 100 and the receiving side is an electronic device 101, 4 indicates a D-type latch circuit that divides the frequency of the original clock signal by 1/2. is used by the sending side (electronic device 100 here) during transmission, for example, 5N
7474AN (manufactured by Texas Instruments) circuit. Further, 10 indicates a clock regeneration circuit, which is a circuit for regenerating the clock signal received at the time of transmission by the receiving side (here, the electronic device 101) into the original original clock signal. Reference numeral 3 denotes a D-type latch circuit, which is a circuit that latches the data signal transmitted from the transmitting side in synchronization with the original clock signal reproduced by the clock regeneration circuit 10 and outputs it internally. In the clock regeneration circuit 10, numeral 1 denotes a delay circuit that delays a received clock signal by 174 cycles, and this can be constructed using a known delay element or by connecting a plurality of inverter circuits in series. Reference numeral 2 designates an XOR circuit that performs an exclusive OR operation on the clock signal output from the delay circuit 1 and the received clock signal to obtain a reproduced signal of the clock signal.

In the above description, one electronic device 100 performs frequency division of the original clock signal, and the other electronic device 101 performs reproduction. Although not shown, the electronic device 100 may also be equipped with a configuration for reproducing, and the electronic device 101 may also be equipped with a configuration that divides the frequency of the original clock signal.

Here, the operation of the first embodiment will be explained using FIG.

In FIG. 3, (A) shows the waveform of the clock signal in the electronic device 100 on the transmitting side, and (B) shows the waveform of the clock signal on the transmitting side.
This shows a clock signal whose frequency has been lowered to 2. (C
) shows the waveform of the clock signal obtained by delaying the clock signal of B by approximately 1/4 period, and this shows the waveform of the clock signal at the point shown in FIG. 1 delayed by the delay circuit 1. (D) shows the waveform of the clock signal reproduced on the receiving side, and (E) shows the data signal. The data signal (E) takes the value of logic "1P" or °°0°° depending on the time, but the change in value is caused by the clock signal (A).
This is done in synchronization with the falling edge of .

First, there is a well-known method of dividing the frequency of the original clock signal into 1/2. Clock signal (B) whose frequency is divided by 1/2 from point g)
is obtained. This clock signal (B) is a pulse that reaches the electronic device 101 on the receiving side, and has the waveform of the clock signal at four points shown in FIG.

On the receiving side, the clock signal (B) inputted from four points via the cable 102 has the same waveform separated into two directions in the clock regeneration circuit 10, and on the other hand, the clock signal (B) is separated into two directions with the same waveform by the delay circuit 1. It is given a delay and output to eight points shown in FIG. The waveform output to this convex point is a clock signal (C). Furthermore, in the clock regeneration circuit 10, the clock signal (C) from the delay circuit 1 and the clock signal (B) that goes to the other side at four points (FIG. 1),
An exclusive OR is performed in the XOR circuit 2, and a clock signal (A), that is, a clock signal (D) reproduced to the same frequency and phase as the original clock signal, is output.

If the delay by delay circuit 1 is not 1/4 period, the duty of the clock signal (D) is no longer 50%,
Although different from the original clock signal (A), the timing at which the data signal (E) is taken into the latch circuit 3, that is, the rising edge of the clock signal (D), is determined by the rising and falling edges of the clock signal (B), so the original clock signal (A) is different from the original clock signal (A). Clock signal (
This is the same as A), so there is no practical problem.

Then, this reproduced clock signal (D) is a data signal (
E) is taken into the D-type latch circuit 3 at its own rising edge. The data signal E thus taken into the D-type latch circuit 3 is outputted from the output Q (the point shown in FIG. 1), and the intended synchronous data transmission is completed.

As explained above, according to the first embodiment, a high frequency clock signal is transmitted by reducing the frequency to 1/2 using a simple circuit, and the receiving side reproduces and obtains the original frequency clock. With this method, unnecessary electromagnetic wave radiation from the clock signal transmission path can be reduced and adverse effects on other devices can be prevented. Further, it is possible to easily produce a device that can meet the U.S., S.A., FCC regulations, domestic VCCI regulations, and the like.

Now, in the above-mentioned embodiment, the frequency of the original clock signal at the time of transmission was set to 1/2, but the present invention is not limited to this. If reducing the frequency to 1/2 is insufficient, on the transmitting side, the original clock signal is passed twice through the D-type latch circuit 4 shown in Figure 1 to divide the total frequency to 1/4. On the receiving side, the receiving clock signal frequency-divided by 1/4 may be configured to pass through the clock recovery circuit 10 twice to reproduce the original clock. Although it is possible to further reduce the frequency to 1/8, 1/16, etc., it is possible to reduce the frequency to 1/8, 1/16, etc., as long as it is determined based on conditions such as circuit complexity, clock frequency, unnecessary radiation amount, etc., without departing from the spirit of the present invention. good.

Second Embodiment In addition, as in the first embodiment described above, it is possible to reduce the frequency not only in the case of synchronous data transmission (but also in the case of long-distance transmission such as sending only a high-frequency clock signal). This makes it possible to reduce unnecessary radiation from transmission patterns and wires within the board or device.

FIG. 4 is a circuit diagram schematically showing the clock transmission circuit of the second embodiment. In FIG. 4, 5 indicates a D-type latch circuit that divides the frequency of the original clock signal into 1/2, similar to the D-type latch circuit 4 described above, and 8 indicates a clock output from the D-type latch circuit 5. Indicates a transmission path for transmitting a signal, 20
1 shows a clock regeneration circuit that regenerates the clock signal transmitted via the transmission line 8 to the frequency of the original clock signal. This clock regeneration circuit 20 has the same configuration as the clock regeneration circuit 10 described above. That is, 6 is a delay circuit which has the same configuration as the delay circuit 1 and delays the clock signal inputted through the transmission line 8 by approximately 1/4 period, and 7 has the same configuration as the XOR circuit 2 described above. 8 shows an XOR circuit that performs an exclusive OR operation on the clock signal inputted via the transmission line 8 and the clock signal outputted from the delay circuit 6 to reproduce the original clock signal.

In the above configuration, the operation is similar to that of the first embodiment described with reference to FIG. 3, so the explanation will be omitted. As shown in Figure 4,
This is effective when point A, which is the transmitting part of the clock signal, and point A, which is the receiving part of the clock signal, are far apart.

In this manner, the present invention can be sufficiently adapted to long-distance transmission in which only a high-frequency clock signal is sent inside an electronic device.

In addition, when lowering the frequency further, the D-type latch circuit 5 and the clock regeneration circuit 2
It may be configured to pass each 0 twice or more than twice.

[Effects of the Invention] As described above, according to the present invention, unnecessary radiation of electromagnetic waves from a clock signal transmission path can be reduced and adverse effects on other devices can be prevented.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing the configuration of the main parts of the data transmission system of the first embodiment, Figure 2 is a diagram showing the configuration of the data transmission system of the first embodiment, and Figure 3 is the data transmission system of the first embodiment. Timing chart of each signal during transmission. FIG. 4 is a circuit diagram schematically showing the clock transmission circuit of the second embodiment. In the figure, 1, 6...delay circuit, 2.7...XOR. 3.4.5...D-type latch circuit, 8...Transmission line, 1
0.20...Clock regeneration circuit, 100°101...
-Electronic equipment, 102...cable. Patent application: Canon Co., Ltd.

Claims (2)

[Claims] (1) In the clock transmission method, at the time of transmission, the transmitting side sets the transmission frequency of the clock signal to 1.
/2^n, further transmitting the frequency-divided clock signal to a receiving side, and on the receiving side, reproducing the original clock signal based on the clock signal transmitted from the transmitting side. A clock transmission method characterized by: (2) In a data signal synchronization type clock transmission method, at the time of transmission, on the transmitting side, the transmission frequency of the original clock signal that synchronizes the data signal is divided by 1/2^n, and the frequency of the divided clock is further divided into 1/2^n. The signal and the data signal are transmitted to a receiving side, and the receiving side reproduces the original clock signal based on the clock signal transmitted from the transmitting side, and reproduces the original clock signal based on the reproduced original clock signal. A clock transmission method characterized by synchronizing received data signals.