JPH03296119A - Reducing device for power consumption of personal computer - Google Patents

Reducing device for power consumption of personal computer

Info

Publication number
JPH03296119A
JPH03296119A JP2098258A JP9825890A JPH03296119A JP H03296119 A JPH03296119 A JP H03296119A JP 2098258 A JP2098258 A JP 2098258A JP 9825890 A JP9825890 A JP 9825890A JP H03296119 A JPH03296119 A JP H03296119A
Authority
JP
Japan
Prior art keywords
cpu
circuit
power consumption
personal computer
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2098258A
Other languages
Japanese (ja)
Inventor
Takakazu Yano
敬和 矢野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP2098258A priority Critical patent/JPH03296119A/en
Publication of JPH03296119A publication Critical patent/JPH03296119A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the power consumption of a personal computer without disturbing the CPU software under execution by switching a CPU and an input/ output device to the low power consumption state in accordance with the access state of the CPU to the input/output device. CONSTITUTION:A keyboard buffer access detecting circuit 106 detects whether a CPU 103 of a personal computer has been executed an access to the input/ output device provided to the personal computer or not. An access frequency counter circuit 107 and a T1 measuring circuit 109 measure the access frequency or the access cycle. Then a CPU stopping circuit 108 and a CPU driving circuit 111 switch at least the CPU 103 and the input/output device received an access to the low power consumption state from the active state and to reduce the power consumption of the personal computer. For instance, the circuit 108 receives the signals from the circuit 107 and switches the clock of the CPU 103 to a low frequency of the low power consumption state from a frequency of the active state. Thus the power consumption of the personal computer can be reduced without stopping such application software as the calculation software that should not be stopped even after a fixed time.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、パーソナルコンピュータにお[6消費電力低
減装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power consumption reduction device for a personal computer.

〔従来の技術〕[Conventional technology]

ラップトノブ型あるいはノートブック型のパーソナルコ
ンピュータは、その携帯性のよさから広く普及しつつあ
る。ところで、このような小型パーソナルコンピュータ
に共通している問題の1つは消費電力である。すなわち
、これらの小型パーソナルコンピータは携帯用電源とし
て電池を用いているが、通常動作だと2〜5時間時間上
か動作しないのが現状である。そのため、一定時間内に
入力装置からデータ入力がない場合は自動的に中央演算
装置(以下CPUと呼ぶ)を停止して、データ入力時に
CPUを自動的に駆動する、自動CPU停止システムを
備えたパーソナルコンピュータが考えられている。この
自動CPU停止システムのブロック図を第3図に示す。
Laptop-knob or notebook-type personal computers are becoming widely popular due to their portability. By the way, one of the problems common to such small personal computers is power consumption. That is, these small personal computers use batteries as a portable power source, but the current situation is that they do not operate for more than 2 to 5 hours during normal operation. Therefore, the system is equipped with an automatic CPU stop system that automatically stops the central processing unit (hereinafter referred to as CPU) if no data is input from the input device within a certain period of time, and automatically drives the CPU when data is input. A personal computer is being considered. A block diagram of this automatic CPU stop system is shown in FIG.

ここでT1測定回路304はCPUの割り込み信号lN
TRがハイレベルからロウレベルになる時点からカウン
ターを用いて一定時間T1を測定する回路である。
Here, the T1 measurement circuit 304 uses the CPU interrupt signal lN.
This circuit uses a counter to measure T1 for a certain period of time from the time when TR goes from high level to low level.

CPU停止回路605はTI測定回路304がらの信号
に応じてCPUを停止する回路である。また、CPU駆
動回路606はCPU停止後、あるいはカウント途中に
lNTRがハイレベルになると同時にカウンターをリセ
ットしCPU 301を駆動する回路である。すなわち
、一定時間入カ装置から入力がない時はCPUのクロッ
クを停止して低消費電力状態にするものである。
The CPU stop circuit 605 is a circuit that stops the CPU in response to a signal from the TI measurement circuit 304. Further, the CPU drive circuit 606 is a circuit that resets the counter and drives the CPU 301 after the CPU is stopped or at the same time that lNTR becomes high level during counting. That is, when there is no input from the input device for a certain period of time, the CPU clock is stopped and the CPU is placed in a low power consumption state.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の自動、CP U停止システムでは計算ソフトのよ
うに一定時間を超過しても停止したくないアプリケーシ
ョンソフトも停止してしまうという問題がある。また、
表示部を書き換えていない時でも表示を行い、逆に表示
部を書き換えている時に表示を消してしまうという問題
がある。
Conventional automatic CPU shutdown systems have a problem in that application software, such as calculation software, that does not want to be stopped even after a certain period of time has passed, ends up being stopped. Also,
There is a problem in that the display is displayed even when the display section is not being rewritten, and conversely, the display is erased when the display section is being rewritten.

本発明はこのような問題点を解決したパーソナルコンピ
ュータの消費電力低減装置を提供することを目的とする
An object of the present invention is to provide a power consumption reduction device for a personal computer that solves these problems.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するために本発明のパーソナルコンピー
タの消費電力低減装置は、パーソナルコンピュータのC
PUがパーソナルコンピュータに備えられた入出力装置
をアクセスしたか否か、すなわち、入出力装置のアドレ
スを指定して、データの入出力要求をしたか否かを検出
する検出手段と、このアクセスの頻度又は周期を計測す
る計測手段と、この計測手段の計測結果に応じて、CP
Uとアクセスされた入出力装置の少なくとも一方を動作
状態から低消費電力状態に切り換えることにより、パー
ソナルコンピュータを低消費電力状態にする切り換え手
段とを備えたことを特徴としている。
In order to achieve the above object, the personal computer power consumption reduction device of the present invention provides a personal computer power consumption reduction device.
a detecting means for detecting whether or not the PU has accessed an input/output device provided in the personal computer, that is, whether or not the PU has made a data input/output request by specifying the address of the input/output device; A measurement means for measuring the frequency or period, and a CP according to the measurement results of this measurement means.
The present invention is characterized in that it includes a switching means that brings the personal computer into a low power consumption state by switching at least one of the accessed input/output device from an operating state to a low power consumption state.

〔作用〕[Effect]

パーソナルコンピュータが実行中のソフトがワープロソ
フトのようにキーボード入力を待っている場合、CPU
は入力があるまで停止しても良いが、計算プログラムソ
フト等を実行している場合は計算処理が途中で止まり支
障がある。そこで本発明はCPUがアクセスする入出力
バッファーのアドレスバスの信号を検出する頻度に応じ
てCPUを停止するか否かを判断するようにしたもので
あるが、以下にこの方法により上記のような支障がなく
CPUの停止ができることを説明する。
If software running on a personal computer is waiting for keyboard input, such as word processing software, the CPU
may be stopped until an input is received, but if calculation program software or the like is being executed, the calculation process will stop midway, causing problems. Therefore, in the present invention, it is determined whether or not to stop the CPU depending on the frequency of detecting the address bus signal of the input/output buffer accessed by the CPU. Explain that the CPU can be stopped without any problems.

ワープロソフト等がキーボード入力を待っている場合、
そのソフトがメモリー中のキーポードパ。
If your word processing software is waiting for keyboard input,
That software is a keypad pad in memory.

ファーを頻繁にアクセスしているのに対し、計算プログ
ラムソフト等を実行している場合はメモリー中のキーボ
ードバッファーを全くアクセスしないか、アクセスして
いても比較的時間間隔が空いている。従って所定時間内
のアクセス回数が一定数に達した時CPUを停止するよ
うにすれば実行しているのが計算ソフトのように一定時
間を超過しても停止したくないアプリケーションソフト
も停止してしまうことはなくなる。
In contrast to frequently accessing the keyboard buffer in memory, when running calculation program software, the keyboard buffer in memory is not accessed at all, or even if it is accessed, it is accessed at relatively small intervals. Therefore, if you stop the CPU when the number of accesses within a predetermined time reaches a certain number, you can also stop application software that you do not want to stop even if it exceeds a certain time, such as calculation software that is running. You won't have to put it away anymore.

t f、−、パーソナルコンピュータに備えられた表示
システムの消費電力削減もCPUのアクセスしているア
ドレスの信号を検出して行える。すなわち、CPUが表
示システムの表示データが書き込まれるVRAMをアク
セスしているか否かをアドレスバスの信号を検出するこ
とにより検出し、度アクセスした後一定時間経過しても
VRAMのアクセスがなげれば表示用コントローラーを
停止させて表示を消して、低消費電力状態にする。
t f,-, power consumption of a display system installed in a personal computer can also be reduced by detecting the signal of the address being accessed by the CPU. In other words, it is detected whether the CPU is accessing the VRAM into which display data of the display system is written by detecting the signal on the address bus, and if the VRAM is not accessed even after a certain period of time has passed after the CPU has accessed it, Stops the display controller, turns off the display, and enters a low power consumption state.

〔実施例1〕 第1図にキーボードからの入力状況に対応してCPUの
動作状態を切り換え、パーソナルコンピータの消費電力
を低減する装置の構成を示す。
[Embodiment 1] FIG. 1 shows the configuration of a device that reduces the power consumption of a personal computer by switching the operating state of a CPU in response to input conditions from a keyboard.

第1図において、103はCPU、104はキーボード
用バッファーを含むメインメモリ、105はアドレスバ
スである。
In FIG. 1, 103 is a CPU, 104 is a main memory including a keyboard buffer, and 105 is an address bus.

T1測定回路109はキーボードからの割り込み信号l
NTRがハイレベルからロウレベルに移った時点から時
間を計り、ロウレベルがT1続いた時、タイムアツプ信
号を出力する回路であり、キーボード用バッファーアク
セス検出回路106はCPU103がメインメモリ10
4に含まれるキーボード用バッファーをアクセスする度
に、アクセス回数カウント回路107にパルスを送る回
路である。アクセス回数カウント回路107はT1の期
間アクセス数をカウントし、設定カウント数Nに達した
時、すなわち、CPUが入力待ちの時CPU停止回路1
08に信号を送る回路である。CPU停止回路108は
アクセス数カウント回路107からの信号を受けて、C
PUのクロックを動作状態の周波数から低消費電力状態
の低い周波数に切り換える。又、CPU駆動回路111
は信号lNTRがロウレベルからハイレベルニ移った時
、低周波数のクロックで停止状態にあるCPUを再び駆
動させる。
The T1 measurement circuit 109 receives an interrupt signal l from the keyboard.
This is a circuit that measures time from the time when NTR moves from high level to low level, and outputs a time-up signal when the low level continues for T1.
This circuit sends a pulse to the access count circuit 107 every time the keyboard buffer included in 4 is accessed. The access count circuit 107 counts the number of accesses during the period T1, and when the set count number N is reached, that is, when the CPU is waiting for input, the CPU stop circuit 1
This is a circuit that sends a signal to 08. The CPU stop circuit 108 receives the signal from the access count circuit 107 and stops the CPU
Switch the PU clock from the frequency in the operating state to the lower frequency in the low power consumption state. In addition, the CPU drive circuit 111
When the signal 1NTR changes from a low level to a high level, the CPU which is in a stopped state is driven again by a low frequency clock.

尚、前に述べた検出手段は本実施例においては、キーボ
ード用バッファーアクセス検出回路106が相当し、計
測手段はT1測定回路109とアクセス回数カウント回
路107が、切り換え手段は本発明に基づいて、動作状
態から低消費電力状態に切り換えるCPU停止回路10
8と再び動作状態に戻すCPU駆動回路111からなる
回路が相当する。
In this embodiment, the detection means described above corresponds to the keyboard buffer access detection circuit 106, the measurement means corresponds to the T1 measurement circuit 109 and the access count circuit 107, and the switching means corresponds to the keyboard buffer access detection circuit 106 based on the present invention. CPU stop circuit 10 that switches from operating state to low power consumption state
8 and a CPU drive circuit 111 that returns to the operating state again.

〔実施例2〕 第2図にCPUが表示装置をアクセスする場合、アクセ
ス状況に応じて、低消費電力状態に切り換える装置の構
成を示す。
[Embodiment 2] FIG. 2 shows the configuration of a device that switches to a low power consumption state depending on the access status when a CPU accesses a display device.

第2図において、201はCPU、204は表示装置の
表示部、206は表示用コントローラー205は表示デ
ータを記憶するVRAM、202ハアドレスバスである
In FIG. 2, 201 is a CPU, 204 is a display section of a display device, 206 is a display controller 205 that is a VRAM that stores display data, and 202 is an address bus.

VRAMバッファーアクセス検出回路206はCPIJ
201がVRAM205をアクセスする毎にT2測定回
路207にパルスを送る回路である。
The VRAM buffer access detection circuit 206 is a CPIJ
201 is a circuit that sends a pulse to the T2 measurement circuit 207 every time the VRAM 205 is accessed.

T2測定回路207はVRAMバッファーアクセス検出
回路206からT2秒間信号がこなければ表示用コント
ローラー停止回路208に信号を出す。表示用コントロ
ーラー停止回路208はT2測定回路207から信号を
受は取ると表示用コントローラー206を停止する回路
である。表示用コントローラー駆動回路209はVRA
Mバッファーアクセス検出回路206から信号を受は取
るか、又は入力装置からの割り込み信号lNTRがハイ
レベルになると表示用コントローラー206を駆動する
The T2 measurement circuit 207 outputs a signal to the display controller stop circuit 208 if no signal is received from the VRAM buffer access detection circuit 206 for T2 seconds. The display controller stop circuit 208 is a circuit that stops the display controller 206 when it receives a signal from the T2 measurement circuit 207. The display controller drive circuit 209 is a VRA
It receives a signal from the M buffer access detection circuit 206, or drives the display controller 206 when the interrupt signal lNTR from the input device becomes high level.

尚、前に述べた検出手段は本実施例においては、VRA
Mバッファーアクセス検出回路206が相当し、計測手
段はT2測定回路207が、切り換え手段は本発明に基
づいて、動作状態から低消費電力状態に切り換える表示
用コントローラー停止回路208と再び動作状態に戻す
表示用コントローラー駆動回路609から成る回路が相
当する。
Incidentally, in this embodiment, the above-mentioned detection means is a VRA.
This corresponds to the M buffer access detection circuit 206, the measuring means is the T2 measuring circuit 207, and the switching means is the display controller stop circuit 208 for switching from the operating state to the low power consumption state and the display for returning to the operating state again, based on the present invention. This corresponds to a circuit consisting of a controller drive circuit 609.

〔発明の効果〕〔Effect of the invention〕

本発明によるパーソナルコンピュータの消費電力低減装
置はCPUが入出力装置をアクセスするアクセス状況に
応じて、CPU、入出力装置を低消費電力状態に切り換
えるので、CPUの実行中のソフトに支障をきたすこと
なく、効率的に消費電力を低減できる。
The power consumption reduction device for a personal computer according to the present invention switches the CPU and the input/output device to a low power consumption state depending on the access status of the CPU to the input/output device, so that software being executed by the CPU is not affected. It is possible to efficiently reduce power consumption.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例の構成図、第2図は第2
の実施例の構成図、第3図は従来の装置の構成図である
。 106.201・・・・・・CPU。 105.202・・・・・・アドレスバス、104・・
・・・・メインメモリ、 106・・・・・・キーボード用バッファーアクセス検
出回路、 107・・・・・・アクセス回数カウント回路、108
・・・・・・CPU停止回路、 109・・・・・・T1測定回路、 111・・・・・CPU駆動回路、 203・・・・・・表示用コントローラー204・・・
・・・表示部、 205・・・・・・VRAM。 206、・・・・・・VRAMバッファーアクセス検出
回路、 207・・・・・・T2測定回路、 208・・・・・・表示用コントローラー停止回路、2
09・・・・・・表示用コントローラー駆動回路。 =147
FIG. 1 is a configuration diagram of the first embodiment of the present invention, and FIG. 2 is a diagram of the second embodiment.
Fig. 3 is a block diagram of a conventional device. 106.201...CPU. 105.202...address bus, 104...
... Main memory, 106 ... Keyboard buffer access detection circuit, 107 ... Access count circuit, 108
... CPU stop circuit, 109 ... T1 measurement circuit, 111 ... CPU drive circuit, 203 ... Display controller 204 ...
...Display section, 205...VRAM. 206...VRAM buffer access detection circuit, 207...T2 measurement circuit, 208...Display controller stop circuit, 2
09...Display controller drive circuit. =147

Claims (1)

【特許請求の範囲】[Claims]  パーソナルコンピュータの中央演算装置による入出力
装置のアクセスを検出する検出手段と、該アクセスの頻
度又は周期を計測する計測手段と、該計測手段の計測結
果に応じて前記中央演算装置と前記アクセスされた入出
力装置の少なくとも一方を動作状態から低消費電力状態
に切り換える切り換え手段とを備えたことを特徴とする
パーソナルコンピュータの消費電力低減装置。
a detection means for detecting an access to an input/output device by a central processing unit of a personal computer; a measuring means for measuring the frequency or cycle of the access; 1. A device for reducing power consumption of a personal computer, comprising: switching means for switching at least one of an input/output device from an operating state to a low power consumption state.
JP2098258A 1990-04-13 1990-04-13 Reducing device for power consumption of personal computer Pending JPH03296119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2098258A JPH03296119A (en) 1990-04-13 1990-04-13 Reducing device for power consumption of personal computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2098258A JPH03296119A (en) 1990-04-13 1990-04-13 Reducing device for power consumption of personal computer

Publications (1)

Publication Number Publication Date
JPH03296119A true JPH03296119A (en) 1991-12-26

Family

ID=14214932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2098258A Pending JPH03296119A (en) 1990-04-13 1990-04-13 Reducing device for power consumption of personal computer

Country Status (1)

Country Link
JP (1) JPH03296119A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5585750A (en) * 1994-06-07 1996-12-17 Hitachi, Ltd. Logic LSI
US6112309A (en) * 1997-04-23 2000-08-29 International Business Machines Corp. Computer system, device and operation frequency control method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5585750A (en) * 1994-06-07 1996-12-17 Hitachi, Ltd. Logic LSI
US6112309A (en) * 1997-04-23 2000-08-29 International Business Machines Corp. Computer system, device and operation frequency control method

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