JPH03258181A - Video signal transmitter - Google Patents

Abstract

PURPOSE:To attain desired condition for the operation by setting the operating condition of a moving vector detection circuit, a differential data generating circuit, a discrete cosine transformation circuit, a requantization circuit or a variable modulation coding circuit at the start of operation by a main control circuit. CONSTITUTION:A main control circuit 56 receive a processing program of each circuit block such as a moving vector detection circuit 16 and a differential data generating circuit 20 from an arithmetic processing unit provided externally and stores the processing program for each digital signal processing circuit provided to each circuit block. Moreover, the circuit 56 stores sequentially the processing program stored in a memory circuit to a transfer memory circuit at the operation of the video signal transmitter 10 and outputs the processing program to each digital signal processing circuit. Thus, the operating condition of each circuit program is set vea the circuit 56 and the arithmetic processing circuit provided externally as required is used and the processing program stored by the circuit 56 is revised.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B. Overview of the invention C. Conventional technology 8. Problems to be solved by the invention 8. Means for solving the problems (Fig. 1) 1. Effects (Fig. 1) G. Examples (Fig. 1 - Figure 10) (G1) Example tank bottom (Figures 1 and 2) (Gl-1
) Setting operating conditions (Gl-1-1) Motion vector detection circuit (Figure 3) (G
l-1-2) Difference data creation circuit (Figure 4) (Gl-1-
3) Discrete cosine transform circuit and discrete cosine inverse transform circuit (Fig. 5) (Gl-1-4) Requantization circuit (Fig. 6) (Gl-1-5) Variable length encoding circuit (Fig. 7~ Figure 1O) (G2) Operation of the embodiment (G3) Effects of the embodiment (G4) Other embodiments H Effects of the invention A Field of industrial application The present invention relates to a video signal transmission device, for example, The present invention can be applied to a video signal transmission device that performs efficiency encoding processing before transmission.

B Summary of the Invention The present invention provides a video signal transmission device in which the operating conditions of each circuit block are set by the main control circuit at the start of operation, thereby freely controlling the operating conditions of each circuit block via the main control circuit. Can be set.

C. Conventional technology Conventionally, in so-called video communication transmission systems that transmit video signals consisting of moving images to remote locations, such as video conference systems and television talk systems, video signals are The inter-frame correlation of the video signal is used to perform inter-frame encoding processing, thereby increasing the transmission efficiency of significant information.

That is, on the transmission device side, a motion vector detection circuit detects a motion vector of an image to be transmitted based on an image of a predetermined frame (hereinafter referred to as a reference frame).

Further, the transmitting device side moves the reference frame image by the amount of the motion vector to generate a comparison reference image, and then sequentially detects difference data pixel by pixel between the image to be transmitted and the image to be transmitted.
The difference data is transmitted together with the motion vector.

In the receiving device, the reference frame image transmitted in advance is moved by the amount of the transmitted motion vector, and then the transmitted difference data is added to reproduce the original image.

As a result, image data for one frame can be transmitted with a smaller amount of data than when directly transmitting image data for one frame, and by repeating the process, video signals can be transmitted efficiently. can do.

The method disclosed in Japanese Patent No. 61-288678 can be applied as needed to reduce requantization noise, and is considered convenient.

The present invention has been made in consideration of the above points, and aims to propose a video signal transmission device in which operating conditions can be freely set as required.

Problems to be Solved by the Invention In this type of video signal transmission device, image data may be directly transmitted instead of difference data.

In addition, when transmitting difference data and image data, discrete cosine transformation (discrete cosine transformation) is used.
(transform), requantization processing, and variable length encoding processing before transmission, thereby further improving transmission efficiency by switching the requantization step size and the like.

Therefore, if the operating conditions of the requantization circuit etc. can be freely set as necessary, for example, a means for solving the problem of time difference E can be obtained.In order to solve this problem, in the present invention, After creating comparison standard image data DP□ from the reference frame image data Dsv based on the motion vector detection circuit 16 that detects the vectors D and JG and the motion vector I) oG, the comparison standard image data DPII is created.
and a difference data creation circuit 16.20 that creates difference data D2 of image data DIND and selectively outputs difference data D2 or image data DIN11, and difference data creation circuit 1.
6. Difference data Dz and image data D output from 20
A discrete cosine transform circuit 22 performs discrete cosine transform on INO, a requantization circuit jI24 requantizes the output data D'aCT of the discrete cosine transform circuit 22, and converts the output data of the requantization circuit 24 into a variable length code. Variable length encoding circuit 3 that performs conversion processing and outputs
0, and a main control circuit 56 that sets the operating conditions of the motion vector detection circuit 16, difference data creation circuit 16, 20, discrete cosine transformation circuit 22, requantization circuit 24, or variable length encoding circuit 30 at the start of operation. be prepared for.

In the F-effect main control circuit 56, the operating conditions of the motion vector detection circuit 16, the difference data creation circuit 16, 20, the discrete cosine transformation circuit 22, the requantization circuit 24, or the variable length encoding circuit 30 are set at the start of operation. For example, it can be operated under desired operating conditions.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

(Gl) Structure of Embodiment In FIG. 1, 10 indicates a video signal transmission device as a whole, which mutually transmits video and audio of a caller to a transmission target.

That is, the video signal transmission 10 is transmitted to the television camera 12.
The television camera 12 captures an image of the caller through the
The video signal Sv output from the video signal processing circuit 1
Give to 4.

The video signal processing circuit 14 converts the video signal S into a luminance signal and a color difference signal, and then converts the signal into a digital signal using an analog-to-digital conversion circuit.

Further, the video signal processing circuit 14 converts the luminance signal and color difference signal converted into digital signals into CCITT (inter
national telegraph and
telephone consultative
committee) standard format.

That is, after thinning the video signal every predetermined frame and converting the frame frequency to 15 (Hz), the number of pixels in the vertical and horizontal scanning directions is reduced.

As a result, regarding the luminance signal, 352x 28BWI elements (i.e. CrF image size) or 176x 144i 1 element (i.e. QCIF
An input video signal is created in which continuous image data D□ (consisting of an image size of ) is generated.

In this manner, the video signal Sv is subjected to preliminary processing via the video signal processing circuit 14 to reduce the amount of data, thereby obtaining an input video signal in which the image data I)+s are continuous in the order of line scanning.

As shown in FIG. 2, the motion vector detection circuit 16 stores the image data DIN in a memory circuit in a built-in scan conversion circuit, and then sequentially reads the image data DIN in a predetermined order, thereby changing the arrangement of the image data DIN. Sort in a predetermined order.

That is, the motion vector detection circuit 16 divides one frame of image (FIG. 2(A)) into 2×6 blocks GOB (hereinafter referred to as block groups) in the horizontal and vertical scanning directions (FIG. 2(B)). ).

Furthermore, the motion vector detection circuit 16 converts each block group GOB into an 11×3 macroblock B.

After dividing the macro block Bx into 8x8ii 1-element micro blocks B in the horizontal and vertical scanning
t (Fig. 2 (C)).

As a result, the video signal processing device f1 transfers and processes image data in units of block groups GOB.

Furthermore, at this time, in the arrangement of the image data D0 in the block group GOB, the image data D0 is arranged consecutively in units of 83 macroblocks, and the macroblock B
, in the order of rask scanning, the minute blocks BL
The image data DIN is made continuous in units.

Note that here, the macroblock Bm has the following relationship with respect to the luminance signal:
While image data (y+ to Y4') of 16 x 16 pixels continuous in the horizontal and vertical scanning directions is taken as one unit, in the two corresponding color difference signals, the video signal processing circuit 14 processes the data. After the amount is reduced, time-axis multiplexing is performed to create one microblock BL.
Data for 16×16N elements is assigned to (C,,C,).

At this time, the motion vector detection circuit 16
The image of the previous frame reproduced in step 8 is set as the reference frame image, and macroblock B is processed.

The motion vector is detected for each motion.

Further, the motion vector detection circuit 16 moves the reference frame image by the amount of the detected motion vector, and moves the reference frame image by an amount corresponding to the 16×16 macroblock B of the current frame.
After creating image data for pixels, the image data DP
□ is output to the difference data creation circuit 20.

At the same time, the motion vector detection circuit 16 outputs the rearranged image data DIND after being delayed by the time required to detect the motion vector.

Further, the motion vector detection circuit 16 detects the image data D I
Header DHt with the HD frame number, block group and macroblock address data, motion vector D, JG, and the sum of absolute values obtained when detecting the motion vector.
? is generated and output to the difference data creation circuit 20.

The difference data creation circuit 20 outputs the image data I)H6 without any processing for each predetermined frame to the subsequent discrete cosine variable m circuit 22, and thereby outputs the intra-frame encoded image at each predetermined period. It is arranged so that data can be transmitted to a transmission target.

On the other hand, for frames other than the frames to be subjected to intra-frame encoding processing, image data D. The image data DPI+ is subtracted from the image data DPI+, and the resulting difference data D2 is output to the discrete cosine transform circuit 22.

As a result, the video signal transmission device 10 performs interframe encoding processing on the image data by transmitting the difference data Dz, and performs transmission by switching between intraframe encoding processing and interframe encoding processing at a predetermined period. The input video signal is efficiently transmitted to the target.

Furthermore, at this time, the difference data creation circuit 20 generates the image data D
When subtracting PI+ from image data DIND, a loop filter circuit is used as necessary to subtract image data DPII.
Suppresses the high-jag power of +.

As a result, in the video signal processing device 10, even if a motion vector is detected between macroblocks Bk and the difference data D2 is encoded, the boundaries between macroblocks Bk are not noticeable.

Furthermore, the difference data creation circuit 20 detects the amount of data required for transmission between macroblocks Bk, and it is determined that the amount of data required for transmission after intra-frame encoding processing is smaller than the amount of data required for transmission after inter-frame encoding processing. If it is determined that it is possible, even if there are B macroblocks in the frame that undergoes interframe encoding, the image data DIND is continuously encoded without any processing, as in the case of intraframe encoding and transmission. It is output to the cosine transform circuit 22.

Thus, in the video signal transmission bag W10, when performing interframe encoding processing, depending on the amount of data required for transmission,
In addition to suppressing the high-frequency components of the image data I) a@, the processing method is switched from interframe coding to intraframe coding, and from this, a selective prediction method is used to efficiently transmit video signals. It is made to be.

At the same time, the difference data creation circuit 20 removes the absolute value sum data from the header D□ transmitted from the motion vector detection circuit 16, and then generates the identification data of the interframe encoding process and the intraframe encoding process, and the loop filter circuit 20. The data is outputted to the discrete cosine conversion circuit 22 with the addition of identification data as to whether or not it is difference data obtained through the .

The discrete cosine conversion circuit 22 converts 2 of the video signal.
Using the dimensional correlation, the image data DINI+ and the difference data D2 output from the difference data creation circuit 20 are subjected to DCT transformation (discrete cos transform) in units of minute blocks B.
ine transform) L/, and outputs the resulting transformed data DIICa to the requantization circuit 24.

At this time, the discrete cosine conversion circuit 22 converts the conversion data D into the header transmitted from the difference data creation circuit 20.
Data such as the cumulative code length of DCT is added and output.

The requantization circuit 24 requantizes and outputs the converted data Docy.

At this time, the requantization circuit 24 detects the cumulative code length and data amount of the converted data I) based on the header output from the discrete cosine transform circuit 22, and also detects the remaining amount of the buffer circuit 26, and The quantization step size is switched based on the detection result.

As a result, the requantization circuit 24 maintains the amount of data per frame required for transmission at a predetermined value.

Further, the requantization circuit 24 converts the converted data DeT from the header output from the discrete cosine transform circuit 22.
After removing the data of the cumulative code length, etc., data of the quantization step size is added and output.

The inverse quantization circuit 26 executes a conversion process inverse to that of the requantization circuit 24 based on the header output from the requantization circuit 24, thereby converting the discrete cosine conversion circuit 20 reproduced on the transmission target side. Conversion data D DCT is reproduced on the transmission side.

On the other hand, the discrete cosine inverse transform circuit 28 executes the inverse transform process of the discrete cosine transform circuit 22 based on the header transmitted via the inverse quantization circuit 26.

As a result, in the video signal transmission device IO, the input data of the discrete cosine conversion circuit 22 that is reproduced on the transmission target side can be reproduced on the transmission side.

In other words, the video signal transmitted through the discrete cosine inverse transform circuit 28 after being intraframe encoded can reproduce image data D, . Regarding the video signal to be transmitted, the difference data D2 can be reproduced.

The decoder circuit 18 is comprised of a frame memory circuit and an adder circuit, and switches its operation based on the header transmitted via the discrete cosine inverse transform circuit 28.

That is, when intra-frame encoded data (that is, image data that reproduces image data DINt+) is output from the discrete cosine inverse transform circuit 28, the decoder circuit 18 directly stores the image data in the frame memory circuit. do.

Furthermore, with respect to the 1i scanning data stored in the frame memory circuit, at the timing when the image data DIN of the next frame is manually inputted to the motion vector detection circuit 16, motion vector detection is performed on the image data DSV stored in the frame memory circuit. Output to circuit 16.

As a result, the motion vector detection circuit 16 can detect a motion vector for a frame subsequent to a frame subjected to intra-frame encoding by setting the frame subjected to intra-frame encoding as a reference frame.

Furthermore, the decoder circuit 18 receives interframe encoded data (
In other words, when data that reproduces the difference data D2 is output, the image data DSv stored in the frame memory circuit is moved by the motion vector of the difference data D2, and then the moved image data is Difference data Dz
and stores it in the frame memory circuit.

This makes it possible to reproduce the original image data of the interframe encoded frame through the addition circuit, and thus the images transmitted to the transmission target side can be sequentially reproduced and stored in the frame memory circuit. can.

Further, the decoder circuit 18 decodes the image data DSV stored in the frame memory circuit at the timing when the image data DIN of the next frame is input to the motion vector detection circuit 16. is output to the motion vector detection circuit 16.

Thereby, the motion vector detection circuit 16 can sequentially detect the motion vector of the current frame using the previous frame as a reference frame.

Further, at this time, in the decoder circuit 18, the loop filter circuit is used to suppress the high frequency component of the difference data D2 created through the loop filter circuit, and the difference data D2 is moved by the amount of the motion vector. The loop filter circuit is switched in conjunction with the difference data creation circuit 20 to make the boundary between macroblocks B1 less noticeable.

The variable length encoding circuit 30 subjects the output data of the requantization circuit 24 obtained via the buffer circuit 32 to variable length encoding processing together with motion vector data, etc., and then outputs the data together with the header to the transmission buffer circuit 33.

The transmission buffer circuit 33 once stores the output data of the variable length encoding circuit 30, and then sequentially outputs the data in a predetermined order.

The stuff bit addition circuit 34 is the transmission buffer circuit 33
The output data of the transmission buffer circuit 33 is outputted to the error correction circuit 36, and at this time, the data amount of the input/output data of the transmission buffer circuit 33 is detected, and the data amount of the transmission buffer circuit 33 is compared to the transmission speed of the line L1.
When the amount of input data becomes extremely small, stuff bits are inserted between the data at a predetermined timing.

The error correction circuit 36 generates a BCH code (bose chaud) according to the output data of the stuff bit addition circuit 34.
huri hocquenghem code) is added to the output data output from the stuff bit addition circuit 34 and output.

Further, the error correction circuit 36 corrects errors in the data obtained from the transmission target via the multiplex conversion circuit 38 based on the BCH code added to the data and transmitted, so that even if an error occurs during transmission, This is designed to effectively avoid image quality deterioration.

The multiplex conversion circuit 38 multiplexes the digital audio signal with the output data of the error correction circuit 36, and then sends the signal to the line Ll.

Thereby, the video signal Sv and the audio signal can be efficiently transmitted to the transmission target.

At the same time, the multiplex conversion circuit 38 inputs the data transmitted from the transmission target via circuit #L1, and separates the multiplexed video signal and digital audio signal.

Furthermore, the separated digital audio signal is output to a predetermined decoding circuit, and the video signal is sent to a stuff bit removal circuit 4.
Output to 0.

The stuff bit removal circuit 40 removes the stuff bits inserted by the stuff bit addition circuit 34 on the transmission target side.

The buffer circuit 42 once stores the data from which the stuff bits have been removed, then separates the header and outputs it to the decoding circuit 44 .

The decoding circuit 44 performs inverse processing of the variable length encoding circuit 30 on the transmission target side.

The inverse quantization circuit 46 performs inverse quantization processing on the output data of the decoding circuit 44 based on the header input via the composite circuit 44, and thereby requantizes the data that has been requantized on the transmission target side. The input data of the conversion circuit 24 is reproduced.

Similarly to the discrete cosine inverse transform circuit 28, the discrete cosine inverse transform circuit 48 processes the output data of the inverse quantization circuit 46 based on the header, thereby reproducing the data subjected to the discrete cosine transform on the transmission target side. do.

The decoder circuit 50 executes the same processing as the decoder circuit 18 based on the transmitted header, thereby reproducing the image data encoded on the transmission target side.

The video signal processing circuit 52 uses an interpolation calculation method to
After performing the reverse processing of the video signal processing circuit 14, the resulting video signal is output to the monitor device 54, thereby making it possible to monitor the image of the communication target sent from the transmission target.

Thus, the image data DIHD and the image data D,
. Header D required for processing. By sequentially transmitting the image data in parallel in units of macroblocks, image data can be processed at high speed, and even if the operating conditions of each circuit block are changed, the image data can be processed reliably.

(Gl-1) Setting operating conditions The main control circuit 56 manually inputs processing programs for each circuit block, such as the motion vector detection circuit 16 and the difference data generation circuit 20, from an externally provided arithmetic processing device. The processing program is stored for each digital signal processing circuit provided in the block.

Furthermore, when the video signal transmission device 10 starts operating, the main control circuit 56 sequentially stores the processing programs stored in the memory circuit in the transfer memory circuit, and transfers the processing programs stored in the transfer memory circuit to each digital signal processing. Output to the circuit.

This allows the operating conditions of each circuit block to be set via the main control circuit 56, and the processing program held in the main control circuit 56 can be executed via an externally provided arithmetic processing unit as necessary. By updating, the operating conditions of each circuit block can be freely set.

Furthermore, when the setting of the operating conditions is completed, the main control circuit 56 outputs a start signal to each circuit block to start processing,
As a result, the image signal transmission device 10 starts encoding processing of the video signal Sv.

(Gl-1-1) Motion Vector Detection Circuit As shown in FIG. Detect DUG.

In other words, the evaluation function calculation units 60A to 60F sequentially and alternately capture image data DIN into the memory circuits 61 and 62 in units of block groups GOB (that is, image data of 176×48 pixels).

Furthermore, the evaluation function calculation units 60A to 60H process image data of an area larger than the block group GOB by the motion vector detection range (that is, since the motion vector detection range is within ±15 pixels in the horizontal and vertical scanning directions, 2
06 x 78 pixels) from the decoder circuit 18 to the memory circuit 63 or 64.
In response to the switching operations of 1 and 62, the data are sequentially and alternately captured.

Thus, in this embodiment, eight evaluation function calculation units 60A to 60H are used in parallel, and the memory circuit 6
Image data D in 1 or 62.63 or 64 IN% D
During the period of writing the SV, the remaining memory circuit 62 or 6
By repeatedly reading and processing the image data D0 and DSV stored in 164 or 63, the motion vector I) us can be detected in real time.

Here, the evaluation function calculation units 60A to 60H operate the memory circuit 6 based on the address data D aooa and DaD□.
1 or 62 and the image data DINs D, v stored in the memory circuit 63 or 64 are selectively read out and provided to the evaluation function circuit 65.

That is, the evaluation function calculation units 60A to 60H sequentially acquire image data D4 from the memory circuit 61 or 62 regarding the first minute block BL (represented by symbol Y in FIG. 2) of the macroblock B1 for which a motion vector is to be detected.
After reading and outputting to the evaluation function circuit 65, 2
The image data D for the minute block BL (represented by the symbol Y2), the third minute block BL (represented by the symbol Y), and the fourth minute block Bt (represented by the symbol Y4) is
IN is read and output to the evaluation function circuit 65.

At this time, the evaluation function calculation unit 60A calculates the image data D for the pixel at the rask scan start position of the micro block BL out of the image data DIN of each micro block BL.
, ),, the image data DIN is sequentially read for pixels adjacent to the current tlFN element in the vertical scanning direction, and the image data read processing for the micro block BL is completed.

On the other hand, in the evaluation function calculation section 60B, the image data I) of the pixel read out by the evaluation function calculation section 60A is
+s, image data D0 of pixels adjacent in the horizontal scanning direction are sequentially read out in the vertical scanning direction.

Further, in the evaluation function calculation units 60C and 60D, the image data D of the pixel read out by the evaluation function calculation unit 60B is
Image data DIN of pixels adjacent to II+ in the horizontal scanning direction are sequentially read out in the vertical scanning direction.

Similarly, evaluation function calculation units 60E, 60F, 60G and 60
In H, 1! in the horizontal scanning direction for the pixel image data DI)l read out by the evaluation function calculation unit 60D.
The image data DIN of pixels separated by a pixel is sequentially read out.

In this way, each evaluation function calculation unit 60A to 60H has 8
By reading out the image data DIN, the motion vector detection circuit 16 is able to read out and process all the image data D of one microblock B, and by repeating the eight processes four times, (Motion vectors are detected only for luminance signals), and all ij scanning data D4 for one macroblock can be read out and processed.

Furthermore, in the evaluation function calculation units 60A to 60H, when reading the image data I)sv from the memory circuit 63 or 64, similarly to when reading the image data DI11 from the memory circuit 61 or 62, each pixel adjacent to the horizontal scanning direction is image data is sequentially read out in the vertical scanning direction.

At this time, when reading the image data DIN from the memory circuit 61 or 62, the evaluation function calculation units 60A to 60H repeatedly read out the image data D1.4 in units of minute blocks B; When reading Dsv, first read the micro block BL for the macro block B corresponding to the image data DIN.
After reading out the image data D3V in units, the image data D3v is then read out at timings sequentially shifted by predetermined pixels in the vertical and horizontal scanning directions within the motion vector detection range.

As a result, in the evaluation function calculation units 60A to 60H,
Macroblock B of the current frame for which motion vectors are to be detected
The image data I)sv of the previous frame, which has been sequentially shifted in predetermined pixel units, is output to the evaluation function circuit 65 together with the image data DIN of the macroblock BI[.

The evaluation function circuit 65 sequentially subtracts the image data Dsv from the image data D to create difference data Da, and detects the sum of absolute values of the difference data D.

As a result, the image data DIN and D3v are read out in the vertical scanning direction in each of the evaluation function calculation units 60A to 60H, and the image data DIN and D3v are read out in the vertical scanning direction via the latch circuit 66 of each evaluation function calculation unit 60A to 60)1. For consecutive pixels, the sum of absolute values of difference data D, Ds+ea
−D□I can be obtained.

As a result, the output data DSrGA to D□ are latched by the latch circuit 66 in the arithmetic logic circuit 67 having an adder circuit configuration.

By cumulatively adding , it is possible to sequentially detect the absolute value sum of the difference data D in macroblock units, and by detecting the minimum movement position of the absolute value sum, it is possible to easily detect the motion vector. can.

Furthermore, when a motion vector is detected, the evaluation function calculation units 60A to 60H output the image data DIN of the macroblock in which the motion vector was detected to the memory circuit 69 via the latch circuit 68, thereby detecting the motion vector. After outputting the image data DIND of the detected macroblock to the subsequent difference data creation circuit 20, the process moves on to motion vector detection processing of the subsequent macroblock.

At the same time, the evaluation function calculation units 60A to 60H operate the memory circuit 63 or 64 based on the detected motion vector.
The image data D xv is read out from the memory circuit 70 , latched by the latch circuit 70 , and then output to the memory circuit 71 .

At this time, when detecting a motion vector, the image data I)sv is sequentially output from the memory circuits 61 to 64 only for the image data of the luminance signal, whereas when outputting the image data after detecting the motion vector, outputs image data D and v also for color difference signals.

As a result, the evaluation function calculation units 60A to 60H move the previous frame based on the detected motion vector, and image data D! After creating image data DPI+ corresponding to HD and outputting the image data D and 1 to the subsequent difference data creation circuit 20, the process moves to motion vector detection processing for the following macroblock.

The control circuit 72 transmits address data A to D based on the master clock signal Sc of the video signal transmission device 10.
D C and Al11I, D are outputted to the video signal processing circuit 14 and decoder circuit 1, respectively, and the image data D
0 and D5v can be sequentially input to the evaluation function calculation units 60A to 60H.

Furthermore, the control circuit 72 reads address data D an of the memory circuits 61 and 62 and the memory circuits 63 and 64.
oA and DA! +1111 and address data D
While ADDA is directly output to the evaluation function calculation units 60A to 60H, address data DA11ll11 is output to an arithmetic logic circuit 73 having an adder circuit configuration.

As a result, in the memory circuit 61 or 62, the output operation of the image data D0 is repeated in macroblock units, whereas in the memory circuit 63 or 64, the output operation of the image data D0 output from the memory circuit 61 or 62 is repeated. , the image data I)sv at the position shifted by the shift vector data D added by the arithmetic logic circuit 73 are sequentially output, and the shift vector data D,
By changing the value of , the moving position can be changed.

Furthermore, the control circuit 72 creates headers such as block group GOB address data, macroblock address data, etc., and outputs them to the digital signal processing circuit 75 via the register circuit 74.

The digital signal processing circuit 75 is composed of an arithmetic processing circuit, and receives shift vector data D,
is output to the arithmetic logic circuit 73.

At this time, the digital signal processing circuit 75
When the data Ds, r of the absolute value sum is taken in through the motion vector detection range 7, the value of the shift vector data D is switched, thereby sequentially detecting the absolute value sum within the motion vector detection range.

Furthermore, the digital signal processing circuit 75 receives data D! of the sum of absolute values. The minimum value of IG is detected, and the motion vector DUG is detected based on the detection result.

At this time, the digital signal processing circuit 75 takes in the processing program output from the main control circuit 56 when the video signal transmission device 10 starts operating, and then outputs shift vector data D based on the processing program, Thereby, the motion vector detection operation is switched in stages.

That is, in the first stage, the image data Dzv is sequentially moved at four-pixel intervals within the motion vector detection range, and the minimum value of the sum of absolute values is detected.

In the second stage, the motion vector detection range is reset based on the minimum movement value I of the sum of absolute values detected in the first stage, and the image data I)sv is set within the motion vector detection range. The minimum value of the sum of absolute values is detected by sequentially moving at 2vM elementary intervals.

Furthermore, in the third step, the motion vector detection range is reset based on the minimum movement position of the absolute value sum detected in the second step, and the image data D3v is set for one pixel within the motion vector detection range. It is sequentially moved at intervals and the minimum movement position of the sum of absolute values is detected.

Thereby, the motion vector detection circuit 16 detects a motion vector according to the operating conditions output from the main control circuit 56.

Therefore, by changing the processing program via the main control circuit 56, the conditions for motion vector detection operation can be freely selected, and the video signal transmission device 10 can be adjusted accordingly.
Usability can be improved.

Further, the digital signal processing circuit 75 calculates the motion vector D
When U is detected, the shift vector data D, from which the sum of the absolute values of the minimum values has been obtained, is output again to the arithmetic logic circuit 76, and then the motion vector detection processing for the subsequent macroblock is started.

By repeating this process, motion vectors are sequentially detected in macroblock units, and based on the motion vector detection results, image data D, □ of comparison standards are detected.
can be obtained.

Furthermore, the digital signal processing circuit 75 outputs the detected motion vector DU to the difference data creation circuit 20, and also converts the header output from the register circuit 74 into a predetermined format based on the processing program output from the main control circuit 56. output to the difference data creation circuit 20.

Therefore, by changing the processing program via the main control circuit 56, the content and format of the header output from the motion vector detection circuit 16 can be freely selected, and the video signal can be transmitted as necessary. The operation of the device 10 can be selected based on a particular consideration, and the usability of the video signal transmission device 10 can be improved.

(Gl-1, -2) Difference data creation circuit As shown in FIG. It is output to the selection circuit 81.

As a result, when the difference data creation circuit 20 performs intraframe encoding processing and transmits a video signal, the difference data creation circuit 20 inputs the image data D INB via the selection circuit 81 and the buffer memory circuit 82.
is output to the subsequent discrete cosine transform circuit 22.

The arithmetic logic circuit 83 having a subtraction circuit configuration receives image data DIN.
The image data Dpm+ is subtracted from l, to create difference data D2, and the difference data D2 is output to the selection circuit 85 via the buffer memory circuit 84.

As a result, when the difference data creation circuit 20 performs interframe encoding processing and transmits the video signal, the selection circuits 81 and 8
By switching the contact No. 5, the difference data D2 is output to the subsequent discrete cosine conversion circuit 22.

The arithmetic logic circuit 86 of the subtraction circuit wl inputs the image data D, □ through the loop filter circuit 87 and generates difference data DF □ from the image data D, , D.

Furthermore, the arithmetic logic circuit 86 outputs the difference data DF2 to the selection circuit 85 via the buffer memory circuit 88, thereby cutting off the contacts of the selection circuit 85 and continuing the difference data DF2 instead of the difference data D2. (It is designed so that it can be applied to the discrete cosine conversion circuit 22.

The square circuits 90, 91, and 92 each receive image data D1.
．． D, the difference data D2 and the difference data D, output the square value of □.

Arithmetic logic circuits 93, 94, 95 and 96 with addition circuit configuration
are the image data DIN! 1.2 power circuit 90.9
The output data of 1.92 is added to the output data of latch circuits 97.98.99 and 100, and the addition results are added to the output data of latch circuits 97.98.99 and 1.92, respectively. Do OO.

As a result, the arithmetic logic circuits 93, 94, 95 and 96 are
Image data D. and the values of Drll are A and 8, and the output data D□ of the loop filter circuit 87. Let FB be the reconnaissance of Detect each macrob Utsuku, and check the corresponding evaluation data D□, D H! s DM: Outputs l and D□ to the digital signal processing circuit 101.

The digital signal processing circuit 101 is composed of an arithmetic processing circuit and operates based on a predetermined reference signal output from the control circuit 102 in synchronization with the system clock signal SCK.

Further, the digital signal processing circuit lO1 includes a main control circuit 5
Based on the processing program output from the motion vector detection circuit 16, evaluation data D□, DM2. , D)
13 and D□, which creates the header D,! 1 to a predetermined format, the buffer memory circuit 10
3 to the digital signal processing circuit 104.

Like the digital signal processing circuit 101, the digital signal processing circuit 104 is composed of an arithmetic processing circuit that operates based on a processing program output from the main control circuit 56, and includes a header DI4! Based on A, selection circuits 81 and 8
5 is switched and controlled.

That is, based on the frame number of the header D□7, the image data DIHD is output to the following discrete cosine transform circuit 22 for each predetermined frame.

Thereby, in the video signal transmission apparatus, it is possible to perform intra-frame encoding processing for each predetermined frame and transmit a video signal.

On the other hand, in the remaining frames, the difference data D
Output FZ to the discrete cosine conversion circuit 22,
A video signal subjected to interframe encoding processing is transmitted.

At this time, the digital signal processing circuit 104 generates evaluation data D based on the processing program output from the main control circuit 56. , Do and D□ are obtained, and the difference data I)r
Image data D1.z instead of image data D1.z. ll or difference data D2 is output to the discrete cosine transform circuit 22.

That is, from equations (3) to (5), evaluation data I)*z
, I) If the image data I)+14o or the difference data D2 is transmitted instead of the difference data D2□ based on the comparison result of tiff and D□, the image data can be transmitted more efficiently.

Therefore, as in this embodiment, the evaluation data Dot, DH is calculated based on the processing program output from the main control circuit 56.
By obtaining the comparison results of 3 and D□ and switching the encoding process based on the comparison results, it is possible to transmit the video signal efficiently as a whole.

At this time, by setting the processing program via the main control circuit 56, not only the difference data D, , D, □ and the image data D4°, but also the entire data that needs to be transmitted, such as motion vectors, address data, etc. , the processing method that minimizes the amount of data can be selected.

Furthermore, by changing the processing program, for example, the frequency of use of the loop filter circuit 87 can be freely changed as necessary, and the usability of the video signal transmission device 10 can be improved accordingly.

Further, the digital signal processing circuit 104 includes a main control circuit 5
Header DIET output from the digital signal processing circuit 101 based on the processing program output from 6.
After removing the evaluation data D□, I)
is output to the subsequent discrete cosine transform circuit 22 via the buffer memory circuit 105.

Therefore, by changing the processing program via the main control circuit 56, the content and format of the header output from the difference data creation circuit 20 can be freely selected, and the corresponding video signal can be adjusted accordingly. The operation of the transmission device 10 can be freely selected.

(Gl-1-3) Discrete cosine transform circuit and discrete cosine inverse transform circuit As shown in FIG. 5, the discrete cosine transform circuit 22 includes three processing blocks ll0A, which are connected in parallel.
Consisting of ll0B and ll0C, image data Dz, D
Each processing block ll0A, ll0B processes FZ and DINE in macroblock units.

110C sequentially and cyclically for processing.

As a result, in the discrete cosine transform circuit 22, each processing block ll0AS 110B, 110C
are operated in parallel to perform discrete cosine transformation processing in real time.

That is, in the discrete cosine conversion circuit 22, the differential data creation circuit 2
Image data D2, DFZ and DIN output from 0
The data is given to each processing block 110A, 110B, and 110C.

Each processing block ll0A, 110B, ll0C includes six digital signal processing circuits 112A, 112B, 112
C, 112D, 112E, and 112F are provided with the Wi tracing data of the minute blocks, and thereby the image data D, DFZ, and DINll are subjected to discrete cosine transformation processing for each minute block.

In other words, the digital signal processing circuits 112A to 112F are expressed as follows:
u=1.2,...,N-1)=0 (
other) ... = Execute the arithmetic processing shown in (5) to obtain image data D, , D, □ and DINll
is subjected to discrete cosine transformation processing, and is processed according to the processing program output from the main control circuit 56 at this time, thereby performing high-speed discrete cosine transformation (FD
CT) calculation processing is executed.

Therefore, by changing the processing program via the main control circuit 56, the arithmetic processing algorithm can be changed. Usability can be improved.

On the other hand, discrete cosine inverse transformation times! 32B
and 48 are composed of the same circuit as the discrete cosine conversion circuit 22, and each digital signal processing circuit 112A
In steps 112F to 112F, the image data subjected to the discrete cosine conversion process is demodulated to the original frame image data by executing the process reverse to that of the discrete cosine conversion circuit 22.

At this time, each digital signal processing circuit 112A-, 112
In F, as in the case of the discrete cosine transform circuit 22, by executing arithmetic processing based on the processing program transferred from the main control circuit 56, the image data subjected to the discrete cosine transform is converted to the original image. Demodulate to data.

Therefore, as in the case of the discrete cosine conversion circuit 22, the processing program can be changed to switch the operating conditions as necessary, and the video signal transmission device lO
Usability can be improved.

(Gl-1-4) Requantization circuit As shown in FIG. 6, the requantization circuit 24 converts the transformed data D output from the discrete cosine transformation circuit 22
IcT is applied to the energy amount detection circuit 120, which detects the energy amount of the converted data DDca.

That is, the energy amount detection circuit 120 converts the converted data D,
4 is input to the squaring circuit 121, and here the conversion data D! is obtained by referring to the table. Detect the square value of IcT.

The arithmetic logic circuit 122 having an addition circuit configuration has a squaring circuit 121
The output data of each micro block is cumulatively added up to a predetermined number from the beginning of each micro block, and the addition result is output to the digital signal processing circuit 123.

(Then, the digital signal processing circuit 123 processes the cumulative added value based on the processing program output from the main@control circuit 56. When the cumulative added value is less than or equal to a predetermined value, the input The digital signal processing circuit 123 determines that the converted data D1A is a small block with conspicuous noise that does not need to be transmitted. Based on the processing program output from the main control circuit 56, the result is added to the header DMET output from the discrete cosine conversion circuit 22, thereby converting the header D, I! After updating the data into a predetermined format, it is output to the digital signal processing circuit 125 via the buffer memory circuit 124.

At this time, the digital signal processing circuit 123 outputs a control signal to the arithmetic logic circuit 122 based on the processing program outputted from the main control circuit 56, thereby switching the number of targets for cumulative addition value calculation, and The resulting cumulative addition pattern is separately output to both quantization blocks 126.

In this way, the operating conditions can be switched based on the processing program output from the main control circuit 56, and the usability of the video signal transmission device 3FIO can be improved accordingly.

On the other hand, in the requantization block 126, the converted data D11eT is inputted via the buffer circuit i27, and the requantization table 128, the threshold level variable circuit 129, the threshold level fixing circuit 130, and the selection circuit 13
1 to perform requantization processing.

At this time, in the requantization table 128, the table for requantization processing is switched based on the control signal output from the table switching circuit 132.

On the other hand, in the selection circuit 131, the output data of the requantization table 128 is received through the threshold level variable circuit 129 and the threshold level fixing circuit 130 at the contacts, respectively, and the switching signal output from the digital signal processing circuit 125 is received. Switch the contacts based on the

As a result, the requantization block 126 requantizes the transformed data Deer with a predetermined requantization step size, and then outputs it to the subsequent variable length encoding circuit 30 via the buffer circuit 32.

That is, the digital signal processing circuit 125 operates based on the processing program output from the main control circuit 56,
Header D output from digital signal processing circuit 123
In response to l1ET, table selection information is output to the table switching circuit 132 and a switching signal is output to the selection circuit 131.

At this time, the digital signal processing circuit 125 converts the header D□
, the intra-frame encoding process and the inter-frame encoding process are determined, and the table is switched based on the determination result.

Furthermore, the on/off operation of the loop filter circuit 87 in the difference data creation circuit 20, whether the motion vector is WLO,
Switch the table according to the size of the motion vector.

Furthermore, even if the requantization step size is made coarser, it is difficult to perceive image quality deterioration in the peripheral portion of am than in the central portion of the image, so the table is switched in accordance with the address data of the macroblock.

Further, the digital signal processing circuit 125 switches the table according to the cumulative addition value outputted from the energy amount detection circuit 120 and the requantization step size of one frame before.

On the other hand, the selection circuit 131 is switched and controlled based on the significant/insignificant data, and the output of data from the requantization table is controlled to be stopped for minute blocks in which noise that does not need to be transmitted is noticeable.

Further, the digital signal processing circuit 125 switches the table according to the amount of variable-length encoded data output from the variable-length encoding circuit 30 and the remaining amount of the transmission buffer circuit 33.

Furthermore, the digital signal processing circuit 125 updates the header D□ by adding the switching information of the requantization step size, and then updates the header D via the buffer circuit 133.
□A is output to the variable length encoding circuit 30 and the inverse quantization circuit 28.

In this way, by processing the header etc. and switching the requantization step size according to the processing program, the processing program can be switched and the conditions for switching the requantization step size can be freely set, and the video signal transmission can be adjusted accordingly. The usability of the device IO can be improved.

(Gl-1-5) Variable length encoding circuit As shown in FIG. and is given to the encoding table 140.

Furthermore, the variable length encoding circuit 30 supplies the input header DHET to a header decoding circuit (not shown) via the buffer circuit 32, and separates the address data and motion vector of the macroblock.

Furthermore, the variable length encoding circuit 30 supplies the separated address data and motion vector to a header processing circuit (not shown), which creates data of relative values of address data and motion vectors between consecutive macroblocks. , the relative value data is encoded in Table 1 along with the rest of the header.
40 at a predetermined timing.

At this time, the variable length encoding circuit 3o outputs the output data of the requantization circuit 24, relative value data, block pattern data (consisting of the data of the result of determining whether the block is significant or invalid determined by the requantization circuit 24), The remaining headers are sequentially output to the encoding table 140 in a predetermined order.

As shown in FIG. 8, the encoding table 140 outputs parallel variable length encoded data DT and code length data DL for the output data of the requantization circuit 24, relative value data, and block pattern data. On the other hand, predetermined parallel data D1i and code length data Dlj+ are output for the remaining headers.

Here, the parallel variable-length encoded data D7 is a value obtained when variable-length encodes the output data of the requantization circuit 24, relative value data, and block pattern data.
01", roof,, "01", "01"...
The code length data D is parallel data that is set to have a data length of 20 bits by adding data with the value "O" to the variable length encoded data D1. Consists of data representing significant bit length.

On the other hand, parallel data D? The engineer sequentially inputs the remaining headers from the header processing circuit into the encoding table 14 in a predetermined order.
By inputting 0, the header information is composed of parallel data of predetermined bits that are consecutive in the arrangement order when transmitting in the transmission format of the video signal transmission device 10,
The code length data DFM is data representing the significant bit length of the parallel data DT.

As shown in FIG. 9, the parallel-to-serial conversion circuit 14]
is the encoding table 】40 via the buffer circuit 142
Sequentially input the output data DT, Dtn9, D, DL8, and based on the code length data DL and DL)1,
Parallel variable length encoded data DT and parallel data D
Significant bits of TH are extracted and sequentially converted into serial data (FIG. 9(A)).

As a result, the output data of the requantization circuit 24, macroblock address data, motion vectors, and block pattern data are subjected to variable-length encoding processing via the parallel-to-serial conversion circuit 14, and then sequentially arranged in a predetermined order. Outputs serial variable length encoded data DVLC.

At this time, in the parallel-serial conversion circuit 141,
By sequentially converting the output data DT and DT11 of the encoding table 140 manually inputted via the buffer circuit 142 into serial data, the data is arranged in the order of the transmission format of the video signal transmission device ZIO and the header is placed at a predetermined position. Transmission data D. Output OT.

That is, as shown in Fig. 10, the transmission data DOUT
In, one frame period of image data DIi+,
Following the picture header, which includes data indicating the start of the frame (PSC), frame number (TR), data indicating the format of the data to be transmitted (PEI), etc.
The picture data in block group units are arranged to be continuous (FIGS. 10 (A) and (B)).

Furthermore, picture data includes data indicating the start of a block group (GBSC), address data of the block group (GN), and data regarding the requantization step size for each block group (GQUAN).
After the block group data in units of macroblocks continues (FIG. 10(C)).

On the other hand, block group data includes macroblock address data (MBA), macroblock requantization step size data (MQUA), and macroblock requantization step size data (MQUA).
NT), block pattern data (CBP), motion vectors (MVD), etc. are continuous, and then image data or difference data subjected to variable length encoding processing in units of minute blocks are continuous (see Fig. 10). (D)).

By sequentially outputting the output data of the parallel-serial conversion circuit 141 at a predetermined speed via the transmission buffer circuit 33, it is possible to sequentially output data in the CCITT [tl notification format].

On the other hand, the counter circuit 143 outputs the code length data D.
While counting up t, the transmission buffer circuit 33
, and outputs the count result to the requantization circuit 24.

Thereby, the requantization circuit 24 can immediately detect how the remaining capacity of the transmission buffer circuit 33 changes as a result of outputting data with a predetermined quantization step size.

That is, in the variable length encoding circuit 30, the processing result can be quickly fed back to the requantization circuit 24, and the requantization step size can be switched and controlled with high precision accordingly.

The arithmetic logic circuit 144 configured as an adding circuit sequentially cumulatively adds the code length data DL and outputs the addition result to the requantization circuit 24, thereby converting the output data amount of the variable length encoding circuit 30 into a requantization circuit. I will return on the 24th.

On the other hand, the flag table 145 sequentially outputs the stuff flag D1 in conjunction with the encoding table 140, and when the relative value data of the macroblock address data is input, raises the stuff flag Dr.

That is, in the CCITT recommended format, the stuff bit insertion position is designated immediately before the address data (MBA) of a macroblock subjected to variable length encoding.

Therefore, by raising the stuff flag DF in response to the relative value data of the macroblock address data, the stuff bit insertion position can be detected.

The buffer circuit 146 operates in conjunction with the buffer circuit 142 and outputs the stuff flag D7 to the parallel-serial conversion circuit 141.

Here, the parallel-to-serial converter circuit 141 sequentially outputs the input stuff flags D, whereas the variable length encoded data Dvtc is output with a delay of a predetermined clock period with respect to the corresponding stuff flag Dr. .

The transmission buffer circuit 33 sequentially stores variable length encoded data DVLC and stuff flag D1 in a data buffer circuit 33A and a flag buffer circuit 33B, respectively, and outputs them at a predetermined transmission rate.

The counter circuit 147 counts up the stuff flag D input to the flag buffer circuit 33B and counts down the stuff flag D output from the flag buffer circuit 33B.

Thereby, the counter circuit 147 can detect the number of stuff bit insertion positions stored in the data buffer circuit 33A based on the count result.

The control circuit 149 performs predetermined arithmetic processing to switch the selection circuit 150 MM, thereby causing the data buffer circuit 3
When the amount of data in 3A decreases and a space is about to appear in the transmission data D out, stuff bits l-D and T are inserted at the stuff bit insertion positions.

That is, the control circuit 149 controls the flag buffer circuit 33B.
When the stuff flag D output from the counter rises, it is determined whether the count result of the counter circuit 147 is the value O or not.

If a positive result is obtained here (this means that when the macroblock address data (MBA) is subsequently output from the data buffer circuit 33, the data buffer circuit 33A
(meaning that the amount of data stored in the data buffer circuit 33A decreases and the number of stuff bit insertion positions stored in the data buffer circuit 33A becomes 0), the control circuit 149
At a predetermined timing, the contact of the selection circuit 150 is switched to the stuff bit generation circuit 152 side, and the stuff bit Dstu output from the stuff bit generation circuit 152 is
is output to the error correction circuit 36.

At the same time, the control circuit 149 outputs a control signal to the transmission buffer circuit 33 to control the output of the variable length encoded data DVLC to be stopped.

As a result, in the control circuit 149, the data buffer circuit 33A receives new macroblock address data (M
Stuff bit D continuously until BA) is manually operated! A TU can be inserted, and one or more macroblock address data (MBA) are always stored in the data buffer circuit 33A.
This makes it possible to effectively avoid empty transmission data.

Furthermore, in the output data of the selection circuit 150, a stuff bit D is placed before the macroblock address data (MBA). U is inserted, and the stuff bit D S is inserted in the correct position corresponding to the format 1 of the image copying signal transmission device 10.
Tu can be inserted (FIG. 9(B)).

Here, the Karigo table 140 and the flag table 145
In this case, when the video signal transmission device 10 starts operating, the output data of the main control circuit 56 is taken in so that the contents of the encoded cable 140 and the flag block 145 can be written. be done to)

Therefore, by rewriting the contents of the encoding cable 140 and flag table 145 via the main control circuit 56 as necessary, you can freely control the operation of stuff bits, insertion positions, and variable length encoding processing. This improves the user experience of the video transmission device 10.

(G2) Embodiment Q) Operation In the above configuration, the video signal Sv output from the television camera 12 is converted into seven digital signals in the video signal processing circuit 14, and then sent to the CCI'l
'T recommendation soo~mat's image y'-y is converted to D0.

After the arrangement of images Y, Y, Y, DIN is changed by the moving ticket vector detection circuit 16, the main control circuit 5
According to the processing program output from 6, a moving vector is detected for each block on the macro.

That is, image data I], 8 are stored in memory circuits 61 and 6.
2, and is repeatedly output to the evaluation function circuit 65 in short intervals of t1.

In the first stage, the digital signal processing circuit 75 outputs 411b vector data D, and the difference data obtained by moving the image of the base frame by the JM element interval m is obtained. The sum of absolute values of the difference data is sent to the arithmetic logic circuit 67 and the meshing circuit 77.
The signals are sequentially stored in the digital signal processing circuit 75 via "."

On the other hand, in the second stage, the motion detection range is reset based on the movement position where the absolute value sum obtained in the first stage becomes the eel detective, and the detection range is reset from the digital signal processing circuit 75. A shift vector F.rude~riri that changes at two-pixel intervals centering on the moving device is output.

As a result, difference data obtained by moving the image of the reference frame by two pixels in black is obtained, and the sum of absolute values of the difference data is stored in the secondary digital signal processing circuit 75.

Furthermore, in the third stage, the motion vector detection range is reset centering on the moving position where the absolute value sum obtained in the second stage is the minimum, and the digital signal processing circuit 75 sends a signal centered around the moving object. A shift vector that changes at 1 pixel intervals.

is output.

As a result, difference data is obtained in which the motion of the reference frame 1 is thermally moved from one pixel to another, and a motion vector can be detected based on the difference data ω absolute rectification, and the main control circuit 5
By changing the processing program via 6, the dynamic red vector detection operation can be changed.

Based on the motion vector detected in this way, the comparison standard image data D, □ is generated, and the image data D, □
is the image data L). It is also output to the difference data creation circuit 20.

In the difference data creation circuit 20, the image data [) 21
is subtracted from both image data I)INII, and the difference data Dz
and DF21 are created, and the arithmetic and logic circuits 93 to 96 generate the evaluation data DHI%0.4 along with the image data DIMO.
is detected.

As a result, in the digital signal processing circuit 101,
5. Update the header according to the processing program, and transfer the evaluation data to the digital signal processing circuit 1.
Output to 04.

On the other hand, in the digital signal processing circuit 104,
According to the processing progera 1, the evaluation data DH1~・
Obtain the comparison result of D, and based on the comparison result, difference data D, , D□ and image D.

is selectively output to the discrete cosine transform circuit 22.

As a result, by rewriting the processing program via the main control circuit 56, the operating conditions of the differential y-ta generation circuit 20 can be changed, and intra-frame encoding processing and inter-frame encoding processing can be switched under desired conditions. I can do it.

In the discrete cosine transform circuit 22, the image data D2, DF□, and DIND are sequentially processed by the discrete cosine transform circuit in each digital signal processing circuit 112A to 112F according to the processing program output from the main control circuit 56. By rewriting the processing program via the circuit 56, the arithmetic processing algorithm of the discrete cosine transform circuit 22 can be changed.

Transformed data DD subjected to discrete cosine transformation
C? is requantized by the requantization circuit 24, and the requantization step size is switched according to the processing program output from the main control circuit 56, thereby rewriting the processing program via the main control circuit 56. Accordingly, the operating conditions of the requantization circuit 24 can be changed.

The requantized data is passed through the buffer circuit 32 and subjected to variable length encoding processing in the variable length encoding circuit 30. At this time, the encoded table 140 and flag table 145 formed through the main control circuit 56 are By processing using the above, it is possible to set the variable length encoding processing operation and the stuff bit insertion position, and the output data is sequentially transmitted to the transmission buffer circuit 33, the stuff bit addition circuit 34, the error correction circuit 36, and the multiplex conversion circuit. 38 to the transmission target.

Further, the output data of the requantization circuit 24 is inputted to the decoder circuit 18 via the inverse quantization circuit 26 and the discrete cosine inverse transform circuit 28 in order, and the original image data is reproduced as prediction reference image data DSV. Output.

(G3> Effects of the Embodiment According to the above configuration, when the video signal transmission device 10 starts operating, the main control circuit 56 outputs the processing program and data for encoding processing to each circuit block, so that the processing Operating conditions for each circuit block can be set based on the program and data for encoding processing.

(G4) Other embodiments In the above embodiments, a motion vector detection circuit,
Difference data creation circuit, discrete cosine conversion circuit,
Although the case has been described in which the operations of the discrete cosine inverse transform circuit, the variable length encoding circuit, and the stuff bit adding circuit are switched, the present invention is not limited to this, and the circuit blocks to be switched can be freely selected as necessary. can.

Furthermore, the contents of the operating conditions to be set can be changed to various conditions as necessary.

Furthermore, in the above-described embodiment, the present invention is applied to a video signal transmission device that transmits a video signal together with an audio signal, but the present invention is not limited to this, and the present invention is not limited to this, and the present invention is not limited to this. It can be widely applied when transmitting, recording on a recording medium, etc.

H Effects of the Invention As described above, according to the present invention, by setting the operating conditions of each circuit block at the start of operation via the main control circuit, each circuit block can be adjusted to desired operating conditions as necessary. A video signal transmission device that can be configured can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a video signal transmission device according to an embodiment of the present invention, FIG. 2 is a route diagram for explaining the operation of a motion vector detection circuit, and FIG. 3 is a block diagram showing a motion vector detection circuit. FIG. 4 is a block diagram showing a difference data creation circuit, FIG. 5 is a block diagram showing a discrete cosine transform circuit and a discrete cosine inverse transform circuit,
FIG. 6 is a block diagram showing a requantization circuit, FIG. 7 is a block diagram showing a variable length encoding circuit, and FIGS. 8 to 10 are route diagrams for explaining the operation thereof. lO...Video signal transmission device, 16...
Motion vector detection circuit, 20...Difference data creation circuit, 24...Requantization circuit, 30...
・Variable length encoding circuit, 33...Transmission buffer circuit, 34...Standard buffer E addition circuit, 56
...Main control circuit. Agent Megumi Tanabe

Claims (1)

[Scope of Claims] A motion vector detection circuit that detects a motion vector of image data; After creating comparison reference image data from image data of a reference frame based on the motion vector, the comparison reference image data and the above Create difference data of image data,
a difference data creation circuit that selectively outputs the difference data or the image data; a discrete cosine conversion circuit that performs discrete cosine transform on the difference data and the image data output from the difference data creation circuit;
a requantization circuit that requantizes the output data of the discrete cosine transform circuit; a variable length encoding circuit that performs variable length encoding processing and outputs the output data of the requantization circuit; A video signal transmission device comprising a motion vector detection circuit, the difference data creation circuit, the discrete cosine transformation circuit, the requantization circuit, or the control circuit for setting operating conditions of the variable length encoding circuit. .