JP2539786Y2 - Video signal transmission device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial application field B Outline of the device C Conventional technology D Problems to be solved by the device (FIGS. 5 and 6) E Means for solving the problem (FIGS. 1, 3 and 4) Fig. F action (Figs. 1, 3 and 4) G embodiment (Figs. 1 to 4) (G1) Configuration of embodiment (Figs. 1 and 2) (G-1) (G2) Operation of the embodiment (G3) Effects of the embodiment (G4) Other embodiments H Effect of the invention A Industrial application field This invention relates to video signal transmission. The device can be applied to, for example, a video signal transmission device that performs high-efficiency coding processing on a moving image video signal and transmits the signal.

B. Outline of the Invention In the present invention, in a video signal transmission device, image data stored in a frame memory circuit for pre-processing a video signal or detecting a motion vector is transferred to a received frame memory circuit for storing image data. By combining images, an image transmitted from a transmission target and an image transmitted to the transmission target can be simultaneously displayed with a simple configuration as a whole.

C Conventional technology Conventionally, in a so-called video communication transmission system for transmitting a video signal composed of a moving image to a remote place such as a video conference system and a video phone system, for example, An image frame is subjected to an inter-frame encoding process using inter-frame correlation, thereby improving the transmission efficiency of significant information.

That is, on the transmission device side, the motion vector detection circuit detects the motion vector of the image to be transmitted with reference to the image of the predetermined frame (hereinafter, referred to as a reference frame).

Further, the transmitting apparatus moves the image of the reference frame by the amount of the motion vector to generate the image of the comparison reference,
Difference data is sequentially detected on a pixel basis with the image to be transmitted, and the difference data is transmitted together with the motion vector.

In the receiving apparatus, after moving the previously transmitted reference frame image by the amount of the transmitted motion vector, the transmitted difference data is added to reproduce the original image.

This makes it possible to transmit one frame of image data with a smaller amount of data than in the case of directly transmitting one frame of image data, and to transmit the video signal efficiently by repeating the process. .

D Problems to be Solved by the Invention By the way, in this type of video signal transmission device, an image transmitted from a transmission target and an image to be transmitted are simultaneously displayed, and what kind of image is transmitted to the transmission target is monitored. It would be useful if you could.

For this purpose, as shown in FIG. 5, the output video signal S _VOUT of the video signal transmission device 2 is applied to the video signal S _VOUT by using a modularized picture-in-picture circuit 1 used for, for example, a television receiver. methods for synthesizing the input video signal S _V of the signal transmission device 2 is considered (Japanese Patent Application No. 1-1254
No. 3).

That television video signal S _V parties taken by Ji camera, after conversion to digital signals by analog-to-digital converter (A / D) 4 and outputs the picture relevant ya in picture relevant Ya circuit 1, the transmitting unit 5 Encode and output.

On the other hand, transmission data arriving from the transmission target is decoded by the receiving unit 6 and is converted into a digital / analog conversion circuit (D / A) 7.
To convert to a video signal _SVOUT .

Further outputs a video signal S _VOUT output from the digital-to-analog converting circuit 7 to the adding circuit 8, wherein after combining the video signal S _V output from the picture relevant Ya-in picture relevant Ya circuit 1, and outputs to the monitor device.

In this way, as shown in FIG. 6, the caller's own image B can be displayed at the corner of the image A on the transmission target side, and what image is transmitted to the transmission target together with the transmitted image. You can monitor what is happening.

However in practice, in the picture relevant Ya in picture relevant Ya circuit 1 of this kind, after storing in the frame memory circuit is once converted into a digital signal a video signal S _V, the video signal S
By that converts an analog signal based on the _VOUT, is adapted to synthesize a video signal S _V to the video signal S _VOUT.

Therefore, when applied to this type of video signal transmission device,
There is a problem in that the configuration is duplicated with the main body of the video signal transmission device 2 and the overall configuration is complicated accordingly.

The present invention has been made in view of the above points, and proposes a video signal transmission device capable of simultaneously monitoring an image transmitted from a transmission target and an image transmitted to the transmission target with a simple configuration as a whole. It is assumed that.

In the present invention for solving means according challenge to solve E problem, the analog-to-digital converter circuit 60 for converting an input video signal S _V to the digital video signal, a digital video signal in the first frame memory circuit 66 and the format converting circuit 14 for converting the image data D _iN given the format by thinning out the Yotsute digital video signal to be read out at a predetermined timing and stores, on the basis of a predetermined reference image data D _SV, the image data D _iN a motion vector detecting circuit 16 for detecting a motion vector D _UG, based on the motion vector D _UG, image data D
Encoding circuit 2 that encodes _IN to generate transmission data
0, 22, 24, and a transmission decoder that decodes the transmission data and stores the decoded data in the second frame memory circuits 80 and 78 and then reads out the reference image data _DSV to the motion vector detection circuit 16 at a predetermined timing. a circuit 18, a reception decoder circuit 46, 48, 50 to create a received image data D _F3 by decoding the transmission data coming from the transmission target, the received image data D _F3
Is stored in the third frame memory circuit 90, and is read out at a predetermined timing to obtain the reception image data _DF3.
And a digital inverse conversion circuit 52 that converts the received digital video signal into an analog signal, and converts the received digital video signal into an analog signal. when storing _F3 in the third frame memory circuit 90, at a predetermined timing, instead of the received image data D _F3, the image data D _F1 or the second frame memory circuit output from the first frame memory circuit 66 by storing the reference image data D _F4 output from 80, the part of the image of the received image data D _F3, the image or the second frame of the image data D _F1 output from the first frame memory circuit 66 Reference image data D _F2 output from the memory circuit 80
Display the image of.

F Operation When the received image data D _F3 is stored in the third frame memory circuit 90, the received image data D _F3 is stored at a predetermined timing.
Instead, the image data D _F1 output from the first frame memory circuit 66 or the reference image data D _F2 output from the second frame memory circuit 80 is stored, and the received image data D _F1 is stored.
Some of the _F3 of the image, by displaying the reference image data D _F2 outputted from the image data D _F1 image or the second frame memory circuit 80 of the output from the first frame memory circuit 66, a separate circuit Even without providing, the image to be transmitted and the image transmitted to the transmission object can be monitored simultaneously.

G Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

(G1) Configuration of Embodiment In FIG. 1, reference numeral 10 denotes a video signal transmission device as a whole, and mutually transmits a video and a voice of a caller to and from a transmission target.

That video signal transmission 10, TV via Ji camera 12 images the caller, providing a video signal S _V, which is output from the television camera 12 to the video signal processing circuit 14.

Video signal processing circuit 14 converts the video signal S _V to the luminance signal and the color difference signal into a digital signal by the analog-to-digital converter circuit.

Further, the video signal processing circuit 14 converts the luminance signal and the color difference signal converted into digital signals into CCITT (international signals).
elegraph and telephone consultative committee).

That is, after the video signal is decimated every predetermined frame to convert the frame frequency to 15 [HZ], the number of pixels in the vertical and horizontal scanning directions is reduced.

As a result, regarding the luminance signal, 352 × 288 pixels (that is, a CIF image size) or 1 in the horizontal and vertical scanning directions.
Image data D _IN of 76 × 144 pixels (i.e. in picture size of QCIF) to create an input video signal to be continuous.

Thus, the video signal is processed via the video signal processing circuit 14.
To reduce the amount of data subjected to preliminary processing S _V, the image data D _IN can be obtained input image signal consecutive in the order of line scanning.

As shown in FIG. 2, the motion vector detection circuit 16 stores the image data D _IN in a built-in scan conversion circuit once in a memory circuit, and then sequentially reads out the image data D _{IN in} a predetermined order. Rearrange the array in a predetermined order.

That is, the motion vector detecting circuit 16 divides the image of one frame (FIG. 2 (A)) into 2 × 6 blocks GOB (hereinafter referred to as block groups) in the horizontal and vertical scanning directions (FIG. 2 (B)). ).

Further motion vector detecting circuit 16, 8 × After dividing each blow poke group GOB of 11 × 3 in macroblock B _K, the more the macro block B _K in the horizontal and vertical scanning direction
The image is divided into minute blocks _BL in units of 8 pixels (FIG. 2C).

Thus, the video signal processing apparatus 1 transfers and processes image data in units of block groups GOB.

At this time, the image data D in the block group GOB
In the arrangement of _IN it is done so that the image data D _IN is continuous in macro-block B _K units, within the macroblock B _K, so that the image data D _IN is continuous small blocks B _L units in the order of raster scan Is made.

Here, the macro block B _K is
While 16 × 16 pixel image data (Y _{1 to} Y ₄ ) continuous in the horizontal and vertical scanning directions is defined as one unit, the video signal processing circuit 14 is used for two corresponding color difference signals.
After the data amount is reduced in, time axis multiplexing is performed,
Data of 16 × 16 pixels is allocated to one minute block B _L (C _r , C _B ).

At this time, the motion vector detection circuit 16
In the reproduced 1 frame preceding image was set to the image of the reference frame, to detect a motion vector for each macroblock B _K.

Further motion vector detecting circuit 16, it is moved by the amount the reference frame image of the detected motion vector and creates picture data of 16 × 16 pixels at the position corresponding to the macroblock B _K of the current frame, the image data _DPRI is output to the difference data creation circuit 20.

At the same time, the motion vector detection circuit 16 outputs the image data D _IND with the rearranged arrangement delayed by the time required for detecting the motion vector.

Further, the motion vector detection circuit 16 generates a header D _MET with the frame number of the image data D _IND , the address data of the block group and the macro block, the motion vector D _UG , and the absolute value sum obtained at the time of the motion vector detection. Is output to the difference data creation circuit 20.

The difference data creation circuit 20 outputs the image data D _IND to the subsequent discrete cosine conversion circuit 22 without any processing for each predetermined frame, and thereby, for each predetermined period, the image data subjected to the intra-frame encoding processing. Can be transmitted to the transmission target.

On the other hand, the image data D _FRI is subtracted from the image data D _IND for frames other than the frame to be subjected to the intra-frame encoding process, and the resulting difference data D _Z is output to the discrete cosine transform circuit 22.

In this manner the video signal transmission device 10, by transmitting the difference data D _Z, the image data and inter-frame coding by switching the coding processing and interframe coding processing frame at a predetermined cycle, An input video signal is efficiently transmitted to a transmission target.

Further, at this time, the difference data creation circuit 20 outputs the image data D
The _PRI when subtracted from the image data D _IND, suppresses the high-frequency component of the image data D _PRI with a loop filter circuit as necessary.

In the video signal processing apparatus 10 Thus, the difference in detecting the motion vector in macro-block B _K unit data D _Z
Be treated encoded, it has been made so inconspicuous boundary between macro blocks B _K.

Further difference data generating circuit 20 is transmitted in less data than to detect the amount of data required for transmission in macro block B _K units, who has transmitted by processing frame coding is transmitted by inter-frame coding If you decide that you can,
Macro block B _{K of the} frame to be subjected to inter-frame coding
In even filed, and outputs the discrete cosine transform circuit 22 which follows without that in any way process the image data D _IND as in the case of transmitting intra-frame coding.

Thus, in the video signal transmission device 10, when performing the inter-frame encoding process, according to the amount of data required for transmission,
In addition to suppressing the high-frequency component of the image data D _UG , the processing method is switched from inter-frame encoding to intra-frame encoding, so that video signals can be transmitted efficiently using a selective prediction method. Has been made.

At the same time, the difference data creation circuit 20
After removing the data of the sum of absolute values from the header D _HET transmitted from 16, the identification data of the inter-frame encoding processing and the intra-frame encoding processing, and identification of whether or not the difference data obtained through the loop filter circuit The data is added and output to the discrete cosine conversion circuit 22.

The discrete cosine conversion circuit 22 converts the video signal 2
Using the dimensional correlation, the image data D _IND and the difference data D _Z output from the difference data creating circuit 20 are subjected to DCT (discrete cosine transform) in units of minute blocks _BL , and the resulting transformed data D _DCT is obtained. Output to the requantization circuit 24.

At this time, the discrete cosine conversion circuit 22 applies the conversion data D _DCT to the header transmitted from the difference data creation circuit 20.
And outputs the data such as the accumulated code length.

The requantization circuit 24 requantizes the transform data D _DCT and outputs it.

At this time, the requantization circuit 24 converts the converted data based on the header output from the discrete cosine conversion circuit 22.
It detects the accumulated code length and the data amount of the _DCT , detects the remaining amount of the transmission buffer circuit 33, and switches the quantization step size based on the detection result.

As a result, the requantization circuit 24 holds the data amount per frame required for transmission to a predetermined value.

Further re-quantization circuit 24, after removal of the data of the cumulative code length of the conversion data D _CT from the header output from the discrete cosine transform circuit 22, and outputs the added data of the quantization step size.

The inverse requantization circuit 26 performs an inverse conversion process with respect to the requantization circuit 24 based on the header output from the requantization circuit 24, and thereby a discrete cosine transform circuit 20 reproduced on the transmission target side. _Is converted on the transmission side.

In contrast, the discrete cosine inverse conversion circuit 28
Executes the inverse transform processing of the discrete cosine transform circuit 22 based on the header transmitted via the inverse requantization circuit 26.

Thus, in the video signal transmission apparatus 10, the input data of the discrete cosine conversion circuit 22 reproduced on the transmission target side can be reproduced on the transmission side.

That is, the video signal transmitted through the intra-frame encoding process through the inverse cosine inverse transform circuit 28 can reproduce the image data D _IND , whereas the video signal transmitted through the inter-frame encoding process can be transmitted. the video signal that can be reproduced difference data D _Z.

The decoder circuit 18 is composed of a frame memory circuit and an adding circuit, and switches its operation based on a header transmitted via the discrete cosine inverse conversion circuit 28.

That is, when the discrete cosine inverse transform circuit 28 outputs data subjected to intra-frame encoding processing (that is, image data obtained by reproducing the image data _DIND ), the decoder circuit 18 directly transmits the image data to the frame memory circuit. To be stored.

Further, with respect to the image data stored in the frame memory circuit, at the timing when the image data D _IN of the next frame is input to the motion vector detection circuit 16, the image data D _SV stored in the frame memory circuit is Output to the detection circuit 16.

As a result, the motion vector detection circuit 16 can detect a motion vector by setting the frame subjected to the intra-frame encoding processing as a reference frame for a frame subsequent to the frame subjected to the intra-frame encoding processing.

The decoder circuit 18 further, when the inter-frame coded data from the discrete cosine inverse transform circuit 28 (i.e., the data obtained by reproducing the difference data D _Z) is output, the image data stored in the frame memory circuit D
After the _SV is moved by the amount of the motion vector of the difference data D _Z, is stored in the frame memory circuit adds the image data obtained by the mobile to the difference data D _Z.

Thereby, the original image data of the frame subjected to the inter-frame encoding processing can be reproduced through the addition circuit,
Thus, the image transmitted to the transmission target side is sequentially reproduced,
It can be stored in a frame memory circuit.

Further, the decoder circuit 18 outputs the image data stored in the frame memory circuit at the timing when the image data D _IN of the next frame is input to the motion vector detection circuit 16 with respect to the image data stored in the frame memory circuit.
D _SV is output to the motion vector detection circuit 16.

Thus, the motion vector detection circuit 16 can sequentially detect the motion vector of the current frame using the frame one frame before as the reference frame.

Further, in the decoder circuit 18 at this time, the difference data D _Z created through a loop filter circuit,
Made to move by the amount of the motion vector by suppressing the high frequency component using a loop filter circuit, thereby switching the loop filter circuit in conjunction with the differential data creating circuit 20, conspicuous boundary between macroblocks B _K Not to be.

The variable-length encoding circuit 30 performs variable-length encoding processing on output data to the requantization circuit 24 obtained through the buffer circuit 32 together with motion vector data and the like, and outputs the data to the transmission buffer circuit 33 together with the header.

The transmission buffer circuit 33 temporarily stores the output data of the variable length coding circuit 30, and then sequentially outputs the data in a predetermined order.

The buffer addition circuit 34 outputs the output data of the transmission buffer circuit 33 to the error correction circuit 36.At this time, the data amount of the input / output data of the transmission buffer circuit 33 is detected, and the transmission amount is compared with the transmission speed of the line L1. When the input data amount of the buffer circuit 33 becomes extremely small, a buffer bit is inserted between the data at a predetermined timing.

The error correction circuit 36 generates a BCH code (bose chaudhuri hocquenghe) according to the output data of the staff bit addition circuit 34.
m code) is generated and added to the output data output from the staff bit adding circuit 34 and output.

Further, the error correction circuit 36 corrects the data obtained from the transmission target via the multiplex conversion circuit 38 based on the BCH code transmitted by being added to the data, so that even if an error occurs during transmission, Image quality degradation can be effectively avoided.

The multiplex conversion circuit 38 multiplexes the digital audio signal with the output data of the error correction circuit 36, and then sends out the multiplexed data to the line L1.

Thereby, the video signal _SV and the audio signal can be efficiently transmitted to the transmission target.

At the same time, the multiplex conversion circuit 38 inputs data transmitted from the transmission target via the line L1, and separates the multiplexed video signal and digital audio signal.

Further, the separated digital audio signal is output to a predetermined decoding circuit, and the video signal is subjected to a staff bit removing circuit.
Output to 40.

The stuff bit removing circuit 40 removes the stuff bit inserted by the stuff bit adding circuit 34 on the transmission target side.

The buffer circuit 42 temporarily stores the data from which the stuff bit has been removed, and then separates the header and outputs it to the decoding circuit 44.

The decoding circuit 44 performs the reverse process of the variable length coding circuit 30 on the transmission target side.

The inverse requantization circuit 46 performs an inverse requantization process on the output data of the decoding circuit 44 based on the header input via the decoding circuit 44, thereby re-quantizing the output data on the transmission target side. The input data of the quantization circuit 24 is reproduced.

The discrete cosine inverse transform circuit 48 processes the output data of the inverse requantization circuit 46 based on the header in the same manner as the discrete cosine inverse transform circuit 28, thereby performing the discrete cosine transform processing on the transmission target side. Reproduce the data.

The decoder circuit 50 executes the same processing as that of the decoder circuit 18 based on the transmitted header, and thereby reproduces the encoded image data on the transmission target side.

The video signal processing circuit 52 uses an interpolation calculation method,
After the inverse processing of the video signal processing circuit 14 is performed, the resulting video signal is output to the monitor device 54, whereby the video of the communication target transmitted from the transmission target can be monitored.

(G1-1) Image superimposition processing part As shown in FIG. 3, in this embodiment, the video signal processing circuits 14 and 52 and the decoder circuit 18 transmit the image transmitted from the transmission target to the transmission target. Combine with the image.

Specifically, in the video signal processing circuit 14 converts the video signal S _V to the luminance signal and the color difference signal into a digital signal by the analog-to-digital converter (A / D) 60.

Further, the color difference signal is time-division multiplexed every other sampling, and the high frequency is suppressed by the pre-filter circuit 61 together with the luminance signal, and is stored in the frame memory circuit 63.

The line number conversion circuit 64 sequentially reads out the image data stored in the frame memory circuit 63 in the vertical scanning direction, creates image data using an interpolation calculation method, and
Convert the number of 5 lines into the number of 180 lines.

The frame memory circuit 66, after storing the image data sequentially outputted from the line number conversion circuit 64 temporarily, outputs in a predetermined order, thereby raster scan from sequential order the sequence of image data D _IN in the vertical scanning direction And outputs it to the motion vector detection circuit 16.

Thus, in the motion vector detecting circuit 16, it takes in the image data D _IN outputted from the frame memory circuit 66, after dividing the macro block unit, is adapted to detect the motion vector.

Further, the frame memory circuit 66 samples the stored image data and outputs it to the selection circuit 88.

Thereby, the frame memory circuit 66 thins out the image data to be output to the motion vector detection circuit 16 and sends it out.For example, the image data DF1 in which the number of pixels is reduced to 1/3 in the horizontal and vertical scanning directions is _supplied to the selection circuit 88. Output.

In this case the frame memory circuit 66 outputs the image data D _F1 in synchronization with the timing of the image data D _F3 output from the decoder circuit 50.

Further, at this time, the frame memory circuit 66 stores the image data.
The image formed by the D _F3, and outputs the image data D _F1 at the timing when the image data D _F3 of the lower right corner of the image is output.

On the other hand, as shown in FIG.
_{Supplies the} image data D _HND and D _Z output from the discrete cosine inverse conversion circuit 28 to the addition circuit 70.

Further, by detecting the header D _NET , the decoder circuit 18 switches the contact points of the selection circuits 72 and 74 in accordance with the identification data of the inter-frame encoding processing and the intra-frame processing, and the on / off information of the loop filter circuit, whereby the encoding is performed. And reproduces the image data subjected to the conversion processing.

That is, when processing image data that has been subjected to intra-frame encoding processing, the decoder circuit 18 selects the ground-side contact of the selection circuit 72.

Thus, in the image data D _IND which is reproduced in the discrete cosine inverse transform circuit 28, adder circuit 70, is stored in the frame memory circuit 78, 80 and 82 via the Kuritsupingu circuit 76.

On the other hand, when processing interframe encoded image data, the decoder circuit 18 selects the contact of the selection circuit 72 on the selection circuit 74 side.

Accordingly, the selection circuit 72 outputs the image data output from the frame memory circuit 82 at a timing shifted by the motion vector _DUG to the addition circuit 70 via the loop filter circuit 84 or the register circuit 86.

Therefore, the difference data D _Z reproduced by the discrete cosine inverse transform circuit 28 is shifted by the motion vector D _UG and read out from the frame memory circuit 82 by 1.
After being added to the image data before the frame by the adding circuit 70,
The image data is stored in the frame memory circuits 78, 80 and 82, whereby the original image data can be reproduced.

At this time, in the selection circuit 74, the difference data creation circuit 20
When the loop filter circuit is selected, the control is performed so as to select the contact point on the loop filter circuit 84 side when reproducing the corresponding image data, whereby the high frequency band is suppressed based on the image data of the previous frame. The original image data is reproduced.

Thus the difference data D _Z created through a loop filter circuit can be reproduced through the loop filter circuit 84, it can be made inconspicuous boundary macro blocks.

When the inter-frame coding process is repeated by setting the frame one frame before as the reference frame, erroneous data may be generated due to accumulation of requantization errors and the like.

For this reason, when the clipping circuit 76 obtains, for example, negative addition data that is not used in the video signal transmission device 10 via the addition circuit 70, the clipping circuit 76 clips this to a value of 0, thereby accumulating the error. Thus, it is possible to effectively avoid the image quality deterioration due to.

On the other hand, the frame memory circuit 78 temporarily stores the image data obtained via the adding circuit 70, and then, based on the address data output from the motion vector detecting circuit 16, sends it to the motion vector detecting circuit 16 in block group units. To output.

Thus, the motion vector detection circuit 16 can sequentially detect motion vectors based on the reproduced image data _DSV .

On the other hand, the frame memory circuit 80 samples the stored image data and outputs it to the selection circuit 88.

Thus the frame memory circuit 80, and sends it decimated reproduced image data D _SV, for example, and outputs the image data D _F2 with a reduced number of pixels to 1/3 in the horizontal and vertical scanning direction to the selection circuit 88.

The time frame memory circuit 80 outputs the image data D _F2 in synchronism with the timing of the image data D _F3 output from the decoder circuit 50.

Further, at this time, the frame memory circuit 80 stores the image data.
The image formed by the D _F3, and outputs the timing image data D _F2 which image data D _F3 of the lower right corner of the image is output.

Thus, in the selection circuit 88, the frame memory circuit
Encoding the previous image data D _F1 stored in 66, the image data D _F3 which is reproduced stored in the frame memory circuit 80 can be selectively output.

Here, the selection circuit 88 switches contacts in response to the operation of a predetermined operation element, and outputs the selected output to the video signal processing circuit 52.
Output to

In the video signal processing circuit 52, the frame memory circuit circuit 90 includes the image data D output from the decoder circuit 50.
After fetching _F3 , the image data is converted into continuous image data in the vertical scanning direction and output.

Further, when a predetermined operator is turned on, the frame memory circuit 90 replaces the image data D _F3 or D _F1 or D _F3 with the timing at which the selection circuit 88 outputs the image data D _F1 or D _F2. Capture _F2 .

In accordance connexion frame memory circuit circuit 90, the lower right corner of the image formed by the image data D _F3, the image can be obtained image data arranged to be formed by the image data D _F1 or D _F2.

The line number inverse conversion circuit 91 processes the image data output from the frame memory circuit 90 by using an interpolation operation method in the reverse manner to the line number conversion circuit 64, thereby reducing the 180 line number to 525 line numbers. Convert to a number.

The frame memory circuit 92 temporarily stores the image data sequentially output from the line number inverse conversion circuit 91, and then outputs the image data in a predetermined order, thereby arranging the image data successively in the vertical scanning direction in the raster scanning order. Change.

The post-filter circuit 93 emphasizes the high frequency range of the image data, contrary to the pre-filter circuit 61.

The video signal processing circuit 52 includes, among the emphasized image data,
After the time-division multiplexed color difference signal is returned to the original arrangement, it is output to a digital / analog conversion circuit (D / A) 94 together with the luminance signal.

Thereby, the image data stored in the frame memory circuit 90 can be converted into the video signal _SVOUT and output, and the image of the caller can be displayed in the lower right corner of the image transmitted from the transmission target.

Thus, the image transmitted from the transmission target and the image transmitted to the transmission target can be simultaneously monitored without using a circuit dedicated to image synthesis such as the picture-in-picture circuit 1, and the entire configuration is accordingly increased. Can be simplified to improve usability.

Further, at this time, by switching the contacts of the selection circuit 88, the captured image and the image displayed on the transmission target can be selectively displayed as necessary, and the usability of the video signal transmission device 10 is improved accordingly. be able to.

Thus, in this embodiment, analog-to-digital conversion circuit 60, while constituting an analog-digital converting circuit for converting an input video signal S _V to the digital video signal, the video signal processing circuit 14, a digital video signal first stored in the frame memory circuit 66 thins out by connexion the digital video signal to be read out at a predetermined timing constituting the format conversion circuit for converting the image data D _iN given the format.

Further, the motion vector detection circuit 16 calculates the motion vector D _UG of the image data D _IN based on the predetermined reference image data D _SV.
A motion vector detection circuit that detects
Discrete cosine transform circuit 22, requantization circuit 28
Constitutes an encoding circuit that encodes the image data D _IN based on the motion vector D _UG to generate transmission data.

Further, the inverse requantization circuit 26, the discrete cosine inverse transform circuit 28 and the decoder circuit 18 decode the transmission data and store it in the second frame memory circuits 78 and 80. A transmission decoder circuit that outputs the D _SV to the motion vector detection circuit 16 is configured, and the corresponding inverse requantization circuit 46, discrete cosine inverse transformation circuit 48, and decoder circuit 50 transmit transmission data arriving from the transmission target. To decode the received image data D _F3
Is formed.

Further, the video signal processing circuit 52 receives the received image data D _F3
Is stored in the third frame memory circuit 90, and is read out at a predetermined timing to obtain the reception image data _DF3.
To form a digital video signal format and convert it to a digital video signal format, and output a received digital video signal to form a format inverse conversion circuit 52.
Constitutes a digital-to-analog conversion circuit for converting a received digital video signal into an analog signal.

In operation the above configuration of (G2) embodiment, the video signal S _V outputted from the television camera 12, the video signal processing circuit 14, after being converted into digital signals, a frame memory circuit 63, the line number conversion circuit 64 and the line number in the frame memory circuit 66 is converted is converted into image data D _iN CCITT recommendation Fomatsuto.

At this time, from the frame memory circuit 66, the image data D _IN continuous in the raster scanning order is transferred to the motion vector detection circuit 16.
Is output to the image data D _F1 sampled processed based on the image data D _F3 output from the decoder circuit 50 is output to the selection circuit 88.

Image data D _IN, after the sequence of image data has been rearranged by the motion vector detection circuit 16, motion vector for each macro block is detected.

Here, based on the detected motion vector, the comparison reference image data _DPRI is generated, and the image data _DPRI is output to the difference data creation circuit 20 together with the image data _DIND .

In the difference data creation circuit 20, the intra-frame encoding process is selected at a predetermined frame cycle. In the intra-frame encoding process, the image data D _IND is directly output to the discrete cosine transform circuit 22.

On the other hand, in the inter-frame encoding process, the image data D _PRI is subtracted from the image data D _IND to obtain the difference data D _Z.
There is created, the difference data D _Z is output to the discrete cosine transform circuit 22.

As a result, the transformed data D _DCT is obtained through the discrete cosine transform circuit 22, the transformed data D _DCT is re-quantized by the re-quantizing circuit 24, and then the variable-length coding circuit is transformed through the buffer circuit 32. The data is subjected to variable-length encoding at 30, and its output data is sequentially sent to a transmission target via a transmission buffer circuit 33, a stuff data addition circuit 34, an error correction circuit 36, and a multiplex conversion circuit 38.

Further, output data of the requantization circuit 24 is input to the decoder circuit 18 via the inverse requantization circuit 26 and the inverse discrete cosine transform circuit 28 in order.

Here, the image data D _INV transmitted after being subjected to the intra-frame encoding processing is directly stored in the frame memory circuits 78, 80, and 82, whereas the transmitted and difference data D _Z subjected to the inter-frame encoding processing is transmitted. In, the adder 70 adds the image data of one frame before the frame whose timing is shifted by the amount of the motion vector, and then adds the frame memory 78, 80, 82
Is stored in

The image data stored in the frame memory circuit 78 is output as image data _DSV of a reference frame for detecting a motion vector, while the image data stored in the frame memory circuit 82 is used to reproduce image data of a subsequent frame. Is output to the adder circuit 70.

This image data stored in the frame memory circuit 80 with respect to, based on the image data D _F3 is outputted to the selection circuit 88 is sampling.

In the image data D _F1 and D _F2 output to the selection circuit 88, the frame memory circuit 90 is synchronized with the image data D _F3.
Is output to the frame memory circuit 90.
An image lower right corner of which is formed by the image data D _F3, the image data which includes image formed by the image data D _F1 or D _F2 is stored.

The image data is converted into a video signal _SVOUT through a post-filter circuit 93 and a digital-to-analog conversion circuit 94 after the number of lines is converted by a line-number inverse conversion circuit 91 and a frame memory circuit 92. 54
The image of the caller can be displayed in the lower right corner of the image transmitted from the transmission target via the.

(G3) Effect of Embodiment According to the above configuration, the image data stored in the frame memory circuit 66 for format conversion of image data or the frame memory circuit 80 for motion vector detection is sampled, and Output image data D
Frame memory circuit 90 for format inverse transformation with _F3
, The image to be transmitted and the image to be transmitted can be simultaneously displayed with a simple configuration.

(G4) Other Embodiments In the above-described embodiment, the case where a captured image or an image displayed as a transmission target is selected and displayed together with the transmitted image has been described, but the present invention is not limited thereto. Instead, only one of them may be displayed.

At this time, for example, when displaying a captured image, instead of transferring the image data from the frame memory circuit 66 to the frame memory circuit 90, the image data may be transferred from the frame memory circuit 63 to the frame memory circuit 92. .

Further, in the above-described embodiment, the case where the present invention is applied to a video signal transmission device that transmits a video signal together with an audio signal has been described. For transmission, it can be widely applied to recording on a recording medium.

H Effects of the Invention As described above, according to the present invention, image data stored in a frame memory circuit for format conversion of a video signal or motion vector detection is transferred to a received frame memory circuit for storing image data. By synthesizing the images, a video signal transmission device capable of simultaneously monitoring the image transmitted from the transmission target and the image transmitted to the transmission target with a simple configuration can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a video signal transmission apparatus according to an embodiment of the present invention, FIG. 2 is a schematic diagram for explaining the operation of a motion vector detection circuit, and FIG. 3 is a block diagram showing an image superimposition processing portion. FIG. 4 is a block diagram showing a decoder circuit;
FIG. 5 is a block diagram showing a conventional image synthesizing method, and FIG. 6 is a schematic diagram showing the synthesized image. 10 video signal transmission device, 14, 52 video signal processing circuit, 16 motion vector detection circuit, 18, 50 decoder circuit, 60 analog digital conversion circuit, 63, 66, 7
8, 80, 82, 90, 92 ... frame memory circuit, 94 ... digital analog conversion circuit.

Claims (1)

(57) [Scope of request for utility model registration] An analog-to-digital conversion circuit for converting an input video signal into a digital video signal; and storing the digital video signal in a first frame memory circuit and reading the digital video signal at a predetermined timing to convert the digital video signal into digital video signals. A format conversion circuit for thinning out and converting the image data into a predetermined format image data; a motion vector detection circuit for detecting a motion vector of the image data based on predetermined reference image data; and An encoding circuit for performing an encoding process to generate transmission data; decoding the transmission data and storing the decoded data in a second frame memory circuit, and then reading out the reference image data at a predetermined timing to the motion vector detection circuit; Output transmission decoder circuit and decode transmission data coming from the transmission target A receiving decoder circuit for generating received image data by storing the received image data in a third frame memory circuit, and then reading out the received image data at a predetermined timing to interpolate the received image data so as to interpolate the digital video data. A format inverse conversion circuit for converting the received digital video signal into an analog signal, and a digital-to-analog conversion circuit for converting the received digital video signal into an analog signal. When storing the reference image data at a predetermined timing instead of the received image data, the image data output from the first frame memory circuit or the reference image data output from the second frame memory circuit at a predetermined timing. By storing, the first frame is added to a part of the image of the received image data. Video signal transmission apparatus characterized by displaying an image of the reference image data output from the image or the second frame memory circuit of the image data output from the frame memory circuit.