JPH03188769A - Picture quality adjustment circuit - Google Patents

Picture quality adjustment circuit

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Publication number
JPH03188769A
JPH03188769A JP1327297A JP32729789A JPH03188769A JP H03188769 A JPH03188769 A JP H03188769A JP 1327297 A JP1327297 A JP 1327297A JP 32729789 A JP32729789 A JP 32729789A JP H03188769 A JPH03188769 A JP H03188769A
Authority
JP
Japan
Prior art keywords
signal
circuit
video signal
level
contour
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1327297A
Other languages
Japanese (ja)
Inventor
Isakiyo Matsuyanagi
松柳 勇精
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP1327297A priority Critical patent/JPH03188769A/en
Publication of JPH03188769A publication Critical patent/JPH03188769A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To attain contour emphasis processing in response to S/N of an input video signal by varying the degree of contour emphasis of the video signal in response to a difference between a white peak level and a black peak level of the input video signal. CONSTITUTION:An adder circuit 8 adds a level control signal D at a prescribed level outputted from a level control circuit 9 and an addition detection signal G and an addition signal obtained from the adder circuit 8 is fed to a contour extraction circuit 3 as a gain control signal D'. The gain control of the contour signal is implemented based on the gain control signal D' outputted from the gain control circuit comprising the adder circuit 8 and the level control circuit 9 by the circuit 3. Even when a video signal with low S/N and much noise is inputted, the contour emphasis processing is implemented to a degree not causing displeasure. Then when the video signal A with excellent S/N is inputted to the input terminal 1, the video signal C improving the sharpness of the picture more is extracted from an output terminal 4.

Description

【発明の詳細な説明】 [発明の目的j (産業上の利用分野) 本発明は、テレビジョン受像機やビデオテープレコーダ
(VTR)などにおいて映像信号の輪郭部分を強調して
画質の改善を行なうための画質調整回路に関する。
[Detailed Description of the Invention] [Objective of the Invention j (Industrial Application Field) The present invention improves image quality by emphasizing the contours of video signals in television receivers, video tape recorders (VTRs), etc. This invention relates to an image quality adjustment circuit.

(従来の技術) 一般にテレビジョン受像機やVTRなどの信号処理回路
には、輪郭強調処理を行なって画像の鮮明度を高めるた
めの画質調整回路が設けられている。 第4図に、この
ような画質調整回路の従来例を示す。
(Prior Art) Generally, a signal processing circuit such as a television receiver or a VTR is provided with an image quality adjustment circuit for performing edge enhancement processing to improve the clarity of an image. FIG. 4 shows a conventional example of such an image quality adjustment circuit.

この図で、入力端子11に入力される映像信号aは、輪
郭抽出回路13と加算回路12の一方の入力端子とに供
給される。輪郭抽出回路13では、入力される映像信号
aの輪郭部分(エツジ部)P(第5図参照)の抽出が行
なわれ、抽出された輪郭信号がレベルコントロール回路
19により適度なレベルに制御されたのち、加算回路1
2の他方の入力端子に供給される。ここで、輪郭抽出回
路13は二次微分回路やデイレイラインなどから構成さ
れる。
In this figure, a video signal a input to an input terminal 11 is supplied to an outline extraction circuit 13 and one input terminal of an addition circuit 12. The contour extraction circuit 13 extracts the contour portion (edge portion) P (see FIG. 5) of the input video signal a, and the extracted contour signal is controlled to an appropriate level by the level control circuit 19. Later, adder circuit 1
2 is supplied to the other input terminal of 2. Here, the contour extraction circuit 13 is composed of a second-order differential circuit, a delay line, and the like.

加算回路12では、原映像信号aと輪郭信号すとが加算
され、出力端子14からは輪郭強調処理された映像信号
Cが取り出される。
In the adder circuit 12, the original video signal a and the contour signal S are added, and from the output terminal 14, a video signal C subjected to contour enhancement processing is taken out.

第5図は、この画質調整回路の各部の信号波形を示した
ものであり、(a>の波形は入力映像信号a、<b>の
波形は輪郭信号b、(c)の波形は画質調整後の出力映
像信号Cをそれぞれ示す。
Figure 5 shows the signal waveforms of each part of this image quality adjustment circuit, where the waveform in (a) is the input video signal a, the waveform in <b> is the contour signal b, and the waveform in (c) is for the image quality adjustment. The subsequent output video signals C are shown respectively.

(発明が解決しようとする課題) ところで、輪郭強調処理を行なう上述した従来の画質調
整回路は、高域強調回路であって、ノイズ成分までも強
調されてしまうことから、出力信号CのSiN比が低下
してしまうという問題点があった。
(Problem to be Solved by the Invention) By the way, the above-mentioned conventional image quality adjustment circuit that performs edge enhancement processing is a high frequency enhancement circuit, and even noise components are emphasized, so the SiN ratio of the output signal C is There was a problem in that the value decreased.

このため、輪郭を強調する量はS/′N比の悪い信号が
入力された場合でも見苦しくない程度にあらかじめ抑え
ておくか、そのような信号が入力された場合にはそのつ
どレベルを小さくしなければならなかった。・したがっ
て、比較的S / N比の良い信号に対しての輪郭強調
量は必ずしし適切な設定とはなっておらず、常に鮮明な
画像が得られるとは限らなかった。
Therefore, the amount of contour enhancement should be limited in advance to a level that does not make the image unsightly even when a signal with a poor S/N ratio is input, or the level should be reduced each time such a signal is input. I had to. - Therefore, the amount of edge enhancement for a signal with a relatively good S/N ratio was not always set appropriately, and a clear image was not always obtained.

本発明は、このような課題を解決するために提案された
ものであり、入力映像信号のS/N比の程度によらず最
適な輪郭強調処理を行なうことができる画質調整回路を
提供することを目的とする。
The present invention has been proposed in order to solve such problems, and an object of the present invention is to provide an image quality adjustment circuit that can perform optimal edge enhancement processing regardless of the degree of S/N ratio of an input video signal. With the goal.

「発明の構成] (課題を解決するための手段) 上記目的を達成するなめに本発明による画質調整回路は
、入力映像信号のエツジ部を検出して輪郭信号を抽出す
る輪郭抽出回路と、上記入力映像信号の白ピークレベル
と黒ピークレベルとを検出してこれら白ピークレベルと
黒ピークレベルの差に対応した検出信号を出力するレベ
ル検出回路と、このレベル検出回路から出力される上記
検出信号に基づいて上記輪郭信号のゲインを制御するゲ
インコントロール回路と、上記入力映像信号にゲイン制
御後のこの輪郭信号を加算する加算回路とを備えること
を特徴とする。
"Structure of the Invention" (Means for Solving the Problems) In order to achieve the above object, an image quality adjustment circuit according to the present invention includes a contour extraction circuit that detects edge portions of an input video signal and extracts a contour signal; A level detection circuit that detects a white peak level and a black peak level of an input video signal and outputs a detection signal corresponding to the difference between these white peak level and black peak level, and the detection signal outputted from this level detection circuit. The present invention is characterized by comprising a gain control circuit that controls the gain of the contour signal based on the above, and an addition circuit that adds the gain-controlled contour signal to the input video signal.

(作用) 上述した構成によれば、白ピークレベルと黒ピークレベ
ルの差に対応した上記検出信号に基づいて輪郭信号のゲ
インを制御しているので、入力映像信号のS/N比に応
じた輪郭強調処理を行なうことができる。
(Function) According to the above-described configuration, since the gain of the contour signal is controlled based on the detection signal corresponding to the difference between the white peak level and the black peak level, the gain of the contour signal is controlled according to the S/N ratio of the input video signal. Contour enhancement processing can be performed.

したがって、ノイズの多い入力映像信号についてはS 
、/′N比が悪くならないように輪郭強調の度合を抑え
られるとともに、S /’ N比の良い入力映像信号に
対しては輪郭強調の度合を高めた信号処理を行なうこと
ができる。
Therefore, for a noisy input video signal, S
, /'N ratio is not deteriorated, and it is also possible to perform signal processing with a high degree of edge emphasis on an input video signal with a good S/'N ratio.

(実施例) 以下、本発明の実施例を図面に基づき詳細に説明する。(Example) Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

第1図のブロック図は、本発明による画質調整回路の一
実施例を示す。
The block diagram of FIG. 1 shows one embodiment of an image quality adjustment circuit according to the present invention.

この図で、入力端子1に入る入力映像信号Aは、加算回
路2に供給されるとともに、輪郭抽出回路3に供給され
て輪郭部分(エツジ部)の抽出が行なわれる。加算回路
2では、入力映像信号に輪郭抽出回路3から出力される
ゲイン制御後の輪郭信号Bが加算され、輪郭部分が強調
された映像信号Cが出力端子4から取り出される。
In this figure, an input video signal A that enters an input terminal 1 is supplied to an adder circuit 2 and also to a contour extraction circuit 3, where a contour portion (edge portion) is extracted. In the adder circuit 2, the gain-controlled contour signal B output from the contour extraction circuit 3 is added to the input video signal, and a video signal C in which the contour portion is emphasized is taken out from the output terminal 4.

一方、上記入力映像信号は白ピーク検出回路5と黒ピー
ク検出回路6とに供給され、これら検出回路5,6で検
出された白ピーク検出信号Eと黒ピーク検出信号Fとが
加算回路7で加算されたのちに、この加算検出信号Gが
加算回路8に供給される。なお、白ピーク検出回路5、
黒ピーク検出回F1116および加算回#I7は、白ピ
ークレベルと黒ピークレベルの差に対応した検出信号G
を出力するレベル検出回路を構成する。
On the other hand, the input video signal is supplied to a white peak detection circuit 5 and a black peak detection circuit 6, and a white peak detection signal E and a black peak detection signal F detected by these detection circuits 5 and 6 are added to an adder circuit 7. After the addition, this addition detection signal G is supplied to the addition circuit 8. Note that the white peak detection circuit 5,
The black peak detection circuit F1116 and the addition circuit #I7 detect the detection signal G corresponding to the difference between the white peak level and the black peak level.
Configure a level detection circuit that outputs.

上記加算回88では、レベルコントロール回路9から出
力される所定レベルのレベルコントロール信号りと加算
検出信号Gとが加えられ、加算回路8から得られる加算
信号がゲインコントロール信号り一として輪郭抽出回路
3に供給される。この輪郭抽出回路3では、加算回路8
とレベルコントロール回路9とからなるゲインコントロ
ール回路から出力されるこのゲインコントロール信号り
一に基づいて輪郭信号のゲイン制御が行なわれる。
In the addition circuit 88, the level control signal of a predetermined level outputted from the level control circuit 9 and the addition detection signal G are added, and the addition signal obtained from the addition circuit 8 is used as a gain control signal to feed the contour extraction circuit 3. is supplied to In this contour extraction circuit 3, the addition circuit 8
Gain control of the contour signal is performed based on this gain control signal outputted from a gain control circuit consisting of a level control circuit 9 and a level control circuit 9.

このように構成される画質調整回路では、通常レベルコ
ントロール回路9であらかじめ設定されている所定レベ
ル(たとえば3dBアツプ)のコントロール信号りがほ
ぼ輪郭抽出回路3に供給され、このレベルコントロール
信号りによって輪郭信号のレベルの調整が行なわれるの
で、S、/N比が低いノイズの多い映像信号が入力され
た場合でも見苦しくない程度に輪郭強調処理を行なうこ
とができる。
In the image quality adjustment circuit configured as described above, a control signal of a predetermined level (for example, 3 dB up), which is normally set in advance by the level control circuit 9, is supplied to the contour extraction circuit 3, and the contour is determined by this level control signal. Since the signal level is adjusted, even if a noisy video signal with a low S/N ratio is input, contour enhancement processing can be performed to a degree that does not make the image unsightly.

ここで、一般に2〜3MHzの周波数信号のレベルを高
めると輪郭強調の効果が大きいが、アップするレベルを
3dB以内にしておけば、ノイズの多い映像信号に対し
ても輪郭強調処理後のS/N比の劣化はそれ稚気になら
ない。
Generally speaking, increasing the level of the 2 to 3 MHz frequency signal will have a great effect on edge enhancement, but if the increased level is kept within 3 dB, the S/R after edge enhancement processing will improve even for noisy video signals. The deterioration of the N ratio is not childish.

つぎに、S/N比の良い映像信号Aが、入力端子1に入
力される場合について説明する。
Next, a case will be described in which a video signal A with a good S/N ratio is input to the input terminal 1.

まず、白ピーク検出回路5では白ピークを検出するにあ
たり、第2図に示すように映像信号Aの同期信号syの
先端を一定電圧にクランプし、映像信号レベルが100
%を越える白ピーク部分(斜線を付した部分)mを検波
して、この白ピーク部分mに比例する直流電圧信号を作
り出す。この直流電圧信号が白ピーク検出信号Eに相当
する。
First, in detecting a white peak, the white peak detection circuit 5 clamps the leading end of the synchronizing signal sy of the video signal A to a constant voltage as shown in FIG.
% (shaded area) m is detected, and a DC voltage signal proportional to this white peak portion m is generated. This DC voltage signal corresponds to the white peak detection signal E.

また、黒ピーク検出回路6では黒ピークを検出するにあ
たり、まず第3図(a)の入力映像信号Aを第3図(b
)に示すように反転し、ペデスタル部分をクランプする
。続いて第3図(C)に示すように同期信号syの部分
をブランキングしたあとに、映像信号レベルが20%レ
ベルより低い黒ピーク部分く斜線を付した部分)nを検
波し、この黒ピーク部分nに比例する直流電圧信号を得
、黒ピーク検出信号Fとして出力する。
In addition, when detecting a black peak, the black peak detection circuit 6 first converts the input video signal A shown in FIG. 3(a) into the input video signal A shown in FIG.
) and clamp the pedestal part as shown. Next, as shown in Fig. 3(C), after blanking the part of the synchronizing signal sy, the black peak part (shaded part) where the video signal level is lower than the 20% level is detected, and this black peak is detected. A DC voltage signal proportional to the peak portion n is obtained and output as a black peak detection signal F.

得られた白ピーク検出信号Eと黒ピーク検出信号Fとは
、加算回路7で加算される。このとき、映像信号の平均
輝度が高い方がS/N比も高くノイズが目立ちにくいこ
とから、2つのピーク検出信号を加算するにあたり、白
ピーク検出信号Eの方が大きい場合、加算出力が大きく
なるように白ピーク検出信号Eに重みを付けて加算する
。このようにして得られた加算検出信号Gは、白ピーク
と黒ピークの差に対応しており、この加算検出信号Gが
大きい程、映像信号Aの白ピークから黒ピークまでのレ
ベルが大きく、信号のS/N比が高いことを示しており
、信号にめりはりがある。このような映像信号Aに対し
ては、輪郭強調量を多くすることで画像の鮮明度の向上
が期待できる。
The obtained white peak detection signal E and black peak detection signal F are added by an adding circuit 7. At this time, when the average brightness of the video signal is higher, the S/N ratio is higher and noise is less noticeable. Therefore, when adding the two peak detection signals, if the white peak detection signal E is larger, the addition output will be larger. The white peak detection signal E is weighted and added so that The addition detection signal G obtained in this way corresponds to the difference between the white peak and the black peak, and the larger the addition detection signal G is, the higher the level from the white peak to the black peak of the video signal A is. This indicates that the S/N ratio of the signal is high, and the signal is sharp. For such a video signal A, it is expected that the sharpness of the image will be improved by increasing the amount of edge enhancement.

上記加算検出信号Gは、レベルコントロール回路9から
供給される一定レベルのコントロール信号りと加算回路
8で加算されて、輪郭抽出回路3にゲインコントロール
信号D゛として供給されるので、S/N比の高い映像信
号Aに対してはレベルコントロール回路9であらかじめ
設定されている輪郭強調量よりも大きな度合で輪郭強調
処理を行なうことができ、画像の鮮明度をより高めた映
像信号Cを出力端子4より取り出すことができる。
The addition detection signal G is added to a constant level control signal supplied from the level control circuit 9 in the addition circuit 8, and is supplied to the contour extraction circuit 3 as a gain control signal D', so that the S/N ratio is For video signal A with a high level of contrast, the level control circuit 9 can perform edge enhancement processing to a greater degree than the amount of edge enhancement preset, and output the video signal C with higher image clarity to the output terminal. It can be extracted from 4.

[発明の効果] 以上説明したように本発明によれば、入力映像信号の白
ピークレベルと黒ピークレベルの差に応じて、映像信号
の輪郭強調の度合を変えられるようにしたので、ノイズ
の多い映像信号に対してはS、/N比が悪化しないよう
に輪郭強調量を抑えられるとともに、S/N比の良好な
映像信号に対しては輪郭強調量を増やして、より鮮明な
画像が得られるよう画質の調整を行なうことができる。
[Effects of the Invention] As explained above, according to the present invention, the degree of edge enhancement of the video signal can be changed according to the difference between the white peak level and the black peak level of the input video signal. The amount of edge enhancement can be suppressed for video signals with a large number of signals so as not to deteriorate the S/N ratio, and the amount of edge enhancement can be increased for video signals with a good S/N ratio to produce a clearer image. You can adjust the image quality to achieve the desired result.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による画質調整回路の一実施例を示すブ
ロック図、第2図は第1図の画質調整回路を構成する白
ピーク検出回路の動作を説明するための波形図、第3図
は第1図の画質調整回路を構成する黒ピーク検出回路の
動作を説明するための波形図、第4図は従来の画質調整
回路を示すブロック図、第5図は従来の画質調整回路の
動作を説明するための波形図である。 2.7.8・・・加算回路 3・・・輪郭抽出回路 5・・・白ピーク検出回路 6・・・黒ピーク検出回路 9・・・レベルコントロール回路 m・・・白ピーク部分 n・・・黒ピーク部分
FIG. 1 is a block diagram showing an embodiment of the image quality adjustment circuit according to the present invention, FIG. 2 is a waveform diagram for explaining the operation of the white peak detection circuit that constitutes the image quality adjustment circuit of FIG. 1, and FIG. is a waveform diagram for explaining the operation of the black peak detection circuit that constitutes the image quality adjustment circuit in Figure 1, Figure 4 is a block diagram showing the conventional image quality adjustment circuit, and Figure 5 is the operation of the conventional image quality adjustment circuit. FIG. 2 is a waveform diagram for explaining. 2.7.8...Addition circuit 3...Contour extraction circuit 5...White peak detection circuit 6...Black peak detection circuit 9...Level control circuit m...White peak portion n...・Black peak part

Claims (1)

【特許請求の範囲】[Claims]  入力映像信号のエッジ部を検出して輪郭信号を抽出す
る輪郭抽出回路と、上記入力映像信号の白ピークレベル
と黒ピークレベルとを検出してこれら白ピークレベルと
黒ピークレベルの差に対応した検出信号を出力するレベ
ル検出回路と、このレベル検出回路から出力される上記
検出信号に基づいて上記輪郭信号のゲインを制御するゲ
インコントロール回路と、上記入力映像信号にゲイン制
御後のこの輪郭信号を加算する加算回路とを備えたこと
を特徴とする画質調整回路。
A contour extraction circuit detects the edge portion of the input video signal and extracts a contour signal, and a contour extraction circuit detects the white peak level and black peak level of the input video signal and corresponds to the difference between the white peak level and the black peak level. a level detection circuit that outputs a detection signal; a gain control circuit that controls the gain of the contour signal based on the detection signal output from the level detection circuit; and a gain control circuit that applies the gain-controlled contour signal to the input video signal. An image quality adjustment circuit comprising an addition circuit that performs addition.
JP1327297A 1989-12-19 1989-12-19 Picture quality adjustment circuit Pending JPH03188769A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1327297A JPH03188769A (en) 1989-12-19 1989-12-19 Picture quality adjustment circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1327297A JPH03188769A (en) 1989-12-19 1989-12-19 Picture quality adjustment circuit

Publications (1)

Publication Number Publication Date
JPH03188769A true JPH03188769A (en) 1991-08-16

Family

ID=18197558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1327297A Pending JPH03188769A (en) 1989-12-19 1989-12-19 Picture quality adjustment circuit

Country Status (1)

Country Link
JP (1) JPH03188769A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0638074A (en) * 1992-07-21 1994-02-10 Fujitsu General Ltd Picture quality adjusting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0638074A (en) * 1992-07-21 1994-02-10 Fujitsu General Ltd Picture quality adjusting circuit

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