JPH03181100A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To perform access while arbitrarily selecting an auxiliary circuit regardless of the presence and absence of a switch set by selecting the auxiliary circuit by setting a prescribed wiring position in an auxiliary selecting circuit at a prescribed signal level by a forced switching circuit corresponding to a forced select signal. CONSTITUTION:When a forced switching circuit 5 instructs an auxiliary selecting circuit 3 to forcedly select one of auxiliary circuits P1-Pl, according to this instruction, one of the auxiliary circuits P1-Pl is selected and the auxiliary selecting circuit 3 applies a normal decoder inactivating signal NED to a normal selecting circuit 2 and inactivates this circuit. Namely, the forced switching circuit 5 sets the prescribed wiring position in the auxiliary selecting circuit 3 at the prescribed signal level corresponding to the forced select signal and selects one of the auxiliary circuits P1-Pl. Thus, regardless of the presence/ absence of the switch set, the auxiliary circuit can be arbitrarily selected and accessed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit provided with a spare circuit for replacing a defective normal circuit.

[Conventional technology]

The invention is most applicable to semiconductor memories with spare memory cells and will therefore be described.

2. Description of the Related Art Due to miniaturization and an increase in chip size of semiconductor memories due to an increase in memory capacity, it is rapidly becoming difficult to manufacture chips without defects. Therefore, in semiconductor memory, starting in the early 1980s, several redundant rows and columns were added on the chip as spares, and the memory cells in the rows and columns containing the defective memory cells were replaced with the memory cells in the spare rows and columns. Redundant circuit technology that replaces cells is widely used.

FIG. 6 is a block diagram showing a circuit selection section in a conventional memory. The operation of the conventional circuit will be explained based on this figure. First, the operation when there is no defect in the normal circuits N1 to Nl11 will be described. If there is no defect, switching circuit 4
Therefore, the preselection pl path 3 is inactive. Therefore, the spare circuits P1 to P are not selected, and one of the normal circuits N1 to N is selected by the normal selection circuit 2 according to the output signals (address signals) A and X from the selection signal generation circuit 1. Ru.

Next, the operation when a part of the normal circuits N1 to N111 is defective will be described. At this time, when the selection signal generation circuit 1 outputs a selection signal that selects a defective normal circuit, the normal selection circuit 2 is inactivated and the preliminary selection circuit 3 is activated. Performs predetermined processing such as cutting off the fuses that make up the switching circuit. Thereby, even if a defect occurs in a part of the normal circuits N1 to Nff1, it is possible to obtain a device that operates normally.

Below, the conventional technology will be explained in more detail using the 1111 road map.

FIG. 7 is a circuit diagram of a decoder section of a conventional semi-dedicated memory path. This decoder section has a normal decoder 10 and a spare decoder 20.

In the figure, A-A is an address signal, A1 to An are I
n Its inverted signal, X and Xo are an address signal different from the above address and its inverted signal. However, the levels of these address signals and their inverted signals are set so that they are both at low level when inactive. PRE is a decoder precharge signal, and NED is a normal decoder inactivation signal.

L and Lt are lines normally selected by the decoder 10, and are usually connected to memory cells (not shown) as circuits. On the other hand, So and Sl are spare decoders 2
0, and is connected to a spare memory cell (not shown) as a spare circuit. 11 in the diagram
．． 14,15°34 is inverter, 12.13 is NOR
Gate, T~T, Tst~"s2n' Trl
'Tr3'Tr4' n T NT , T , T , T -T
r6 rlOr13 r14 rlO
rlO is an n-channel MOS transistor (rNM
It is called O3TJ. ), Tr2'Tr5' Tr12
'T represents a p-channel MO8) transistor (hereinafter referred to as 15r, PMO3TJ). Spare decoder 20
, node N2 and NMO8) transistor T-T
Between each of the fuses Ft~sl
A total of 20 pieces, one each of 52n and F2n, have been created.

In correspondence with FIG. 6, the normal selection circuit 2 corresponds to the normal decoder 10, the preliminary selection circuit 3 or the preliminary decoder 20, and the switching circuit 4 to the fuse Fl""F2n. The selection signal generation port 1 corresponds to a circuit (not shown) for generating the signal. Further, the normal four-way N - N is the line of the normal decoder 10.

The spare circuit P ``'''' P J) corresponds to the normal memory cell connected to l m Ll, and the spare circuit P ``'' P J) corresponds to the spare memory cell connected to the lines So and Sl of the spare decoder 20.

FIG. 8 is a timing chart showing the operation of the decoder of FIG. 7. At time tl, precharge signal P
Since RE is at low level, transistor TT
is turned on, and the nodes Nr2' r12 1 and N2 each become high level. At time t2,
Since the precharge signal PRE becomes a low level, the transistors Tr2' to Tr12 are turned off, and the transistors Trl' to Trlo are turned on.

At time t3, among the plurality of sets of normal decoders 10 in the decoder section, in the decoder 10 to which the address signals A1 to An that turn off all the transistors TI-Tn are input, the node N1 maintains a high level. do. On the other hand, in other decoders 10, the node N1 becomes low level.

Normally, if there is no defect in the decoder 10, the fuse F-F
2n is not disconnected, the node N of the backup decoder 20
2 becomes low level and the normal decoder inactivation signal NED
is also at low level. Therefore, at time t4, both lines S and Sl in the preliminary decoder 10 become low level. Further, since the normal decoder inactivation signal NED is at a low level, the NOR gates 12 and 13 become equivalent to inverters. Therefore, among the plurality of normal decoders 10, the node N1 is the decoder 10 that maintains a zero level, and the address signals X, X that are manually input to the NOR gates 12 and 13.

The line of the decoder 10 selected by L.

Only one of them is at a high level. The lines L and L of the other decoders 10 are all at the low level.

When a defect occurs in a memory cell, the fuse corresponding to the address of the defective memory cell is cut. For example, if a defect occurs in a memory cell selected by an address input in which only the address A1 is at a low level and the other addresses A2 to Ao are at a high level, the transistor Ts2 whose gate receives the address A1 and the addresses A2 to Ao are at a high level. A is a fuse F connected to the transistor s3...Ts2n-1, which is manually powered by the gate, respectively.
Cut a total of n fuses of 2°F...F.

Therefore, at time t3, node N2 maintains a high level only when the address of the defective memory cell is input, and at time t4, address signal X or Xo becomes high level. In this case, the line So or Sl becomes high level. At this time, the decoder inactivation signal NED becomes high level, so the output x of the NOR gate 12.13
, x1 are both at low level, and 11L and L of the normal decoder 10 are both at low level. Addresses Al to A other than the address of the memory cell where the defect occurred
If it is manually operated, the node N2 becomes low level at time t3, so the operation is the same as in the case where there is no defect.

[Problem to be solved by the invention]

In this way, with the above-mentioned conventional technology, a good product can be obtained even if a part of the normal circuit is defective, but if there is a defect in the spare circuit, a good product cannot be obtained even after switching. There was a problem.

To deal with this problem, in the semiconductor circuit disclosed in Japanese Patent Application Laid-Open No. 1-130399, a spare circuit (spare memory circuit) is arbitrarily selected so that the quality of the spare circuit can be tested in advance.

However, even in this semiconductor circuit, after programming (cutting the fuse) to replace a defective normal circuit with a spare circuit, it was not possible to arbitrarily select the spare circuit.

Although the backup circuit and the normal circuit are almost equivalent, their circuit configurations are slightly different, so their operating characteristics (response speed, etc.) are usually different. Therefore, when analyzing and evaluating semiconductor circuits, there has been a desire to arbitrarily select a spare circuit that has been replaced with a normal circuit and test its characteristics.

The present invention has been made to solve the above-mentioned problems in the prior art, and provides a semiconductor integrated circuit in which a backup circuit can be arbitrarily selected and accessed regardless of the presence or absence of a switching setting for switching a normal circuit to a backup circuit. The purpose is to obtain a circuit.

[Means to solve the problem]

In order to solve the above-mentioned problems, a semiconductor integrated circuit according to the present invention includes a plurality of normal circuits, a spare circuit having the same function as the normal circuits, and a plurality of normal circuits that are selected from among the plurality of normal circuits according to a given address signal. a normal selection circuit that selects one of the normal selection circuits, and a switching element, and the switching element undergoes a predetermined process, so that the normal selection circuit selects the normal circuit according to a predetermined value of the address signal. a preliminary selection circuit that selects the preliminary circuit while blocking the
By receiving a predetermined forced selection signal and setting a predetermined wiring position in the preliminary selection circuit to a predetermined signal level in accordance with the forced selection signal, regardless of whether or not the predetermined processing is performed on the switching element, and a forced switching circuit that causes the preliminary selection circuit to select the preliminary selection circuit.

[Effect]

The forced switching circuit sets a predetermined wiring position in the preliminary selection circuit to a prescribed signal level in response to the forced selection signal, and thereby selects the preliminary circuit, regardless of whether or not the switching element is processed. You can select a spare circuit.

〔Example〕

FIG. 1 is a block diagram showing a circuit selection section in a semiconductor integrated circuit as an embodiment of the present invention. This circuit has a configuration in which a forced switching circuit 5 is added to the circuit shown in FIG.

The forced switching circuit 5 connects the preliminary selection circuit 3 to the preliminary selection circuit P −
This is a circuit that forcibly selects one of Pp.

When the forced switching circuit 5 does not instruct the preliminary selection circuit 3 to make this forced selection, the operation of the circuit selection section is the same as the conventional one. That is, when addresses A, At this time, since the preliminary selection circuit 3 is inactivated by the switching circuit 4, the preliminary selection circuits P-P,! are not selected.On the other hand, if any of the normal paths Nl-Nff1 is defective, In some cases, when the selection signal generating circuit 1 generates addresses A, R's 1
is selected. This is realized by using a square bale or the like for cutting a fuse or the like as the switching circuit 4. The P If selection circuit 3 selects one of the spare circuits P to P, and also deactivates the normal selection circuit 2 by applying a normal decoder inactivation signal NED to the normal selection circuit 2.

On the other hand, the forced switching circuit 5 switches the preliminary selection circuit 3 to the preliminary selection circuit p.
- When an instruction is given to forcibly select one of Pil, one of the preliminary circuits P1 to Pri is selected according to this instruction, and the preliminary selection circuit 3 sends the normal decoder inactivation signal NED to the normal selection circuit 2. ! ) and inactivate it.

FIG. 2 is a circuit diagram showing a decoder section of a semiconductor memory circuit as an embodiment of the present invention, and shows the normal selection circuit 2. Preliminary selection circuit 3 shows portions corresponding to switching circuit 4 and forced switching circuit 5.

A normal decoder 10 as a normal selection circuit 2 includes NMOS transistors Tl-"rn-t connected in parallel with each other.
- equipped with these NMO3I- transistors T
Each gate of -T is given an address Alin to A (or A t ""' A rI), respectively. Moreover, one common node of the NMOS transistors T t ""' T connected in parallel is,
It is grounded via the NMOS transistor Trl.

A precharge signal PRE is input to the gate of this NMO8) transistor Trl. The other common node N1 of the NMOS transistors T1 to T is connected to the PMO5, to which the precharge signal PRE is input.
) It is connected to the power supply potential VDD via the transistor Tr2. Also, node N1 is NMO3) transistor T
NMOS transistor TT through r3''r4, respectively.
It is connected to the gate r8' r7 of. NMOS transistor Tr3'T
The gates of each are connected to the power supply potential ■DD. The NMOS transistor "rB is further connected to another NMOS transistor"rB.
MO3) is grounded via transistor Tr7. Similarly, NMO5) transistor "rB" is also connected to another NM
O5) Grounded via transistor Tr9. N.M.
The gates of OS transistors Tr7 and Tr9 are each connected to node N1 via an inverter 11. Note that the output terminal of the inverter 11 is PMO5! - The gate of transistor Tr5 is also manually operated, and node N
l is the power supply potential v via this PMOS transistor T
The node between NMOS transistors Tr6 and Tr7 is connected to line L. The node between NMOS transistors Tr8 and Tr9 is connected to line L. , Lt are connected to memory cells (not shown) as a normal circuit.The address signals X and X inputted to the normal decoder 10 are as follows.
Each of them is supplied as one of the NOR gates 12 and 13 via inverters 14 and 15. A normal decoder inactivation signal NED supplied from a backup decoder 30 is inputted to the other NOR gate 12 and L3. NOR
The output signals X X of gates 12 and 13 are respectively N
MO3) Rung 12° 13 is input to Star TT.

r6' rB The spare decoder 30 includes NMO3) transistors T-T connected in series with fuses F-F2n, respectively.
Each set (Fl.

TSL) (1-1 to 2n) are connected in parallel to each other.

At the gate of the NMOS transistor T-T,
sl s2n Address A , Al, A , A , ..., A
.

1 2 2 n A is given. Among the nodes on both sides of the parallel connection, the nodes connected to the NMO3) transistors Tsl-Ts2n are grounded via the NMOS transistor T. The gate of the NMOS transistor T is connected to the output terminal of the NOR gate 35, and the NOR gate 35 is supplied with a precharge inversion signal PRE and a spare enable signal SE. The parallel connected fuse F −F2o
The side node N2 is connected to a PMOS transistor T whose gate is supplied with a spare apple inversion signal SE.
The power supply car is connected to the 11th vDD via. The other configuration of the preliminary decoder 30 is almost the same as that of the normal decoder 10.

That is, the transistor T −T provided in the preliminary decoder 30, the inverter 34, and rl2
The rl9 lines S and S1 are the transistors Tr2 to Tr9 provided in the decoder 10, the inverter 1, and the lines S and S1.
They correspond to Ll and Ll, respectively. However, transistor T
, T are directly supplied with rl6 rllt address signals X and Xo, respectively.

In terms of correspondence with FIG. 1, the normal selection circuit 2 corresponds to the normal decoder 10. Further, the forced switching circuit 5 is composed of a NOR gate 35 in the preliminary decoder 30 and a PMOS transistor T. Another circuit in the preliminary decoder 30 is the preliminary selection circuit 3.
The fuse Fl=F2n corresponds to the switching circuit 4.

In the circuit shown in FIG. 2, when the spare enable signal SE is at a low level, the spare enable inverted signal SE is at a high level, so that the transistor T in the spare decoder 30 is turned off.

ll At this time, since the NOR gate 35 functions as an inverter, rl is applied to the gate of the transistor T.

The precharge signal PRE is manually input. The operation at this time is the same as that of the conventional circuit shown in FIG.

When the spare enable signal SE is at a high level, the spare enable inverted signal SE is at a low level, so the transistor T is always on and TrlOll is always off. Regardless of the level I n of A, the node N2 is always at a high level. Further, the normal decoder inactivation signal NEC also becomes high level. Therefore, the output of NOR gate 1213
is always at a low level, and both lines L and L of the normal decoder 10 are maintained at a low-low level. On the other hand, the line S of the spare decoder 3o
, S to the address signals X and X.
One line selected from 0 0 becomes high level. In this way, the forced switching circuit 5 composed of the transistor T and the NOR circuit 35 forcibly sets the node N2 to a high level in response to the spare enable signal SE, so that the fuses F1 to F2n are disconnected. Regardless, it is possible to select the spare decoder 30 and the spare memory cells connected thereto. Therefore, before cutting the fuse, address A-A, A-A
, X , X by l n 1 n
OO can select either line S or Sl in the spare decoder 30 and select a spare memory cell (not shown) connected to the selected line. An operational test can be performed before cutting the fuse. This makes it possible to switch a defective memory cell to a non-defective spare memory cell.

Further, even after cutting off the fuse, the spare memory cell can be operated by setting the pair enable signal SE to a high level.

Furthermore, redundantly used addresses (addresses accessing spare memory cells) can be detected as follows. That is, first, the spare enable signal SE is set to high level, and specific data is written into one of the spare memory cells. Thereafter, the spare enable signal SE is returned to low level, and data from all memory cells is read.

If the spare memory cell into which specific data has been written has been replaced with a defective memory cell, specific data will be read corresponding to a certain address. The address at this time is detected as a redundant address. In this way, if any spare memory cell can be accessed even after the fuse is disconnected, the advantage is that redundant addresses can be detected without the need for a special circuit for detecting redundant addresses. There is also.

It should be noted that since the desired spare memory cell can be accessed even after the fuse is cut, there is an advantage that it is possible to easily check whether the fuse cutting process is successful or not.

When performing fuse cutting processing, since it is known which fuse to cut, which address Al-
It is known which +F(a memory cell will be accessed for Ao. Therefore, after cutting the fuse, write specific data according to that address, and then use the forced switching circuit 5 to write the spare memory cell. By forcibly accessing and reading the data, it is possible to check whether the fuse was disconnected as planned.

FIG. 3 shows the spare enable signal SE and its inverted signal S.
FIG. 2 is a circuit diagram showing an example of a circuit that generates E. Spare enable signal SE is output as a signal at the level of node 54 connected to external terminal 52. This node 54 is grounded via a high resistance 51. Spare enable inverted signal SE is an output signal of inverter 53 connected to node 54. Since node 54 is normally equal to the ground potential, spare enable signal SE is also at a low level. When a high level signal is applied to the external terminal 52, the spare enable signal SE becomes high level.

Note that in order to input the spare enable signal SE manually, it is also possible to input it from an existing external terminal without providing a new external terminal. For example, there is a circuit in which the spare enable signal SE becomes high level only when an ultra-high voltage is applied from an existing external terminal, or a circuit where the spare enable signal SE becomes high level only when the address input timing is set to a special timing.
It is sufficient to provide a circuit in which E becomes high level.

FIG. 4 is a circuit diagram showing a spare enable signal generation circuit used when there are two sets of spare decoders 30. Spare enable signal generation circuit 60 includes two NAND gates 61 and 62 and two inverters 63 and 64. The spare enable signal SE output from the circuit shown in FIG. 3 is applied to one side of each of the NAND gates 61 and 62. Also, NAND gate 61
On the other hand, the address At is the NAND gate 6
2, the inverted signal A1 is given as the other manual input.

The output signal of the NAND gate 61 becomes the first spare enable inverted signal SE1. Further, this signal is inverted by an inverter 63 and becomes the first spare enable signal SE1. On the other hand, the output signal of the NAND gate 62 becomes the second spare enable inverted signal SE2, and this signal is inverted by the inverter 64 to become the second spare enable signal SE2. Depending on the levels of the original spare enable signal SE and the address signal At, only one of the first and second spare enable signals SE and SE2 becomes the 7\high level, and the other becomes the low level. Therefore, the first and second spare enable signals SE, SE, .
Accordingly, only one of the two preliminary decoders can be activated.

Even when there are three or more spare decoders, it is possible to divide the spare enable signal in the same way. For example, if there are four spare decoders, use the original spare enable signal SE and address signals A t and A 2 to create four spare enable signals SE-3E4, and select any one of them. It is only necessary to make it high level.

Note that if there are two or more spare decoders, the normal decoder deactivation signal NED is obtained from each spare decoder, so the logical sum of these signals NED is used as the deactivation signal to deactivate all the normal decoders. Just give it to the decoder. In this way, if any one of the preliminary decoders is activated, all the normal decoders will be deactivated.

FIG. 5 is a block diagram showing a decoder section in a semiconductor integrated circuit as another embodiment of the invention. In the figure, a normal decoder 10a includes a NOR gate 12.13 and an inverter 4.1 from the normal decoder 10 shown in FIG.
5 and NMOS transistor T, AND
It has a configuration in which a gate 16 and a gate F and Fb are added.

In the normal decoder 10a of FIG. 5, the node N1 is grounded via the transistor T.sub.1. Also, precharge signal PRE and spare enable signal S
E is input to the AND gate 16, and the output of the AND gate 16 is input to the gate of the transistor Tr2°. Fuse F is connected to transistor T.

6 and fuse F6. is interposed between the transistor "r8 and the line L1."

Further, the preliminary decoder 30a in FIG. 5 has almost the same configuration as the preliminary decoder 30 in FIG. 2, but does not output the normal decoder deactivation signal NED to the normal decoder 10a.

In the decoder shown in FIG. When deactivating the memory cell connected to F, fuse F is cut. In this way, the normal decoder deactivation signal NE
The spare decoder 30a can be activated by setting the spare enable signal SE to a high level, which can deactivate the normal memory cells connected to the normal decoder 10H without applying D from the spare decoder 30a to the normal decoder 10a. Can be forcibly activated. That is, at this time, the output of the AND gate 16 becomes high level, and the node N1 becomes low level. Therefore, the normal decoder 1 is activated by the spare enable signal SE.
0a is deactivated and only the preliminary decoder 30a is activated.

〔Effect of the invention〕

As explained above, according to the present invention, the forced switching circuit sets a predetermined wiring position in the preliminary selection circuit to a predetermined signal level in response to the forced selection signal, and thereby selects the preliminary selection circuit. Therefore, the spare circuit can be selected regardless of whether or not the switching element is processed. Therefore, there is an effect that the spare circuit can be arbitrarily selected and accessed regardless of whether or not a switching setting is made by the processing of the switching element.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a circuit selection section of a semiconductor integrated circuit according to an embodiment of the invention, FIG. 2 is a circuit diagram showing a decoder section according to an embodiment of the invention, and FIGS. 3 and 4 are spare parts. FIG. 5 is a circuit diagram showing an enable signal generation circuit; FIG. 5 is a circuit diagram showing a decoder section according to another embodiment of the present invention; FIG. 6 is a block diagram showing a path selection section of a conventional semiconductor integrated circuit; FIG. 8 is a circuit diagram showing a conventional decoder section, and FIG. 8 is a timing chart showing the operation of the decoder section. In the figure, N1 to Nff1 are normal circuits, P[--P are preliminary circuits, 2 is a normal selection circuit, 3 is a preliminary selection circuit, 4 is a switching concave path, and 5 is a forced switching circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A plurality of normal circuits, a spare circuit having the same function as the normal circuit, a normal selection circuit that selects one of the plurality of normal circuits according to a given address signal, and a switching element. and a preliminary selection circuit that prevents the normal selection circuit from selecting the normal circuit and selects the backup circuit according to a predetermined value of the address signal by subjecting the switching element to a predetermined process. and receiving a predetermined forced selection signal and setting a predetermined wiring position in the preliminary selection circuit to a predetermined signal level in accordance with the forced selection signal, thereby determining whether or not the predetermined processing is to be performed on the switching element. 2. A semiconductor integrated circuit comprising: a forced switching circuit that causes the preliminary selection circuit to select the preliminary circuit.