JPH0314055A - Communication controller - Google Patents

Abstract

PURPOSE:To reduce the overhead due to retry of a channel command of software by connecting a timer to a channel command controller and holding data transfer for a prescribed time at the time when a transmission buffer cannot be reserved on a buffer memory during the execution of the channel command. CONSTITUTION:A timer means 5 is connected to a channel command control means 2; and if a channel command control means 2 cannot reserve the transmission buffer on a buffer memory means 1 when receiving the channel command for data transfer to the transmission buffer on the buffer memory means 1 from a main storage device, the channel command control means 2 starts the timer means 5. Data transfer is held for the preliminarily determined time of the timer means 5, and data transfer to the transmission buffer is started when this buffer is reserved. Thus, the overhead of software is reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a communication control device.

[Prior Art] Conventionally, this type of communication control device includes a buffer memory for storing transmitted and received data, a buffer management section for managing reservation and release of one buffer, and a channel command control section for controlling channel commands.

It consists of a line control section that performs transmission control.

When such a communication control device transfers data stored in the main storage device to the buffer memory based on instructions from the central processing unit, the channel command control unit secures a transmission buffer and transfers the transmission data to the buffer. The data is transferred and a report of normal completion is sent to the central processing unit.

Furthermore, if there is no space in the buffer memory, the transfer to the buffer memory is not performed, or is terminated when a transmission buffer can no longer be secured.

Reports abnormal termination to the central processing unit.

[Problems to be Solved by the Invention] In the conventional communication control device described above, if a transmission buffer cannot be secured in the buffer memory, the transfer is not performed or is terminated when the transmission buffer cannot be secured. , the central processing unit software had to issue a channel command to the communication control unit again after a certain period of time to transfer the data from the main memory to the buffer memory, which had the disadvantage of increasing software overhead. .

[Means for Solving the Problems] The present invention provides channel command control means for controlling the execution of channel commands based on instructions from a central processing unit, a buffer memory for storing transmitted/received data, and a transmitter prepared on the buffer memory. A communication control device comprising a buffer management means for managing the head address and number of buffers, and a line control means for controlling a transmission control procedure,
A timer means is connected to the channel command control means.

If a transmission buffer cannot be secured on the buffer memory means when the channel command control means receives a channel command for transferring data from the main storage device to the transmission buffer on the buffer memory means, the channel command control means starts said timer means;
The present invention is characterized in that the timer means suspends data transfer for a predetermined period of time, and starts data transfer to the transmitting bar/sofa when the transmitting sofa is secured.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a communication control device according to an embodiment of the present invention.

The channel command control means 2 has a function of fetching, decoding, and executing channel commands stored on the main storage device according to instructions from the central processing unit. This channel command control means 2 is connected to the central processing unit via a signal line 11, to the main storage device via a signal line 12, and to the buffer memory 1 via a signal line 13. The channel command control means 2 also controls the buffer empty signal line 21. Buffer reservation signal line 22. Bath sofa release signal 1j123. and is connected to the buffer management means 3 via a buffer address signal line 24. Furthermore, the channel command control means 2 has a timer set signal line 25. Timer reset signal line 26. and time-over signal line 2
It is connected to timer means 5 via 7.

The buffer memory 1 is a memory for storing transmission data/reception data, and is connected to the channel command control means 2 via a signal line 13 and to the line control means 4 via a signal line 14.

The buffer management means 3 has a function of managing the start address and number of transmission data buffers/reception data buffers. This buffer management means 3 includes a buffer empty signal line 21. Buffer reservation signal line 22. Buffer release signal line 23. and is connected to the channel command control means 2 and the line control means 4 via a buffer address signal line 24.

The timer means 5 measures a predetermined time according to a signal from the channel command control means 2. This timer means 5 includes a timer set signal line 25, a timer reset signal line 26. and is connected to the channel command control means 2 via a time-over signal line 27.

The line control means 4 controls the transmission control procedure for one line.

This line control means 4 is connected to the buffer memory 1 via a signal line 14. Also, the buffer empty signal line 2
1. Buffer reservation signal line 22, buffer release signal line 23
．． and is connected to the buffer management means 3 via a buffer address signal line 24.

FIG. 2 is a detailed block diagram of the buffer management means 3 of FIG. 1.

The address stack 41 is a stack that stores the start address of the transmitting buffer/receiving buffer. Address stack 41 is connected to channel command control means 2 and line control means 4 via buffer address signal line 24.

Further, the address stack 41 is connected to the read pointer signal line 5.
3(a) to the read pointer 44, and the write pointer signal line 54(a) to the write pointer 43.

The buffer control circuit 42 is a circuit that controls the buffer management means 3. The buffer control circuit 42 is connected to the channel command control means 2 via a buffer reservation signal line 22 and a buffer release signal line 23. Also,
The buffer control circuit 42 is connected to a read pointer 44 via a read control signal line 51 and a write control signal line 52.
It is connected to the write pointer 43 via.

The write pointer 43 is connected to the buffer control circuit 42 via a write control signal line 52.

Further, the write pointer 43 is connected to the write pointer signal line 54.
It is connected to the address stack 41 and the comparator 45 via (a) and (b).

The read pointer 44 is connected to the buffer control circuit 42 via a read control signal 51.

The read pointer 44 also has a read pointer signal 53.
It is connected to the address stack 41 and the comparator 45 via (a) and (b).

When a buffer reservation signal is sent from the channel command control means 2 or the line control means 4 to the buffer management means via the buffer reservation signal line 22, the contents of the address stack 41 indicated by the read pointer 44 are sent to the buffer buffer as a buffer address signal. The signal is output to the address signal line 24 and the read pointer 44 is updated. Similarly, when the buffer release signal 23 is sent from the channel command control means 2 or the line control means 4, the contents of the buffer address signal from the buffer address signal line 24 are written to the address stack 41 indicated by the write pointer 43. The pointer 43 is updated.

The comparator 45 has a write pointer 43 and a read pointer 44.
If they do not match, a signal 41 indicating that the buffer is empty is outputted to the channel command control means 2 and the line control means 4 via the buffer empty signal line 21.

Next, the operation of the communication control device shown in FIG. 1 will be explained.

The channel command control means 2 accepts activation from the central processing unit via the signal line 11. At this time, if the signal from the buffer empty signal line 21 indicates that the buffer is empty, a buffer reservation signal is output to the buffer reservation signal line 22.

When the buffer management unit 3 receives the buffer reservation signal, it outputs the transmission buffer head address to the channel command control unit 2 via the buffer address signal line 24. When the channel command means 2 receives the first address of the transmission bus sofa, it transfers the transmission data from the main storage device to the buffer memory 1 via the signal lines 12 and 13. Thereafter, the channel command means 2 reports normal termination to the central processing unit.

When the signal from the buffer empty signal line 21 indicates that the sofa is empty, the channel command control means 2 sends a signal to the timer means 5 via the timer set signal line 25.
and enters into a waiting state for a predetermined time.

When a buffer empty signal is output from the buffer management means 3 after a predetermined period of time has elapsed, the channel command control means 2
outputs a reset signal via the timer reset signal line 26 to reset the timer 5. Thereafter, the transmission data is transferred to the buffer memory 1 via the signal lines 12 and 13 as described above, and a normal termination is reported to the central processing unit.

If the transmission bar/sofa cannot be secured before the predetermined time elapses, the timer means 5 notifies the channel command control means 2 of the time over via the time over signal line 27. The channel command control means 2 does not execute the transfer operation, but reports the abnormal termination to the central processing unit.

The transmission buffer is released when the line control means 4 transmits this data onto one line and receives a response indicating normal reception from the other station.

Therefore, it is possible to find out when the transmission buffer is empty by suspending data transfer for a predetermined period of time.

The above explanation is an example in which a buffer cannot be secured at the start of data transfer, but the same applies even if a buffer cannot be secured during data transfer.

[Effects of the Invention] As explained above, the present invention connects a timer to the 9-channel command control device, and suspends data transfer for a predetermined period of time when a transmission buffer cannot be secured in the buffer memory when executing a channel command. Transfer from main memory to buffer memory can be performed,
This has the effect of eliminating the overhead caused by retrying channel commands by software.

control means, 3... buffer management means, 4... line control means, 5... timer, 11, 12.13.14.15
...Signal line, 21...Buffer empty signal line, 22
. . . Buffer reservation signal line, 23 . . . Buffer release signal line.

24... Buffer 7 address signal line, 25... Timer set signal line, 26... Timer reset signal line, 27
13. Time over signal line, 41...Address stack, 42...Buffer control circuit, 43...Write pointer, 44...Read pointer, 45...Comparator.

51... Read control signal line, 52... Write control signal line, 53 (a), 53 (b)... Read pointer signal line.

54(a), 54(b)...Write pointer signal line.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a detailed block diagram of the buffer management means 3 shown in FIG. 1... Buffer memory, 2... Channel command system Figure 2

Claims (1)

[Claims] 1. Channel command control means for controlling execution of channel commands according to instructions from a central processing unit, a buffer memory for storing transmitted and received data, and a starting address of a transmitting buffer prepared on the buffer memory. and a communication control device comprising a buffer management means for managing the number of buffers and a line control means for controlling a transmission control procedure, wherein a timer means is connected to the channel command control means,
If a transmission buffer cannot be secured on the buffer memory means when the channel command control means receives a channel command for transferring data from the main storage device to the transmission buffer on the buffer memory means, the channel command control means starts the timer means and suspends data transfer for a time determined by the timer means,
A communication control device characterized in that when a transmission buffer is secured within the time period, data transfer to the transmission buffer is started.