JPH0235500B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a line control system in data communications.

A communication control device for performing data communication includes, for example, as shown in FIG. 1, a processing device 100 having a processor 110 and a memory 120, a plurality of line control units 200, and a data communication line 300. There is.

Here, characters (including transmission control characters and general characters) are transferred between the processing device 100 and the line control unit 200, and transmitted data and received data are transferred between the line control unit 200 and the data communication line 300. transfer is taking place. In addition, the processing device 1
The communication procedure at 00 follows the synchronous basic procedure.

In order to reduce the processing load on the processing device 100, it has been proposed that the line control unit 200 be provided with an automatic data transmission/reception function and a direct memory access (DMA) function. Here, the text start signal STX and text end signal ETX of the synchronous basic procedure are
etc., and it is necessary to stop DMA transfer during this time. This is because, in the synchronous basic procedure, the state is changed in accordance with the type of transmission control character received by the processing device 100, and the next character cannot be received until this state is determined.

Also, when transmitting and receiving transmission control characters, the processing device 10
0 controls multiple data communication lines 300 in a time-sharing manner, so it is necessary to process transmission control characters from other data communication lines at the same time. It may take some time to finish. In this case, data overrun or underrun occurs between the data communication line 300 and the line control unit.

Below, the technology of normal DMA transfer will be explained.

A typical DMA transfer method is a method in which data transfer between a peripheral device and a memory in a computer system is performed by a DMA transfer execution device without using the memory writing and reading functions of the central processing unit. The DMA transfer execution device is sent in advance from the central processing unit the address of the memory to be the transfer source or the transfer destination. Therefore, the DMA transfer execution device executes data transfer between the peripheral device and the memory based on an address that is notified in advance from the central control device or the peripheral device when it is activated. In the DMA transfer method, data is transferred without using the write or read functions of the central processing unit, so the central processing unit continues to perform processes other than data transfer even while data is being transferred in memory. Can be done.

Note that when writing to or reading from consecutive addresses in memory using the normal DMA transfer method, the central processing unit notifies the DMA transfer execution device of the initial value memory address and the number of data to be transferred in advance.
This is done by incrementing the address by 1 each time the DMA transfer execution device transfers one unit of data.

The details of the prior art will be explained below.

FIG. 2 is a block diagram of the main parts of a conventional line control section, in which 210 is an interface control circuit, 22
0 is a data transmission/reception circuit, 230 is an automatic data transmission/reception circuit, 310 is a transmission line, 320 is a reception line,
330 is a transmission timing signal line, and 340 is a reception timing signal line. The data transmitting/receiving circuit 220 of the line control unit 200 performs the processing of assembling the received data from the receiving line 320 into characters and the processing of disassembling the characters from the processing device 100 into transmission data. A data communication line is a line that transmits and receives data to and from the processing device 100 in a parallel format.
Data is transmitted and received in serial format in synchronization with timing signals ST and RT.

When accommodating a plurality of data communication lines, the processor 11
There is no need to perform transfer processing for general characters other than 0 as a transmission control character, and the probability of data overrun or underrun occurring is reduced.

Here, the characters targeted for DMA transfer are transmission control characters and general characters when transferred from the memory 120 to the data transmission/reception circuit 220, and general characters when transferred from the data transmission/reception circuit 220 to the memory 120.

The automatic data transmitting/receiving circuit 230 has the above-mentioned normal
It has the function of a DMA transfer execution device in the DMA transfer method. Here, automatic data transmission/reception circuit 23
0 contains the memory 1 required to perform DMA transfer.
The address within 20 is notified in advance by the processing device 100.

However, text start signal STX, text end signal ETX, transmission control extension signal DLE, synchronization signal
When transmitting and receiving transmission control characters such as SYN that require processing in the processing device 100, there is a high probability that overruns and underruns will occur because the processing described below is necessary.

In other words, the transmission control character is
0, the automatic data transmitting/receiving circuit 2
In addition to stopping DMA startup for 30,
An interrupt signal is generated to the processing device 100. The processing device 100 that received this interrupt signal
determines the type of transmission control character based on the type of interrupt and starts corresponding processing, and when the processing of the transmission control character is completed, it notifies the data transmission/reception circuit 220 to that effect, and then starts the automatic data transmission/reception circuit 230 again. is started. DMA transfer is resumed.
In this way, while the processing device 100 is processing transmission control characters, characters cannot be transferred between the data transmission and reception circuit 220 and the processing device 100.
There was a possibility that an overrun of received data to the transmission line 310 or an underrun of transmission data from the data transmission/reception circuit 220 to the transmission line 310 would occur.

Note that the processing performed when the processor receives a transmission control character is based on state transitions defined by a known basic procedure. Here, the state regarding data transfer of the processor is defined for each data communication line, and this state changes when a transmission control character is received.

For example, when the processor recognizes the arrival of STX from a certain data communication line, the state of the processor changes from the data reception state to the data reception state. In the data reception state, the processor determines that a string of ordinary characters sent from this data communication line is one block of data. Furthermore, if ETX is received, the processor determines that it has finished receiving one block of data, and transitions to the data reception state.

An object of the present invention is to prevent the occurrence of data overruns or underruns, which are the drawbacks of the above-mentioned prior art, with a simple configuration. Examples will be described in detail below.

FIG. 3 is a block diagram of an embodiment of the present invention, in which the same reference numerals as in FIG. 2 indicate the same parts, and 240
is transmit first-in-first-out (FIFO)
The queue 250 is a receiving first-in-first-out (FIFO) queue, and the reference numeral 260 is a timing generation circuit that generates timing signals ST' and RT' at several times (for example, twice) the speed of the timing signals ST and RT. Transmission FIFO queue 240 and reception
Data is transferred between the FIFO queue 250 and the data transmission/reception circuit 220 in synchronization with timing signals ST' and RT' created by the timing creation circuit 260.

In addition, under normal conditions, the data transmission/reception circuit 220
Assembles and disassembles the character at the speed of timing signals ST' and RT'.

Here, the automatic data transmitting/receiving circuit 230 has a normal DMA transfer function and transfers characters between the data transmitting/receiving circuit 220 and the memory 120. Characters to be subjected to DMA transfer are transmission control characters and general characters in transfer from the memory 120 to the data transmission/reception circuit 220, and general characters in transfer from the data transmission/reception circuit 220 to the memory 120.

The automatic data transmitting/receiving circuit 230 is a normal DMA
It has the function of a DMA transfer execution device in the transfer method. Here, the automatic data transmitting/receiving circuit 230 includes memory 1 necessary for performing DMA transfer in advance.
The address within 20 has been notified from the processing device 100.

When the data transmitting/receiving circuit 220 finishes assembling the received data into a character, it notifies the automatic data transmitting/receiving circuit 230 to that effect. The automatic data transmitting/receiving circuit 230 is the data transmitting/receiving circuit 22
Upon receiving the notification from 0, DMA transfers one character in the data transmission/reception circuit 220 to the memory 120.
Forward.

When a character to be transferred is generated in the processing device 100, the automatic data transmission/reception circuit 230 is notified of this fact. Automatic data transmission/reception circuit 230
At the time of receiving the notification from the processing device 100,
The characters in the memory 120 are DMA-transferred to the data transmitting/receiving circuit 220 according to the address sent from the processing device 100 in advance. Furthermore, the transfer of characters stored at consecutive addresses in the memory 120 is as follows:
The automatic data transmitting/receiving circuit 2 determines the initial value of the address and number of characters of the data to be transferred from the processing device 100 in advance.
30, this is done according to the normal DMA transfer method.

Note that, due to execution of the DMA transfer, the operations of the data transmitting/receiving circuit 220 to read the received data from the receive FIFO 250 and to transfer the transmit data to the transmit FIFO 240 are not interrupted.

Data on a data communication line is a timing signal
Since it is synchronized with ST and RT, the transmission line 310
and the speed of the receiving line 320 are determined by the timing signal ST,
The speed is the same as RT. Further, the data rate from the data transmitting/receiving circuit 220 to the transmitting FIFO queue 240 is several times (for example, twice) the data rate transmitted to the transmitting line 310. In addition, synchronization signals can be used even when there is no data to be transmitted.
SYN is generated by the data transmitting/receiving circuit 220 and continuously transferred to the transmitting FIFO queue 240.
Here, since the input speed is faster than the output speed, this transmit FIFO queue 240 is normally full. Similarly, the data rate from the reception FIFO queue 250 to the data transmission/reception circuit 220 is the reception line 3.
The data rate is several times (for example, twice) the rate received from 20, and the output data rate is faster than the input, so it is normally empty.

In this way, the transmitting FIFO queue 240 is normally controlled to be full of data, and the receiving FIFO queue 250 is normally controlled to be empty.

The transmission FIFO queue 240 has a function of detecting whether the data waiting to be transmitted is full or not, and the signal detected to be full is applied to the timing generation circuit 260, thereby stopping the generation of the timing signal ST'. be done. In addition, the reception FIFO queue 250 has a function of detecting whether or not the accumulated content is zero, and the signal detected as zero is sent to the timing generation circuit 2.
60, thereby timing signal
The generation of RT' is stopped.

The transmission FIFO queue 240 has a timing signal.
Data is transferred and accumulated from the data transmitting/receiving circuit 220 in synchronization with ST', and the transmission data SD is transferred to the transmission FIFO queue 240 in synchronization with the timing signal ST.
The signal is sent to the transmission line 310. Also receive FIFO
The received data RD from the receiving line 320 is stored in the queue 250 in synchronization with the timing signal RT.
The data is read out by the data transmitting/receiving circuit 220 in synchronization with the timing signal RT'.

The automatic data transmitting/receiving circuit 230 allows the memory 12 to
0 to the data transmitting/receiving circuit 220, or when the receiving FIFO queue 250
When a transmission control character is set in the data transmitting/receiving circuit 220, the data transmitting/receiving circuit 220 issues an instruction to the automatic data transmitting/receiving circuit 230 to stop the activation of DMA, and also sends an interrupt to the processing device 100. The signal is generated, and at the same time, the generation of timing signals ST' and RT' is stopped. Furthermore, the processing device 100 that receives this interrupt signal determines the type of transmission control character based on the type of interrupt and starts processing, and when the processing of the transmission control character is completed, a notification to that effect is sent to the data transmission/reception circuit 220. Notify the automatic data transmission/reception circuit 2 again.
30 is activated and DMA transfer is restarted, and at the same time, generation of timing signals ST' and RT' is restarted.

Transmission control characters include STX (text start signal), ETX (text end signal), DLE (transmission control extension signal), SYN (synchronization signal), etc.
When processor 110 receives a transmission control character, processing is performed based on state transitions defined by a known basic procedure. While the processing device 100 is processing transmission control characters based on the state transition specified in the basic procedure, the transmission data accumulated in the transmission FIFO queue 240 is sent out to the transmission line 310, and the transmission data accumulated in the transmission FIFO queue 240 is sent to the transmission line 310, and
The queue 250 receives data received from the receiving line 320.
RD is accumulated.

Note that even if DMA transfer is in progress, as long as the timing signals ST' and RT' are generated, the data transmission/reception circuit 220 and reception FIFO queue 250
Data transfer operations between the data transmitting/receiving circuit 220 and the transmitting FIFO queue 240 are not interrupted.

Next, the operation when DMA transfer is in progress and timing signals ST' and RT' are being generated will be described.

After reading the received data from the reception FIFO queue 250, the data transmitting/receiving circuit 220 notifies the automatic data transmitting/receiving circuit 230 when it finishes assembling the received data into general characters. If the automatic data transmitting/receiving circuit 230 receives the notification from the data transmitting/receiving circuit 220 and DMA transfer between the line control unit 200 and the memory 120 corresponding to another data communication line is not performed, the automatic data transmitting/receiving circuit 230 transfers the data. One general character in the transmitter/receiver circuit 220 is DMA-transferred to the memory 120. If a DMA transfer is being performed between the line control unit 200 corresponding to another data communication line and the memory 120, the DMA transfer to the memory 120 is performed after waiting for its completion.

When a character to be transferred occurs in the processing device 100, the automatic data transmitting/receiving circuit 230 is notified of this fact. If DMA transfer between the line control unit 200 corresponding to another data communication line and the memory 120 is not performed at the time of receiving the notification from the processing device 100, the automatic data transmission/reception circuit 230 stores data in advance. Memory 120 according to the address
The characters within are DMA transferred to the data transmitting/receiving circuit 220. If a DMA transfer is being performed between the line control unit 200 and the memory 120 corresponding to another data communication line, wait for the completion of the DMA transfer, and then DMA transfer the characters to the data transmitting/receiving circuit 220.

As mentioned above, the transmit FIFO queue 240 and receive
By providing the FIFO queue 250, for example, text start signal STX, text end signal
Even when receiving or transmitting transmission control characters that require processing by the processing device 100, such as ETX, transmission control extension signal DLE, and synchronization signal SYN, the processing time in the processing device 100 is In the case of transmission, the transmission FIFO queue 24 is already
Transfer the transmission data SD stored in 0 to transmission line 3
10, the data transmitting/receiving circuit 22
0 can be prevented, and in the case of reception, by storing the received data RD from the reception line 320 in the reception FIFO queue 250, it is possible to prevent an overrun in the data transmission/reception circuit 220. Become.

As explained above, the present invention provides a transmission FIFO queue 240 that is controlled to be full of data.
and reception controlled so that the data is empty.
By providing the FIFO queue 250, STX, ETE, etc. that require processing by the processing device 100,
When transmitting or receiving a transmission control character such as DLE or SYN, transmit the data accumulated in the transmission FIFO queue 240 and accumulate the received data in the reception FIFO queue 250 until the processing of the transmission control character is completed. This has the advantage of preventing data overruns and underruns.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a communication control device, FIG. 2 is a block diagram of a conventional line control section, and FIG. 3 is a block diagram of a line control section according to an embodiment of the present invention. 100 is a processing device, 110 is a processor, 12
0 is a memory, 200 is a line control section, 210 is an interface control section, 220 is a data transmission/reception circuit,
230 is an automatic data transmission/reception circuit, 240 is a transmission
FIFO queue, 250 is receive FIFO queue, 260
3 is a timing generation circuit, 300 is a data communication line, 310 is a transmission line, 320 is a reception line, 33
0 is a transmission timing signal line, and 340 is a reception timing signal line.

Claims (1)

[Claims] 1. A processing device having a processor and a memory;
It consists of a line control unit that accommodates a data communication line, and characters transferred between the line control unit and the processing device include general characters and transmission control characters. In a communication control device equipped with a circuit for DMA transfer of general characters to a processing device, the received data from the data communication line is received and assembled as a character, and then transferred to the processing device, or receiving a character from a processing device and decomposing the character into transmission data;
a data transmission/reception circuit that transfers data to the data communication line; a transmission first-in-first-out queue that stores transmission data between the data transmission and reception circuit and the data communication line; and a reception first-input queue that stores reception data. A strikeout queue is provided, and if the character received by the data transmitting/receiving circuit is a transmission control character, the data transmitting/receiving circuit notifies a processing device to that effect and causes the processing device to process the transmission control character. until the end of
performing control to stop input from the receiving first-in-first-out queue to the data transmitting/receiving circuit and stopping output of transmitting data from the data transmitting/receiving circuit to the transmitting first-in-first-out queue; The first-in-first-out queue is controlled by a timing generation circuit so that the data to be sent is received from the data transmission/reception circuit at a timing faster than the timing at which data is sent to the data communication line, and the data to be sent is full. The in-first-out queue is controlled by the timing generation circuit so that the received data is transferred to the data transmitting/receiving circuit at a timing faster than the timing at which the received data is accepted from the data communication line so that the received data becomes empty. Characteristic line control method.