JPH03139049A - Serial parallel conversion circuit - Google Patents

Abstract

PURPOSE:To increase a reference for discriminating truth of a parallel data at transmission error by providing a counter circuit counting bit number of parallel signal of one frame reproduced from a serial signal of a sent frame. CONSTITUTION:When a counter circuit 12 inputs, e.g. a serial signal 1, the circuit 12 receives a 9-bit data comprising data 0-7 and a parity bit. In this case, 9 pulses are outputted as an output signal 7 of a gate circuit 2. The signal drives the circuit 12, and when the pulse number reaches 9, a timing pulse 14 being a counter output signal is outputted to an AND circuit 13, and when the parity is correct, a data output enable signal 11 is outputted from an AND circuit 13. Through the constitution above, not only the parity but also transmission bits are detected to improve the reference for discriminating the truth of the parallel data at a transmission error thereby applying transmission with high reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a serial/parallel conversion circuit applied to communication products.

[Prior Art] In the case of normal serial data transmission, a phase modulation method is often used. As shown in Figure 3, this is a method of sending 1 bit of data using 2 bits in serial signal 1. If it is "10", the data is 0, and if it is "01", the data is 1. .

The conventional serial/parallel conversion circuit detects the rise or fall of the serial signal 1 by passing the serial signal 1 through the differentiating circuit 2 as shown in Fig. 2, and outputs the differentiating circuit output as shown in Fig. 3. Outputting signal 3, timer circuit 4
Open the gate circuit 6 so as to pass the first pulse 5 to the (N+1)th pulse of the differential circuit output signal,
The output signal 7 of the gate circuit was obtained, and the data input to the shift register 9 was sequentially latched at timing 8 of this signal "1" to reproduce parallel data. At the same time, a parity bit is added to the transmitted data, and the parity circuit 10 on the playback side
After performing a parity check, data output permission signal 1 is sent.
It was configured to output 1.

[Problems to be Solved by the Invention] In the conventional serial-to-parallel conversion circuit described above, when the transmission of the serial signal 1 is interrupted midway, or due to a timing difference between the timer circuit 4 and the differential circuit output signal 3, the gate When the circuit output signal 7 is no longer output normally, the serial signal that is manually input to the system register 9 at the wrong timing is latched, and the number of bits of the transmitted frame and the number of reproduced frames are determined at the output timing of the data output permission signal 11. Even if the number of bits is different and multiple bit errors occur, if the parity happens to be correct, output is allowed as is.
was being output. As a result, erroneous parallel data may be output as normal data.

Of the present invention: II! The problem is to provide a serial/parallel conversion circuit that can solve the above conventional problems.

[Means for Solving the Problems] A serial/parallel conversion circuit according to the present invention includes a differentiating circuit into which a serial signal is input, a gate circuit connected to the differentiating circuit and the timer circuit, respectively, the serial signal and the gate. In a serial/parallel conversion circuit comprising a shift register for manually inputting the output signals of the lff1 path, and a parity circuit for checking the parity of the data output from the shift register and outputting data output permission No. 16,
A feature is that a counter circuit is provided to count the number of bits of data that has been converted into parallel and serial data. That is, in the present invention, a counter circuit is provided in the conventional serial/parallel conversion circuit in order to count the number of bits of one frame of parallel signal reproduced from the transmitted frame serial signal. .

[Function] Since the serial/parallel conversion circuit of the present invention is configured as described above, when the gate circuit output signal is input to the shift register 9, it is input to the counter circuit, and the transmission bit obtained by the counter circuit is If the number and parity are normal, a data output permission signal will be output. As a result, if the transmission of the serial signal is interrupted during serial/parallel conversion, or if an error occurs in the gate circuit output due to a timing difference between the timer circuit and the differential circuit output signal, the data At the output timing of the output permission signal, it is possible to detect that the number of bits in one transmitted frame and the number of bits in one reproduced frame are different, and a transmission error has occurred. This type of error involves multiple bit errors and cannot be detected by a parity check by adding a parity bit, so the method of the present invention is effective.

Further, since there is no need to add extra check bits to the frame and the frame transmission time is not increased due to the transmission and reception of the check bits, it is effective in realizing highly reliable and high-speed serial communication. Further, since the test circuit can be configured only with a counter and a NAND gate, the hardware can be configured easily.

[Example 1] FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, 1 is a serial signal, 2 is a differential circuit,
3 is the differential circuit output signal, 4 is the timer circuit, 5 is the first pulse, 6 is the gate circuit, 7 is the gate circuit output signal, 8 is the timing point, 9 is the shift register, 10 is the parity circuit, 11 is the data output permission 12 is a counter circuit, 13 is an AND circuit, and 14 is a timing pulse.

In FIG. 1, for example, when the counter circuit 12 receives a serial signal 1 as shown in FIG. 3, the counter circuit 12 converts data 0 to data 7 and parity into 9-bit data. At this time, nine pulses are outputted as the gate circuit output signal 7. When the counter circuit 12 is driven by this signal and the number of pulses reaches 9, a timing pulse 14, which is a counter output signal, is outputted and inputted to the AND circuit 13, and at the same time, if the parity is correct, a data output permission signal 11 is outputted. It becomes like this.

[Effects of the Invention] As explained above, according to the present invention, by detecting not only parity but also transmission bits, the standard for determining the authenticity of parallel data in the event of a transmission error is raised, and highly reliable transmission can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional example, and FIG. 3 is a block diagram showing the configuration of a conventional example.
FIG. 3 is a timing waveform diagram of a parallel conversion circuit. 1...Series signal, 2...Differential circuit, 4...Timer circuit, 6...Gate circuit, 9...Shift register,
10... Parity circuit, 12... Counter circuit, 1
3...AND circuit.

Claims (1)

[Claims] A differentiating circuit into which the serial signal is input, a gate circuit connected to the differentiating circuit and the timer circuit, a shift register into which the serial signal and the output signal of the gate circuit are respectively input, and an output signal from the shift register. A serial/parallel conversion circuit comprising a parity circuit for checking the parity of data and outputting a data output permission signal, the serial/parallel conversion circuit comprising a counter circuit for counting the number of bits of parallel/serial converted data.・Parallel conversion circuit.