JPH03138753A - Boot loader for multiprocessor system - Google Patents

Abstract

PURPOSE:To easily restart a processor after abnormality of an operating system by referring to a prereset state holding register, where the state before restart is held, to execute boot load by a secondary storage device at the time of restarting the processor. CONSTITUTION:Board discrimination numbers are used as boot processor discrimination numbers on a multiprocessor 1a, 1b, and 3a to 3n. The impossibility of boot load of the system due to overlap of discrimination numbers is prevented, and a boot processor discriminating register set 9 which can be accessed by all processors 1a, 1b, and 3a to 3n is provided, and processors 3a to 3n to which secondary storage devices 2a and 2b capable of boot load are not connected are selected as boot processors to prevent the impossibility of boot load of the system. Further, the past rest classification is referred by a reset history register 7 to perform the execution control of boot adapted to the state of the processor. Thus, the processor is easily restarted after abnormality.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system in which a collection of many processor boards connected by a common bus collectively perform one function. The present invention relates to a boot load device for a multiprocessor system that sets software to be processed from a secondary storage device into the memory area of each processor.

[Conventional technology]

FIG. 4 is a block connection diagram showing a conventional multiprocessor system platform load device disclosed in, for example, Japanese Unexamined Patent Publication No. 63-104167.
1b, . . . 1n are processors connected by a common bus, 6D, 11a, 11b, . Combine 1a to 1n and h
12 is a common memo connected to common bus 4.
)% 13ae13b-...13n are storage areas corresponding to the above respective identification numbers.

Next, the operation will be explained using the flowchart shown in FIG. First, turn on the power (Step ST21)
, activates the status monitoring line of the common bus 4. Then, each processor 1a to 1n performs a self-diagnosis (step 5T22), and writes a self-identification number into the corresponding storage area 13a to 13n on the common memory 12 according to the identification number specified by the identification number operation unit 11 & to 11n. write(
Step 5T23), release its own status monitoring line. After this, it is checked whether the status monitoring line of the entire system has been released (step 5T24), and if it is not released and it is determined that a predetermined time has elapsed (step 5T25), abnormality processing for each processor is performed. conduct(
Step 5T26). If the system status monitoring line is normally released within the specified time, it is determined whether the self is the boot processor (step 5T27).
). Jin's determination is that if no identification number with a higher priority than the value of his own is stored in the occupational number storage area 13&~13nK on the common memory 12, he becomes the boot processor. Next, the processor determined to be the boot processor performs a boot operation, and after completing the boot, sends a boot command to the other processor (step 5T28). On the other hand, processors that are not determined to be boot processors wait for a startup command from the foot processor (step 5T29).
. After this, all processors 1a to 1n perform normal operations.

[Problem to be solved by the invention]

The bootload device of a conventional multiprocessor system is configured as described above, so when an abnormality occurs in one of the processors 1a to 1n during system operation, it is possible to locally reset that processor 1a to 1n. Normal state KO! In addition, there is a restriction that the common memory 12 is always required in the boot processor determination process, and there are no restrictions on setting the identification number for determining the boot processor. If the number is duplicated among the processors 1a to 1n, there is a problem that the system may not start up properly.

This invention was made to solve the above problems, and even if a single processor on a multiprocessor is reset during system operation, the system function can be restored normally. , a boot load device for a multiprocessor system that can have an effective boot processor determination process even in a multiprocessor system that does not have a common memory, and that can prevent the occurrence of a boot impossible state due to duplication of boot processor identification numbers. The purpose is to obtain.

[Means to solve the problem]

A bootload device for a multiprocessor system according to the present invention connects a plurality of processors including a processor capable of becoming a boot processor to a common bus, and each of these processors has a common bus that controls access to the common bus. A reset switch for local reset is provided to reset the bus interface unit and itself, and the history of reset information obtained from these common bus interface units and the reset switch is stored in a reset history register. A board identification register enables access to processors, a register set for boot processor identification is provided to determine which processors can be bootloaded, and the past state of each processor saved without being initialized is determined by the local reset described above. It is saved in the pre-reset state save register, and when the self-processor was a boot processor in the past or was determined to be a boot processor by the above boot processor determination register set, bootload is executed from the secondary storage device. The structure is such that

[Effect]

The bootloading device for a multiprocessor system according to the present invention uses a board identification number on a multiprocessor as a boot processor identification number, so it prevents the identification number from being duplicated and the system cannot be put into a bootable state. , equipped with a register set for identifying the boot processor that can be accessed from all processors.
A processor to which a bootloadable secondary storage device is not connected is selected as a boot processor, thereby preventing the system from being put into a non-putable state.

In addition, the reset history register allows you to refer to the past reset type (reset only to the local self-board, reset to the entire system, or power on the system), and execute boot according to the state of the processor. Enabling control.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, tag and 1b are processors that can become boot processors, and each is connected to a secondary storage device 2a s 2b.

3a...3n are processors that cannot become boot processors. 4 is all processors 1a*1
b, 3a to 3n are connected to the common bus. Each processor 1a *1b connected to this common bus 4
s3a to 3n can communicate with any processor by the function of the common bus 4, and the form of communication may be by using special hardware or by using a common memory.

Further, FIG. 2 shows details of the processors 1ae1b, 3a to 3n, and in the figure, 5 indicates each processor Ia, 1b.
*A common bus interface section provided in each of 3a to 3n to control access to the common bus 4. This common bus interface section 5 detects a power-on reset or a system level reset generated on the common bus. When the processor 1a*1b, 3a including itself
Send a reset signal to the entire 3n. 6 is a processor 1a.

1 b # 3 a~3nK is a reset switch for local reset that is uniquely equipped. When this reset switch 6 is pressed, the processor 1a*1b+3a~3
Only the n processing functions are reset.

The common bus interface unit 5 and the pre-reset state storage register (t or area) 10, which will be described later, are not reset. 7 is a reset history register, and this register 7 inputs the system level reset signal (or power-on reset signal) output from the common bus interface section 5 to the set input, and resets the local level reset signal from the reset switch 6. This can be easily achieved with a circuit such as a reset-set flip-flop that is input to the input. 8 is a board identification register accessible from the common bus interface unit 5.

Reference numeral 9 denotes a boot processor determination register set including a board name register for clearly identifying the board type and the like. This board name is stored in a means such as a read-only memory and is non-volatile. Also, by the action of the common bus interface unit 5, each processor 1a, 1b,
3a to 3n. 10 is a pre-reset state saving register. It is not initialized on a local level reset and is used to save past state (eg whether the self processor (board) was or was not a boot processor).

Next, the operation will be explained using chart 70 in FIG. First, it is initialized as a result of a reset or power-on,
Processor 1a starts execution again.

1b, 3a to 3n perform self-diagnosis (step 5TI
).

It is determined whether the self-diagnosis result is normal or not (step ST2), and if it is abnormal, a jump is made to the self-diagnosis error stop (step ST3). In self-diagnosis error stop, the processor that has caused the self-diagnosis error is prevented from becoming the boot processor using either of the following two methods.

1) Set self-diagnosis error in the boot processor discrimination register set 9.

2) Send a signal to the common bus interface unit 5 to prevent this processor from being accessed by other processors connected to the common bus 4.

Next, when it is determined to be normal in step ST2, it is determined whether the cause of the restart is due to the reset switch 6 by referring to the reset history register 7 (
Step ST4). If the result of this determination is due to the reset switch 6 (in the case of local reset),
As will be described later, a case where the reset history is a system level reset will first be shown here. In the case of a system level reset, it is determined whether the self processor is a poutable processor (step ST5). This is the boot processor identification register set 9 that includes the board name register, and indicates that the board name is a bootable processor and that a secondary storage device is connected.)
Also, if the self-diagnosis result is normal, it is determined that the processor is a poutable processor. Next, determine whether a processor with a higher priority board identification number than yours that is connected to the system is a poutable processor (if the board name indicates a poutable processor and the self-diagnosis result of that processor is normal). Step ST6
), the self-processor (self-board) becomes the poutable processor if there is no poutable processor with a higher priority than the self.

Further, the processor that did not become the boot processor in step ST5 determines the boot processor of the system (step ST7) and waits until the boot processor declares the start of booting. The CPU then polls the boot processor determination register set 9 and waits for the start of booting (step ST8). On the other hand, the processors 1a+1b, which have become boot processors, set the boot start in the polling register (step ST9), then perform boot loading from the secondary storage device 2a or 2b (step 5TIO), and start executing the booted operating system. do. This operating system has
The program for the put request service shown in FIG. 3 is included, and step ST5. The processor board that did not become the boot processor in ST6 responds to the boot request in step 5T12 using inter-processor communication to the boot processor obtained in step ST7 (step 5T13), and in step 5T14 in FIG. Return the requested data. After obtaining this data, processors other than the boot processor also start executing the operating system (step 5T15).

On the other hand, if it is determined in step ST4 that a local reset is required, the pre-reset state storage register 10 is referred to and it is determined whether the self-processor was a boot processor in the past (step 5T16). In the past, when the self-processor was the boot processor, it jumps to step 5TIO and is self-independent and the secondary storage 2
Run a put from a or 2b. If the self processor is not the boot processor, step 5
Jumping to T12, a boot request is made to the boot processor, and as a result, the boot is serviced by the program shown in FIG. be done. and,
The part that requests the boot processor in step 5T12 and returns the requested data in step 5T14 is as follows:
This is done using the inter-processor communication function.

〔Effect of the invention〕

As described above, according to the present invention, in a multiprocessor system having an inter-processor communication function, a processor that can serve as a boot processor among a plurality of processors and that is determined to be normal as a result of self-diagnosis is The boot processor identification register set has a function to automatically determine the boot processor, and
When restarting a processor that has stopped during system operation, the system is configured to refer to the pre-reset state save register, which saves the state before restart, and execute bootload from the secondary storage device. The present invention has the advantage that it is not affected by abnormalities in the system, and can be easily restarted even if the system is in operation due to an abnormality.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram showing a bootload device of a multi-cross processor system according to an embodiment of the present invention, and FIG.
The figure is a block connection diagram showing the configuration of the processor in Figure 1;
FIG. 3 is a flowchart showing the operating procedure of the bootload device shown in FIG. 1, FIG. 4 is a block connection diagram showing the bootload device of a conventional multiprocessor system, and FIG. FIG. 3 is a flowchart showing the operating procedure of the device. 1a e1bp3a" 3n is a processor, 2a and 2b are secondary storage devices, 4 is a common bus, 5 is a common bus interface unit, 6 is a reset switch, 7 is a reset history register, 8 is a board identification register, 9 is a boot processor determination 10 is a pre-reset state storage register. In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] a common bus connecting a plurality of processors including a processor capable of serving as a boot processor; a common bus interface provided in each of the processors to control access to the common bus; a reset switch for local reset that puts itself into a reset state; a reset history register that stores a history of reset information of the processor obtained from the common bus interface unit and the reset switch; a board identification register that enables access to each of the processors through the bus interface; a register set for determining a boot processor that determines a boot loadable processor among the processors as a boot processor and stores this information; In a local reset, there is a pre-reset state save register that stores the past state of each processor that is saved without initialization, and this pre-reset state save register allows you to determine if the self-processor was a boot processor in the past, or if the above-mentioned boot processor is determined. A bootloading device for a multiprocessor system, comprising a secondary storage device that executes bootloading when a self-processor is determined to be a boot processor based on a register set for each processor.