JPH03133294A - Nonstandard signal detector and clock decision device - Google Patents

Abstract

PURPOSE:To detect a video signal to be a non-standard signal stably with high accuracy by monitoring the fluctuation of a phase difference of a horizontal synchronizing signal formed based on a horizontal synchronizing signal separated from a horizontal synchronizing signal and a video signal formed based on a color burst signal extracted from the video signal. CONSTITUTION:A color burst signal SC extracted by a burst extraction circuit 21 is fed to a clock generating circuit 22 and a reference horizontal synchronizing signal HR is formed via a frequency divider circuit 23 and fed to a phase measurement circuit 24. Moreover, a horizontal synchronizing signal HD separated by a synchronizing separator circuit 8 is fed to a phase measurement circuit 24 via an AFC circuit 25. The phase difference between the signals HR and HD is measured by the phase measurement circuit 24 and a phase difference data DPH is directly fed to a subtraction circuit 26 and delayed by a prescribed time at a delay circuit 27 and fed to a subtraction circuit 26. The circuit 26 calculates the difference between the input and output of the delay circuit 27 and a difference DDI is fed to a discrimination circuit 28. When the DDI is smaller than a prescribed value, the discrimination circuit 28 discriminates the video signal SV to be a standard signal and in other cases, the circuit 28 discriminates it to be a non-standard signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The second invention relates to a non-standard signal detection device and a clock determination device suitable for application to television receivers such as IDTV and EDTV.

[Prior Art] FIG. 6 shows an example of a television receiver.

In the figure, for example, an NTS signal is supplied to input terminal 1.
The C color video signal Sv is converted into a digital signal by an A/D converter 2, and then supplied to a three-dimensional signal processing circuit 3 having a memory.

Further, the video signal SV supplied to the input terminal 1 is supplied to an analog Y/C separation circuit 14, and the color signal C separated by this Y/C separation circuit (line type filter) 14 is sent to a color demodulation circuit 15. The red difference signal RY and the blue difference signal B-Y are demodulated. This color difference signal R-Y, B
-Y is converted into a point-sequential digital signal by the A/D converter 2 and then supplied to the signal processing circuit 3.

The signal processing circuit 3 processes a video signal SV and a color difference signal R-
Y/C separation processing and scanning line interpolation processing are performed for each of Y/B-Y.

Although not shown, in the still image part, Y/C separation is performed by interframe processing using the signal from one frame period before, and in the moving image part, the signal from one horizontal interval (IH) before is used to perform line separation. Y/C separation is performed by intermediate processing.

In addition, in the still image part, the interpolated scanning line signal is formed from the average value of the main scanning line signals at the same vertical position in the front and rear fields, and in the moving image part, the interpolated scanning line signal is formed from the average value of the main scanning line signals of the upper and lower lines. is formed.

Note that such a signal processing circuit 3 is disclosed in, for example, Japanese Patent Application No.
152527 in detail.

The main scanning line signal Yr and interpolation scanning line signal Y1 of the luminance signal Y outputted from the signal processing circuit 3 are supplied to the double speed conversion circuit 4 and subjected to double speed conversion processing. In other words, the main scanning line signal Yr and the interpolation scanning line signal Y1 are respectively written into the line memory and read out continuously over a period of H/2. As a result, a progressive scanning luminance signal Y' with a horizontal period of H/2 is formed, and this luminance signal Y' is supplied to the matrix circuit 5.

In addition, the color difference signal R-Y/
The B-Y interpolated scanning line signal C1 is supplied to the double speed conversion circuit 4'I to perform double speed conversion processing.

That is, this interpolated scanning line signal Ci is written into the line memory and read out twice in succession with a period of H/2. As a result, progressive scanning color difference signals R'Y' and B'-Y' with a horizontal period of H/2 are formed, and these color difference signals R'-Y' and B'-Y' are sent to the matrix circuit 5. Supplied.

The sequential scanning red, green, and blue primary color signals R'G'B' output from the matrix circuit 5 are output from the D/A
After being converted into an analog signal by a converter 6, it is supplied to a color picture tube 7.

In addition, the video signal S■ supplied to the input terminal] is supplied to a synchronization separation circuit 8 to separate a horizontal synchronization signal HD, and this horizontal synchronization signal HD is supplied to a clock generation circuit 9 composed of, for example, a PLL circuit. be done. From this clock generation circuit 9, a 1B20f signal whose phase follows the horizontal synchronization signal HD is output.
A clock CLK having a frequency of h (fh is the frequency of the horizontal synchronization signal HD) is output.

The clock CLK output from the clock generation circuit 9 is divided by two by the frequency divider 10 and then supplied to the A/D converter 2 and the signal processing circuit 3, and is also supplied to the double speed conversion circuit 4 as a write clock. .

Further, the clock CLK is supplied to the double speed conversion circuit 4 as a read clock, and is also supplied to the D/A converter 6 and the frequency divider 11.

The frequency divider 11 divides the clock CLK by 910 to form a double-speed horizontal synchronization signal H2D having twice the frequency of the horizontal synchronization signal HD. This horizontal synchronizing signal f (20) is supplied to the deflection circuit 12.

In addition, from the output signal of the D/A converter 6, the synchronization separation circuit 13
The vertical synchronizing signal VD is separated, and this vertical synchronizing signal VO
is supplied to the deflection circuit 12. Horizontal and vertical deflection control of the color picture tube 7 is performed by this deflection circuit 12, and a progressive scanning image is displayed on the screen of the color picture tube 7.

[Problems to be Solved by the Invention] Here, when the video signal S is of the NTSC standard (standard signal), the relationship between the horizontal frequency fh and the color subcarrier frequency fsc is expressed by the following formula. % Formula % (1) When this interrelationship is satisfied, the phase of the color subcarrier is inverted between lines and between frames, and the luminance signal Y and chrominance signal C that constitute the video signal Sv have a frequency interleaving of 1
Satisfied with the intermediaries.

Therefore, when the video signal SV is a standard signal,
The signal processing circuit 3 can perform good Y/C separation by inter-line processing or inter-frame processing.

However, if the video signal Sv is a reproduced signal from a home VTR, for example, and has jitter, the relationship in equation (1) may not be satisfied. In this way, when the video signal S becomes a non-standard signal, the phase inversion relationship between the input and output of the frame memory is no longer established for the color subcarrier, and the signal processing circuit 3 performs Y/C separation by interframe processing. is not performed well, resulting in deterioration of image quality.

Therefore, when the video signal Sv is a non-standard signal, it is conceivable to fix the Y/C separation processing to only the inter-line processing.

Furthermore, the clock generation circuit 9 is required to have the following characteristics depending on whether the video signal SV is a standard signal or a non-standard signal. In other words, when it is a standard signal,
In order to perform good Y/C separation in the signal processing circuit 3, it is required to generate a stable lock CLK that is not affected by jitter or the like contained in the horizontal synchronizing signal HD. On the other hand, when the signal is a non-standard signal, it is required to generate a clock CLK that quickly follows the horizontal synchronizing signal HD in order to form an interpolated scanning line signal well.

Therefore, depending on whether the video signal SV is a standard signal or a non-standard signal, the P
It is conceivable to switch the specific number of loop filters in the LL circuit.

An object of the present invention is to provide a non-standard signal detection device that can satisfactorily detect that an input video signal is a non-standard signal. Another object of the present invention is to provide a clock determination device that can accurately determine whether a system clock is phase-locked to a color burst signal.

[Means for Solving the Problems] According to the non-standard signal detection device according to the first invention, the first synchronization signal forming method forms a horizontal synchronization signal based on a color burst signal extracted from an input color video signal. means, a second synchronizing signal forming means for forming a horizontal synchronizing signal based on a horizontal synchronizing signal separated from the input color video signal, and a phase difference between the horizontal synchronizing signals from the first and second synchronizing signal forming means. a phase difference measuring means for measuring the phase difference, a delay means for delaying the phase difference measured by the phase difference measuring means for a predetermined time, a subtracting means for obtaining the difference between the input and output of the delay means, and an output from the subtracting means. and determining means for determining that the input color video signal is a non-standard signal based on the difference.

According to the clock determination device according to the second aspect of the invention, the first synchronization signal forming means forms the horizontal synchronization signal based on the color burst signal extracted from the input color video signal;
a second synchronization word forming means for forming a horizontal synchronization signal based on a system clock used in the video signal processing circuit;
a phase difference measuring means for measuring the phase difference between the horizontal synchronizing signals from the first and second synchronizing signal forming means; and a delay means for delaying the phase difference measured by the phase difference measuring means for a predetermined period of time;
Delay means - comprising subtraction means for obtaining a difference between input and output, and determination means for determining whether the system clock is phase-locked to the color burst signal based on the difference output from the subtraction means.

[Function] For example, when the input color video signal SV is of the NTSC standard (standard signal), the horizontal frequency f
The relationship between h and color subcarrier frequency fsc is as shown in the following equation.

fsc=455fh/2 In this case, the phase difference between the horizontal synchronizing signal HR formed based on the color burst signal extracted from the video signal SV and the horizontal synchronizing signal HD separated from the video signal SV is constant, and the subtracting means The output difference will be 0.

On the other hand, when the video signal S is a non-standard signal, the phase difference between the two horizontal synchronizing signals changes, and the difference output from the subtracting means becomes larger than O.

Therefore, the determining means in the first invention can determine that the video signal SV is a non-standard signal based on the difference output from the subtracting means.

Furthermore, the phase difference between the horizontal synchronizing signal HR formed based on the color burst signal extracted from the video signal S and the horizontal synchronizing signal formed based on the system clock used in the video processing circuit is such that the system clock is When the phase is locked to the signal, it is constant, and the difference output from the subtraction means is O. On the other hand, when the system clock is not phase-cocked to the color burst signal, the phase difference fluctuates, and the difference output from the subtraction means becomes larger than O.

Therefore, the determining means in the second invention can determine that the system clock is phase-locked to the color burst signal based on the difference output from the subtracting means.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 5 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In the same figure, the video signal S₻ supplied to the input terminal 1 is supplied to the Y/C separation circuit 14 and also to the fixed terminal on the a side of the changeover switch 16.

The luminance signal Y separated by the Y/C separation circuit 14 is supplied to a fixed terminal on the b side of the changeover switch 16.

The output signal of the changeover switch 16 is converted into a digital signal by the A/D converter 2, and then supplied to the signal processing circuit 3 in place of the video signal Sv in FIG.

Further, the video signal SV supplied to the input terminal l is supplied to the burst extraction circuit 21. The color burst signal SC extracted by the burst extraction circuit 21 is composed of an AFC circuit or an APC circuit, and is supplied to a lock generation circuit 22.
(n is a positive integer, and fsc is the color subcarrier frequency). This reference clock CLKR is frequency-divided by 455·n by the frequency dividing circuit 23 to form a reference horizontal synchronizing signal HR, and this horizontal synchronizing signal HR is supplied to the phase measuring circuit 24.

Further, the horizontal synchronization signal HD separated by the synchronization separation circuit 8 is supplied to the phase measurement circuit 24 via the AFC@ path 25. Here, the horizontal synchronization signal HD is stably detected by the synchronization separation circuit 8.
If the AFC circuit 25 is separated, the AFC circuit 25 is unnecessary. However, in the synchronization separation circuit 8, separation errors such as omissions or omissions due to noise etc. occur, so an AFC circuit 25 is provided to stabilize the signal.

The phase measuring circuit 24 measures the phase difference between the horizontal synchronizing signal HR and HD.

In this case, when the video signal S2 is of the NTSC standard, that is, a standard signal, the relationship between the horizontal frequency fh and the color subcarrier frequency fsc is as shown in equation (1) above.

In this case, the phase difference between the horizontal synchronizing signal HR formed based on the color burst signal SC extracted from the video signal Sv and the horizontal synchronizing signal HD separated from the video signal Sv is approximately constant regardless of time. On the other hand, when the video signal S■ is a non-standard signal, the phase difference between the two horizontal synchronizing signals HR and HD changes with time.

Phase difference data DPI (
is directly supplied to the subtraction circuit 26, and the delay circuit 27
After being delayed for a predetermined time, the signal is supplied to the subtraction circuit 26.

The subtraction circuit 26 calculates the difference between phase difference data DP)l input and output from the delay circuit 270. When the video signal SV is a standard signal, the phase difference data DPI is constant, so the difference data DOI output from the subtraction circuit 26 is 0.
becomes. On the other hand, when the video signal S■ is a non-standard signal, the phase difference data DPH varies, so the difference data DDI output from the subtraction circuit 26 becomes greater than zero.

The difference data DDE output from the subtraction circuit 26 is supplied to a determination circuit 28. The determination circuit 28 determines that the video signal SV is a standard signal if the amount of variation in the phase difference between the horizontal synchronizing signals HR and HD is within a certain range and the difference data DDI is smaller than a predetermined value, and in other cases The video signal SV is determined to be a non-standard signal. If the video signal SV is a standard signal, the determination circuit 28 outputs a low level "0", for example, and a high level "1" if the video signal SV is a non-standard signal.
11! A determination signal SD that becomes 1 is output.

This determination signal SD is supplied to the changeover switch 16 as a control signal. The selector switch 16 is set to the video signal Sv!
! When it is a signal, it is connected to the a side, while when it is a non-standard signal, it is connected to the b side.

Therefore, in the signal processing circuit 3, when the video signal S■ is a standard signal, the video signal S■ and the color difference signal R-Y
/B-Y, the - side, when the video signal Sv is a non-standard signal, the luminance signal Y and the color difference signal R-
Y/C separation processing and scanning line interpolation processing are performed for each of Y/B-Y. In other words, when the video signal Sv is a non-standard signal, the signal processing circuit 3 is supplied with the luminance signal Y separated by line interleaving processing in the analog Y/C separation circuit 14, so that the Y/C signal Y by three-dimensional processing is
-3) The separation becomes almost ineffective, and only scan line interpolation works. After all, when the video signal Sv is a non-standard signal, Y/C separation is performed only by line-to-line processing.

Further, the determination signal SD from the determination circuit 28 is supplied to the clock generation circuit 9 as a control signal. The loop filter of the PLL circuit that constitutes the clock generation circuit 9 is
When the video signal Sv is a standard signal, a signal with a large time constant is selected, whereas when it is a non-standard signal, a signal with a small time constant is selected.

FIG. 2 shows a specific configuration of the main parts in the example shown in FIG. In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals.

In the figure, the horizontal synchronization signal HD from the AFC circuit 25
(shown in FIG. 3A) is supplied to a load signal generator 241 constituting the phase measurement circuit 24.

This generator 241 is supplied with a reference clock CLKR from the clock generation circuit 22. In the generator 241, the horizontal synchronizing signal HD is sampled using the reference clock CLKR, and a one-clock width pulse (shown in FIG. B) synchronized with the horizontal synchronizing signal HD is created.

The pulse created by the creator 241 is supplied to the counter 242 as a load signal. A reference clock CLKR is supplied to this counter 242 as a count clock. The counter 242 is loaded with "0" by the load signal, and thereafter counts up by 1 every time the reference clock CLKR is supplied until the load signal is supplied again (as shown in FIG. 2C).

Count data from counter 242 is supplied to latch 243. This latch 243 is supplied with a reference horizontal synchronizing signal HR (shown in E of the same figure) formed by the frequency dividing circuit 23 as a latch pulse.

The latch 243 latches the count data from the counter 242 at the rising edge of the horizontal synchronization signal HR, and the latched count data xl.

x2. x3. -Fist- is output as phase difference data DPH' (shown in F of the figure).

By the way, when the video signal Sv is a standard signal, there is little variation in the phase difference between the horizontal synchronization signals HR and HD except in the vicinity of the vertical synchronization signal VD, so the phase difference data DPH
It is conceivable to reduce the scale of the delay element 271 constituting the 11th delay circuit 27, which will be described later, by keeping the value of . In order to provide a frame for the value of the phase difference data DPI, the counter 242 in this example uses a ripple carry RC or the like to stop the counting operation once it has counted up to a certain value. As a result, the counter 242
The actual count data from is shown in the third diagram.

In addition, the reference clock CLK from the clock generation circuit 22
R is supplied to a frequency divider 231 forming the frequency dividing circuit 23. In this frequency divider 231, frequency division is started by the trigger signal ST, and a horizontal synchronizing signal HR is formed. Trigger signal S
T is generated by a trigger generator 232 and supplied to a frequency divider 231.

The horizontal synchronizing signal HD from the AFC circuit 25 is supplied to the trigger generator 232, and the trigger signal ST is generated at the time when the horizontal synchronizing signal HD is delayed by half the value of the frame provided for the value of the phase difference data DP)l. is generated (illustrated in Figure 3G). As a result, as mentioned above, the phase difference data DP)l
Even if a frame is provided for the value of , the horizontal synchronizing signal f(R is located within the frame, so the phase measurement circuit 24 outputs the phase difference data DPI favorably.

Here, when the time axis fluctuation of the video signal S■ becomes large, the horizontal synchronizing signal HR begins to protrude from within the frame. However, in this case, the trigger generator 232 includes the phase measurement circuit 24.
A signal of high level "1" is supplied from the overflow detector 244 of
T is generated and controlled so that the horizontal synchronizing signal HR is positioned within the frame.

A ripple carry RC (shown in FIG. 3H) is supplied from the counter 242 to the detector 244, and this ripple carry RC is latched at the timing of the horizontal synchronizing signal HR. That is, when the horizontally open No. XI IN HR protrudes from within the frame, the ripple carry RC is at a high level "1", and the detector 244 outputs a signal at a high level "1".

Although not mentioned above, the vertical synchronization signal VD separated by the synchronization separation circuit 13 is supplied to the trigger generator 232, and the trigger signal S
T is generated outside the vicinity of the vertical synchronization signal VD.

Furthermore, near the vertical synchronizing signal vO, the horizontal synchronizing signals HR and H are insufficiently separated by the synchronizing separation circuit 8.
The phase difference of D may fluctuate, and it is conceivable that the determination sensitivity will deteriorate.

In order to solve this problem, the vertical synchronizing signal VD is supplied to the mask generator 233, and this V mask generator B233 generates a mask signal for the period from when the vertical synchronizing signal VD is supplied until the disturbance in the horizontal synchronizing signal (fD) subsides. SM is formed. This mask signal SM is then supplied to the gate 234, so that the horizontal synchronizing signal HR formed by the frequency divider 231 is not supplied to the phase measuring circuit 24 during the period of the mask signal SM. As a result, phase measurement in the vicinity of the vertical synchronization signal (2) 0 is stopped.

Further, the phase difference data DPI from the latch 243 of the phase measurement circuit 24 is supplied to the subtraction circuit 26 and is also supplied to the subtraction circuit 26 via the delay element 271 of the delay circuit 27 . The delay element 271 is configured using, for example, an asynchronous memory, and a delay amount is set by a delay amount setting device 272. The horizontal synchronizing signal F (R) from the frequency dividing circuit 23 is supplied to the M extension element 271 as a write and read clock. The horizontal synchronizing signal HR and the vertical synchronizing signal VD are supplied to the delay amount setter 272, and the horizontal synchronizing signal F (R) is supplied as a write and read clock. The amount of delay is set to an integral multiple of signal HR.

In this case, the delay amount is 1 field when the system clock of the signal processing circuit 3 in FIG. Since it is best in terms of efficiency to set it close to one frame, it is set close to one frame in this example.

Difference data DDI outputted from the subtraction circuit 26 is supplied to a decision unit 283 via an integral averager 281 and an absolute value converter 282 that constitute the decision circuit 28 .

In this case, the reference clock CLK is included in the differential data DDE.
Since there are fluctuations in the sampling timing of the horizontal synchronization signal HD due to R and fluctuations due to jitter generated in the synchronization separation circuit 8, these fluctuations are averaged and stabilized by the integral averager 28. Furthermore, since this value has a positive or negative signal, it is converted into an absolute value by an absolute value converter 282.

The determiner 283 determines that the amount of variation in the phase difference between the horizontal synchronizing signals HR and HD is within a certain range, and the difference data D0! is smaller than a predetermined value, the video signal Sv is determined to be a standard signal, and in other cases, the video signal SV is determined to be a non-standard signal. Then, the determination unit 28 outputs a determination signal that has a low level of "0", for example, when the video signal S is a standard signal, and has a high level of "1" when it is a non-standard signal. The determination signal is supplied to a time expander 285 via a mixer 284.

As described above, when the time axis variation of the video signal SV is large and a signal of high level 1' is output from the detector 244 of the phase measuring circuit 24, the mixing The determination signal supplied by the device 284 to the time expander 285 is, for example, a high level "1" signal indicating non-standard.

In addition, in the NTSC system, the color sequence goes around in 4 fields, so when the time expander 2nd6 receives a non-standard determination signal, the non-standard period is at least 4 fields. A determination signal indicating that the condition is true is output. The output signal of this time expander 285 is then supplied to the changeover switch 16 as the determination signal SD.

The phase difference between the horizontal synchronizing signal HR formed based on the color burst signal SC extracted from the video signal Sv and the horizontal synchronizing signal HD separated from the video signal Sv is determined by the fact that the video signal S is a standard signal as described above. At certain times, it is constant, and when the video signal S is a non-standard signal, it varies.

In this example, the phase measuring circuit 24 outputs phase difference data DPH indicating the phase difference between the horizontal synchronizing signals HR and HD, and the subtracting circuit 26 outputs difference data DDI indicating fluctuations in the phase difference. This difference data DDI
Based on this, it is determined whether the video signal SV is a standard signal or a non-standard signal. Therefore, according to this example,
When the video signal SV is a non-standard signal, it can be detected well and the Y/C separation processing can be reliably changed to line processing, and the characteristics of the clock CLK from the clock generation circuit 9 can be It can be changed reliably and image quality deterioration due to signal processing can be prevented.

Further, according to this example, as shown in FIG. 2, since a frame is provided for the value of the phase difference data DPH, the phase difference data DP
The number of bits of H can be reduced, and the scale of the delay element 271 can be reduced. Note that the counter 242 can also use a counter with a small number of bits.

Further, according to this example, as shown in FIG. 2, the mask signal SM causes the frequency dividing circuit 23 to
Therefore, the horizontal synchronization signal HR is not output, and the phase measurement circuit 24
Since phase measurement is not performed in the vertical synchronization signal VD, the influence of phase fluctuations in the vicinity of the vertical synchronization signal VD can be excluded, and non-standard signals can be detected accurately.

Further, according to this example, as shown in FIG.
Since the difference data DDI from 6 is averaged over a certain period of time by the integral averager 281 before the judgment is made, the judgment in the judgment circuit 28 can be made stably.

In the embodiment shown in FIG. 1, it is assumed that when the video signal SV is a standard signal, the clock (system clock) CLK generated by the clock generation circuit 9 is naturally phase-locked to the color burst signal SC. Depending on whether the video signal SV is a standard signal or a non-standard signal, it is determined whether Y/C separation is performed using motion adaptive processing or only between line processing, but such changes in signal processing are rather Clock CLK is Y/C for interframe processing
It is preferable to decide based on whether the separation is possible.

As shown in FIG. 4, by dividing the clock CLK from the clock generation circuit 9 by 1820 in the frequency dividing circuit 29 and supplying it to the phase measurement circuit 24, the clock CLK can be adjusted without any other circuit changes. It is possible to determine how much phase lock is achieved with the burst signal SC. In this case, the determination signal SD' output from the determination circuit 28 indicates that the clock CLK is well controlled by Y/C due to interframe processing.
When the phase lock state is such that separation can be performed, the low level is "09°", and when the state is such that separation cannot be performed satisfactorily, the high level is "1".

Therefore, in the example of FIG. 4, Y
A changeover switch 16 is controlled to determine whether the /C separation is performed by motion adaptive processing or only by interline processing.

Although the above embodiments have been described with respect to NTSC video signals, the present invention is applicable to other video signals such as PAL video signals in which there is a certain frequency relationship between the horizontal synchronization signal and the color burst signal. Of course, the present invention can be similarly applied to video signals of other systems.

[Effects of the Invention] As explained above, according to the non-standard signal detection device according to the first invention, the horizontal synchronization signal formed based on the color burst signal extracted from the video signal is separated from the video signal. The system monitors fluctuations in the phase difference of the horizontal synchronization signal formed based on the horizontal synchronization signal used to determine whether the video signal is a standard signal or a non-standard signal. And it can be detected stably. Therefore, the present invention is suitable for use as a detection device for a television receiver that changes signal processing depending on whether a video signal is a standard signal or a non-standard signal.

Further, according to the clock determination device according to the second invention, the horizontal synchronization signal is formed based on the color burst signal extracted from the video signal and the horizontal synchronization signal is formed based on the system clock used in the signal processing circuit. It is possible to detect with high accuracy and stability whether or not the system clock is phase-locked to the color burst signal by monitoring fluctuations in the phase difference of the color burst signal. Therefore, the present invention is suitable for use as a detection device for a television receiver that changes signal processing depending on whether or not the system clock is phase-locked to a color burst signal.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a configuration diagram showing an embodiment of the present invention, Fig. 2 is a specific configuration diagram of the main part of the example in Fig. 1, and Fig. 3 is an explanatory diagram of the operation of the example in Fig. 2. , FIG. 4 is a block diagram showing another embodiment of the present invention, and FIG. 5 is a block diagram of an example of a television receiver. 3 φ 8 Φ 9, 22 φ l 6 ・ 111 23 Conflict 24 Conflict 25 ・ 26 ・ 27 Conflict 28 #

Claims (2)

[Claims] (1) a first synchronization signal forming means for forming a horizontal synchronization signal based on a color burst signal extracted from an input color video signal; a second synchronizing signal forming means for forming a horizontal synchronizing signal; a phase difference measuring means for measuring a phase difference between horizontal synchronizing signals from the first and second synchronizing signal forming means; and a phase difference measured by the phase difference measuring means. a delay means for delaying the input color video signal by a predetermined time; a subtraction means for obtaining a difference between the input and output of the delay means; and a determination for determining that the input color video signal is a non-standard signal based on the difference output from the subtraction means. A non-standard signal detection device comprising means. (2) a first synchronizing signal forming means for forming a horizontal synchronizing signal based on a color burst signal extracted from an input color video signal; and a first synchronizing signal forming means for forming a horizontal synchronizing signal based on a system clock used in the video signal processing circuit. a phase difference measuring means for measuring the phase difference between the horizontal synchronizing signals from the first and second synchronizing signal forming means; and a phase difference measuring means for measuring the phase difference measured by the phase difference measuring means for a predetermined period of time. a delay means for delaying; a subtraction means for obtaining a difference between the input and output of the delay means; and a determination for determining that the system clock is phase-locked to the color burst signal based on the difference output from the subtraction means. A clock determination device comprising means.