JP2765936B2 - Chroma noise reducer - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a feedback noise reducer that reduces random noise from a chroma signal (color signal).

[Conventional technology]

As a means for reducing random noise in a video signal, a noise reducer is well known. The principle of the noise reducer is, for example, as described in "Digital Signal Processing of Images" (by Takahiko Fukibuki, published by Nikkan Kogyo Shimbun), p115 to p118, the average of n-frame video signals is obtained, and the correlation between frames is calculated. This increases the ratio between a certain video signal and uncorrelated noise. Further, the above-mentioned document states that a cyclic configuration using a memory for one frame has a large noise reduction effect with a small memory capacity.

By the way, since a video signal generally has a correlation not only between frames but also between fields and lines, it is necessary to configure a cyclic field noise reducer or a cyclic line noise reducer using a memory for one field or one line. Can also. "VC-DS1000 with NEC S Digital Noise Wiper" (TV Technology February '88) describes an example in which a cyclic field noise reducer is applied to a home VTR.

By the way, the field noise reducer is configured to change the feedback coefficient according to the strength of the correlation in order to prevent the occurrence of an afterimage when there is movement, but since it is impossible to completely determine the presence or absence of the correlation, Some afterimages are unavoidable in principle. Also, the field period is not an integral multiple of the line period. For example, in the case of the NTSC system, since one field has 262.5 lines, the operation in the field noise reducer is performed by alternately switching 262 lines and 263 lines every field period. For this reason, there is a disadvantage that the vertical resolution is degraded because the picture shifted in the vertical direction by 1/2 line due to the interlaced scanning is averaged.

These afterimages and deterioration of the vertical resolution are particularly noticeable in the luminance signal. In a home VTR, the S / N ratio (signal-to-noise ratio) of a chrominance signal is lower than the S / N ratio of a luminance signal. Therefore, a field noise reducer may be provided only for a chrominance signal.

[Problems to be solved by the invention]

FIG. 8 shows a configuration example of a chroma noise reducer. In FIG. 8, 1 is an A / D converter, 2 is a decoder, 3 is an encoder, 4 is a D / A converter, 5 is a memory, 6 is a multiplication circuit,
7, 8 are subtraction circuits, and 9 to 17 are signals.

The carrier chrominance signal 9 is converted into a digital signal 10 by the A / D converter 1 and further converted into two color difference signals, BY and RY, by the decoder 2. In this configuration example, the two color difference signals are alternately switched in the decoder 2 to output the output signal 11.
, And the signals 12 and 15 to 17 are also signals that alternately switch between BY and RY. Color difference signal
11 is subtracted from an output signal (which corresponds to the signal one field before) 15 from the memory 5 by a subtraction circuit 7 to obtain a difference signal.
It becomes 16. The difference signal 16 is multiplied by a coefficient of about 0.5 to 0.75 by the multiplication circuit 6 to become a signal 17, which is subtracted from the color difference signal 11 in the subtraction circuit 8, becomes a signal 12, and is written in the memory 5. Signal 12 is a carrier color signal by encoder 3.
13 and finally the analog signal 1 by the D / A converter 4.
Converted to 4.

Among the above operations, the principle of the decoder 2 and the encoder 3 is, for example, “synthesis and separation of a color television signal”.
(Takehiko Fukinuki, The Journal of the Institute of Television Engineers of Japan, Vol. 33, No. 4 (19
79) As described in P271～p276), it can be performed easily by selecting a sampling frequency four times the color subcarrier frequency f _sc. In the case of this configuration example, B
Since the time division processing is performed alternately between −Y and BY at the frequency of 2f _sc , the processing actually performed by the tecoder 2 and the encoder 3 simply inverts the polarity at the frequency of f _sc .

That is, in this configuration example, all processing is performed by sampling at 4f _sc (2f _sc for each color difference signal) in which the phase is locked to the burst signal.

By the way, in a home VTR, the band of the color difference signal is suppressed to about 0.5 MHz, and according to the sampling theorem, the sampling frequency should theoretically be 1 MHz or more. In practice, it is not possible to create an ideal filter, so the sampling frequency is chosen to be 1.5 to 2 times the theoretical value.
Even in that case, the sampling frequency of the color difference signal (In the case of an NTSC signal, f _sc = 3.58 MHz) is sufficient. Therefore, in the example of FIG. 8, since sampling is performed at four times the required frequency, there is a disadvantage that the memory capacity is required to be four times as much as actually required.

FIG. 9 is an example of a chroma noise reducer that does not have the above-mentioned disadvantages. 4f _sc up to the decoder 2 as in FIG.
(2f _sc for each color difference signal), but f _sc (for each color difference signal) in the subtraction circuits 7 and 8, the multiplication circuit 6 and the memory 5. Sampling is performed at the frequency of). Therefore, the memory capacity may be 1/4 of the case of FIG. By the way, when the sampling frequency is converted from a high frequency to a low frequency, thinning sampling may be performed, so that a circuit is not particularly necessary. However, in the opposite case, an interpolation circuit is required. As mentioned above, the sampling frequency in encoder 3 is 4f
_{Since sc} (2f _sc for each color difference signal) needs to be set, the interpolation circuit 18 converts the sampling frequency (data interpolation).

However, in the case of FIG. 9, the delay time of the color signal is increased by the amount of the interpolation circuit 18 as compared with FIG. When only the color signal passes through the noise reducer, the luminance signal may be passed through a delay circuit in order to match the timing with the luminance signal. However, in order to perform digital delay, an A / D and D / A converter is required, which has a disadvantage of increasing costs. On the other hand, analog delay elements are inexpensive, but it is generally difficult to flatten the group delay characteristics when trying to increase the delay time,
The waveform response deteriorates. Therefore, the configuration shown in FIG. 9 is not preferable in terms of delay time.

Next, what is important in the field noise reducer is to prevent a shift in the time axis direction between the current signal and the signal one field before. For standard NTSC signals Since (f _H is the horizontal synchronizing frequency) there is relationship, since the 4f _sc = 910f _H integral multiple of that even if the 4f _sc that is phase locked to the burst signal and the clock as in the above example, the deviation Will not occur. However, since the reproduction signal of a home VTR has jitters, the above relationship is not established, and there is no guarantee that the phase of the burst signal and the phase of the horizontal synchronizing signal have the same fixed relationship as one field before and now.
Since the output of the digital decoder is obtained by sampling each color difference signal at 2 _fsc , the worst case one field before and now Deviation occurs. To eliminate this disadvantage, typically read from or write to the arithmetic processing portion and a memory of the noise reducer using a clock locked to f _H.

The above-mentioned reference (VC with NEC S digital noise wiper)
-DS1000), the A / D conversion, decoder, encoder, and D / A conversion processes are 4f phase locked to the burst signal.
is used to clock the _sc, processing and write to memory are using the clock (752f _H) locked to f _H. However, even with such a configuration, since asynchronous clock conversion is performed, the maximum Time lag occurs. Also, two PLLs, 4f _Cs and 752f _H, are required.

Next, the prior art does not specifically describe a case where the carrier chrominance signal is distorted and becomes vertically asymmetric, but it is desirable that accurate decoding can be performed even in such a case.

SUMMARY OF THE INVENTION It is an object of the present invention to use a minimum required memory, to have a small delay time, to be able to be constituted by one system of PLL, to reduce a jitter (time shift), and to have a small error in the presence or absence of a carrier color signal. To provide a reducer.

[Means for Solving the Problems] The present invention has the following configuration. That is, a color signal demodulation means for demodulating an input carrier color signal and alternately outputting two color difference signals, an arithmetic means having an output signal of the color signal demodulation means as one input, and an output signal of the arithmetic means. Delay means for delaying a substantially constant time by using a memory; and feedback-type chroma noise for reducing the noise component contained in the input carrier color signal by inputting the output of the delay means to the other of the arithmetic means and performing an arithmetic operation. A reducer, wherein the relative phase relationship between a color difference flag signal indicating whether the output of the color signal demodulation means is one of the two color difference signals and a horizontal synchronization signal indicating a horizontal synchronization timing of the color difference signal is represented. A phase detecting means for detecting each line, and a writing means for shifting the output signal data of the calculating means on a time axis and selecting a shift amount according to the output of the phase detecting means. Data time axis shift means, and read data time axis shift means for shifting the color difference signal data output from the delay means on the time axis and selecting the shift amount according to the output of the phase detection means. The configuration is provided.

Before writing the color difference signal into the memory, a digital filter for removing the frequency component of the color subcarrier from the color difference signal is provided.

[Action]

In the present invention, writing to the memory is performed using f _sc (for each color difference signal, ), The memory capacity is substantially the minimum required.

Further, the interpolation filter only passes the color difference signal read from the memory, and the filter does not enter the path of the current signal, so that the delay time can be reduced.

The relative phase between the burst signal and horizontal sync signal And the color difference signal data to be written to the memory and the output color difference signal of the interpolation filter are shifted, so that the time shift (jitter) between the current signal and the signal one field before can be suppressed to 70 ns or less.

Further, since the filter that removes the _fsc component acts to average the upper and lower sides of the carrier color signal, the effect of the noise reducer is not reduced even if the waveform is distorted.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS.

In FIG. 1, 1 to 17 operate in the same manner as in FIG. A /
D converter 1, decoder 2, encoder 3, D / A converter 4,
The sampling frequency in the subtraction circuits 7 and 8 and the multiplication circuit 6 is 4 _fsc , which means that each color difference signal is sampled at 2 _fsc . Also, BY, RY
However, the time-division processing is alternately performed at a frequency of 2f _{sc in} the same manner as in FIG. In FIG. 1, the color difference signal 12 is stored in the memory 5.
When writing, thinning sampling is performed, and f _sc (for each color difference signal, The writing to the memory 5 is performed at the frequency of ()). Reading from the memory 5 is also performed at the frequency of _fsc , and the interpolation circuit 1
Performs interpolation of data at 9, are returned to the sampling frequency 4f _sc.

The interpolation circuit 19 performs a process of smoothly connecting the sampling points reduced by the thinned sampling, and corresponds to passing an LPF (reduced pass filter) in analog signal processing.

FIG. 2 shows a configuration example of the interpolation circuit 19. In FIG.
21 and 22 are digital LPFs and 23 is a multiplexer. In the signal 15 read from the memory 5, BY and RY are alternately arranged, but the interpolation processing needs to be performed separately in the LPF 21 and the LPF 22. And the signal 24,25 after the interpolation processing
Are alternately arranged again by the multiplexer 20.

FIG. 3 shows a signal (sampling point) in each part. In FIG. 3, a white circle indicates a BY signal and a black circle indicates an RY signal. The signal 15 before interpolation is for both B-Y and R-Y Sampling frequency. Interpolated signal 24,2
At 5, the sampling frequency is 2f _sc , and finally the multiplexer 20 alternately outputs BY and RY at a sampling frequency of 4f _sc .

The pass band of the digital filters 21 and 22 may be selected to be about 600 to 800 KHz in consideration of the fact that the color signal band in the reproduced signal of the home VTR is about 500 KHz.

As described above, according to the present embodiment, the sampling frequency of the color difference signal data to be written into the memory 5 is f _sc (for each color signal, ), And a noise reducer can be constructed with a substantially minimum memory capacity. The delay time is the sum of the delay times of the A / D converter 1, the decoder 2, the arithmetic circuit 8, the encoder 3, and the D / A converter, and the delay time of the interpolation circuit 19 is added to the color signal delay. Therefore, it is a chroma noise reducer with a small delay time.

Next, another embodiment of the present invention will be described with reference to FIG.

In FIG. 4, reference numerals 26 and 27 denote timing correction circuits, reference numeral 28 denotes a phase detection circuit, and other parts are common to FIG.

As described above, since the phase relationship between the horizontal synchronization signal and the burst signal is not fixed in the playback signal of the home VTR, if sampling is performed with a clock phase-locked to the burst signal, the signal one field before and the current signal And a time lag (jitter) of up to one sample occurs. In the case of FIG.
Since the sampling frequency of each color difference signal is 2f _sc , Jitter occurs.

The timing correction circuits 26 and 27 and the phase detection circuit 28 in FIG. 4 are circuits for reducing this jitter.

FIG. 5 shows a configuration example of the timing correction circuits 26 and 27.
In FIG. 5, 29 and 30 are D flip-flops, 31 is a multiplexer, 32 is an adder, 33 is a 1-bit shift circuit, 34 to 38 are digital signals, and 39 is a clock.

The input signal 34 is sequentially shifted to the D flip-flops 29 and 30 by the clock 39. BY and R as described above
Since the -Y signal is processed alternately, at a certain time, for example, 34 and 36 are like the BY signal, and 35 is like the RY signal. After the signals 34 and 36 are added by the adding circuit 32, they are multiplied by 1/2 by a 1-bit shift circuit. That is, the signal 37 is an average value of the signals 34 and 36. In other words, the signal 37 can be considered as a sampling point in time between the signals 34 and 36. Therefore, the multiplexer
According to the control signal 51 input to the selection input terminal S of the 31,
By selectively outputting either signal 36 or signal 37, Data can be output with a precision of.

Next, FIG. 6 shows an example of the phase detection circuit. In FIG. 6, reference numeral 40 denotes a VCO (voltage controlled oscillator), 41 denotes a phase comparison circuit,
43 is a divide-by-2 circuit, 44 is a D flip-flop, 45 is a color subcarrier, 46 is a horizontal synchronizing signal, and 51 is an output of a phase detection circuit.

The oscillation frequency of the VCO 40 is controlled by the control voltage 47 and oscillates at a frequency of 4 _fsc . The output 39 is used as a clock of the chroma noise reducer, and is input to the divide-by-2 circuit 42 to become a signal 49 having a frequency of _2fsc . The signal 49 is supplied to the D input of the flip-flop 44 and becomes a signal 50 having a frequency of _fsc by the _divide- by-2 circuit 43. The phase of the signal 50 is compared with the phase of the chrominance subcarrier 45 by the phase comparison circuit 41, and an output voltage 47 proportional to the phase difference is supplied to the VCO 40. That is, the VCO 40, the frequency divider circuits 42 and 43, and the phase comparison circuit 41 constitute a PLL (phase locked loop), and in a normal state, the signal 3
9, 49 and 50 have a fixed phase relationship with the color subcarrier 45. Color subcarrier 45, because the color burst signal in the input carrier chrominance signal 9 signals that are phase-locked, in the locked state of the PLL, 4f _sc clock 39,2f _sc 49, f _sc 50 and the input carrier chrominance signal 9 Is kept constant.

Since the Q output 51 of the D flip-flop 44 is determined by the clock, that is, the D input at the rising edge of the horizontal synchronizing signal 46, that is, the output of the signal 49, once every 1H (horizontal scanning cycle), the color subcarrier and the horizontal synchronizing signal 46 are output. Is output. As described above, since 2f _sc is a frequency at which two color difference signals are subjected to time division processing, the signal 49 can be called a color difference signal flag indicating which of the multiplexed color difference signal data. Therefore,
Since the output 51 is a phase detection result indicating the relative phase relationship between each sample of the color difference signal and the horizontal synchronizing signal in one clock unit, the output 51 is connected to the selection input of the multiplexer 31 in the time axis shift means of FIG. Thus, the shift of the sample position due to the jitter can be corrected by one clock.

In summary, in this embodiment, since sampling is performed at _4fsc which is phase-locked to the burst signal, decoding (demodulation to a color difference signal) can be easily performed only by inverting the polarity. The case, since the sampling frequency of each of the color difference signal becomes 2f _sc, when performing processing such as resetting the memory address by the horizontal synchronizing signal However, in this embodiment, the timing correction circuit
Since the sampling frequency is substantially set to 4f _sc at 26 and 27 and the jitter is controlled by the phase phase output circuit 28, the jitter is Can be suppressed.

In FIG. 1, when the input signal 9 is distorted or the linearity of the A / D converter 1 is poor, the signal 10 is vertically asymmetric. Since in the decoder 2 performs processing to reverse the sign of the input signal at a frequency of f _sc, when the vertically asymmetric input signals, since the level difference in the case of inverted if no inversion occurs, the frequency component of f _sc Will occur. When the noise reducer is turned off (the output 17 of the feedback coefficient circuit is set to zero), the frequency component of this _fsc is inversely processed by the encoder 3 with the decoder 2, so that the output 14 is only vertically asymmetric, so that the performance is particularly poor. However, turning on the noise reducer does cause a problem. That is, since only thinning sampling is performed when writing a signal to the memory 5, a level difference occurs between a case where a non-inverted point is written to the memory and a case where an inverted point is written to the memory, and this becomes a noise generation source. Would.

FIG. 7 shows still another embodiment of the present invention for eliminating such inconveniences. Reference numeral 52 denotes a digital filter, and the other components are the same as those in FIG.

The digital filter 52 can be constructed in such a manner that the multiplexer 31 shown in FIG. 5 is deleted and 37 is used as an output signal. That is, this is a circuit that takes an average value of two consecutive points, but is a digital filter that has a zero response at _fsc in the frequency domain. By inserting the digital filter 52, the above-mentioned noise can be removed from the signal written in the memory 5, so that the effect of the noise reducer is reduced even when the input signal 9 is distorted into a vertically asymmetric waveform. I will not do it.

As described above, in the embodiment, the explanation has been made using the NTSC signal.
In the case of and SECAM, a chroma noise reducer can be realized with a similar circuit configuration.

〔The invention's effect〕

According to the present invention, when writing data to the memory, the sampling frequency is lowered by thinning sampling, so that the memory capacity can be minimized. In addition, since the interpolation filter for returning the sampling frequency to the original signal does not enter the path of the current signal, the system has a small delay time.

Further, the timing correction circuit and the phase detection circuit
A chroma noise reducer with less jitter can be configured with a system PLL.

Further, the digital filter that removes the _fsc component can suppress noise generated when the input signal is vertically asymmetric.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a circuit block diagram of the interpolation circuit shown in FIG. 1, and FIG.
A timing diagram showing a temporal change of a signal of the interpolation circuit in the figure,
FIG. 4 is a circuit block diagram showing another embodiment of the present invention, FIG. 5 is a circuit block diagram of the timing correction circuit of FIG. 4,
FIG. 6 is a circuit block diagram of the phase detection circuit of FIG. 4, and FIG.
The figure is a circuit block diagram showing still another embodiment of the present invention. FIG. 8 and FIG. 9 are block diagrams showing an example of the chroma noise reducer. 1 A / D converter 2 Decoder 3 Encoder 4 D / A converter 5 Memory 6 Coefficient circuit 7, 8 Subtraction circuit 19 Interpolation circuit 26, 27 Timing correction circuit 28: Phase detection circuit 52: Digital filter.

Continuation of the front page (72) Inventor Asagiri Kuroyanagi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Home Appliance Research Laboratory, Hitachi, Ltd. (56) References JP-A-64-71287 (JP, A) JP-A-64- 86678 (JP, A) JP-A-63-87093 (JP, A) JP-A-2-265391 (JP, A) JP-A 64-5191 (JP, A) JP-A-63-227294 (JP, A) JP-A-61-13891 (JP, A) JP-A-61-228793 (JP, A) JP-A-64-58192 (JP, A) JP-A-63-187988 (JP, A) (58) (Int.Cl. ⁶ , DB name) H04N 9/64 H04N 9/78

Claims (2)

(57) [Claims] 1. A color signal demodulation means for demodulating an input carrier color signal and alternately outputting two color difference signals, an arithmetic means having an output signal of the color signal demodulation means as one input, Delay means for delaying the output signal for a substantially constant time using a memory; and a feedback type for reducing the noise component contained in the input carrier color signal by inputting the output of the delay means to the other of the arithmetic means and performing an arithmetic operation. A color difference flag signal indicating whether the output of the color signal demodulation means is one of the two color difference signals, and a horizontal synchronization signal indicating a horizontal synchronization timing of the color difference signal. Phase detection means for detecting the phase relationship line by line, and shifting the output signal data of the calculation means on a time axis;
A write data time axis shift means whose shift amount is selected according to the output of the phase detection means; and a color difference signal data output from the delay means are shifted on a time axis, and the shift amount is determined by the phase detection means. And a read data time axis shift means selected in accordance with the output of the chroma noise reducer. 2. The chroma noise reducer according to claim 1, further comprising a digital filter for removing a frequency component of a color subcarrier from the color difference signal before writing the color difference signal into the memory.