JPH03113555A - Bus repeater device - Google Patents

Abstract

PURPOSE:To apply to bus repeater device even to a multiprocessor system by controlling the driver parts for an address line, a command line, and a data line based on the state of a bus requester which acquired the bus right and controlling the flowing directions of signals of those three lines. CONSTITUTION:An identification part 33 identifies a bus right requester that acquired the bus right based on the bus right request signal sent to a basic part 1 from an extended part 2, the bus right grant signal sent to the part 2 from the part 1, and the signal showing a bus busy mode. A control part 10 controls the driver parts 34 and 40 inserted to an address line 101, a command line 102, and a data line 103 based on the identifying result (output) of the part 33 and then controls the flowing directions of the signals of those lines 101 - 103. Thus the parts 34 and 40 are controlled for the lines 101 - 103 based on the state of the bus requester (CPU, IOC, etc.) that acquired the bus right. Thus such a bus repeater device can be applied even to a multiprocessor system.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bus repeater device for expanding a bus in a computer system.

(Prior Art) FIG. 2 is a block diagram showing an example of a general computer system. In the figure, the computer system is
It consists of a basic part 1, an extension part 2, and a bus repeater device 3.

Here, the basic unit 1 includes a central processing unit (hereinafter referred to as CPU) 10 and a main memory device (hereinafter referred to as MEM) 11
and an input/output device (hereinafter referred to as IOC) 12. The CPU 10, MEMII, and 10C12 are connected to the basic bus 100. The expansion unit 2 is provided for the purpose of expanding the functions and performance of the computer system, and is made up of a plurality of l0C22s.
is connected to expansion bus 200.

Further, the bus repeater device 3 connects the basic bus 100 and the expansion bus 200, and the basic section 1 and the expansion section 2 are connected by this path repeater device 3.

FIG. 3 is a block diagram showing a conventional example of the bus repeater device 3 of FIG. 2. In the figure, address lines 101 . Command (indicating read/write cycle) line 102. Data line +03 is driver 30.3
2 of the expansion bus 200 via address lines 201.2. Command line 202. Connected to data line 203. Here, the driver 30 is always enabled, and its direction is from the basic bus 100 to the expansion bus 200. On the other hand, the driver 32 is enabled by an instruction from the decoder 31, and the direction is set by the command line 102.
determined by the state of Therefore, the direction of the driver 32 is from the expansion bus 200 to the basic bus 100 in the case of a read cycle, and from the basic bus 100 to the expansion bus 200 in the case of a write cycle.

Next, the operation will be explained.

When CPUl0 accesses l0C22 of extension unit 2, CPUl0 connects l0C of extension unit 2 to address line 101.
22 and information on the access type (read or write) are output to the command line 102. These pieces of information are transmitted via driver 30 to address lines 201 . It is sent to the command line 202 and reaches the l0C22 of the extension unit 2. At the same time, information from address line 101 is supplied to decoder 31, and the output of decoder 31 enables driver 32. Here, when the access of CPUl0 is write, CPUl0 outputs write data to the data line 103, and this write data passes through the driver 32 (in this case, the direction of the driver 32 is determined by the state of the command line 102). (from the basic bus 100 to the expansion bus 200) is sent to the data line 203.

The l0C22 of the expansion unit 2 receives the write data from the CPU l0 sent to the data line 203. Also,
When the access of CPUl0 is for reading, l0C22 of the expansion unit 2 outputs read data to the data line 203, and the read data passes through the driver 32 (in this case,
The direction of the driver 32 is from the expansion bus 200 to the basic bus 100 depending on the state of the command line 102. )
It is sent to data line 103. And the CPU 10 is
Receives read data from l0C22 of extension section 2 sent to data line +03. As described above, the CPU l0 can access the l0C22 of the expansion unit 2.

(Problems to be Solved by the Invention) However, in the conventional bus repeater device described above,
For the following reasons, the CPU is connected to the expansion bus and the resources (MEM) present on the basic bus.

There is a problem in that it cannot be used in a multiprocessor system in which the CPUs share the 10C).

(1) Since the direction of the driver 30 is unidirectional, information for a CPU existing on the expansion bus 200 to select a resource existing on the basic bus 100 cannot be sent to the basic bus 100, and information that exists on the expansion bus 200 cannot be sent to the basic bus 100. CPUs that do so cannot access resources that exist on the basic bus 100.

(2) The enable state and direction control of the driver 32 is controlled by the address line 101. of the basic bus 100. Since this is done only using the command line 102, the CP existing on the expansion bus 200
When U accesses, the driver 32 cannot be controlled.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a bus repeater device that can also be used in a multiprocessor system.

(Means for Solving the Problems) The present invention provides a basic bus to which at least a central processing unit, a main storage device, and an input/output device constituting a basic section are connected, and a basic bus to which at least an input/output device constituting an extension section is connected. In a bus repeater device that connects an expansion bus, a bus request signal from the expansion unit side to the basic unit side, a bus permission permission signal from the basic unit side to the expansion unit side, and a signal indicating that the bus is in use. an identification unit that identifies a bus right requesting source that has acquired the bus right based on the above information; a plurality of driver units that are inserted into the address line, the command line, and the data line and control the direction of the signal; and the identification unit and a control section that controls the plurality of driver sections to control the direction of the signal according to the identification result.

(Function) Therefore, the identification unit receives a bus request signal from the expansion unit side to the basic unit side, a bus permission permission signal from the basic unit side to the expansion unit side, and one
．． Based on the signal indicating that the bus is in use, the bus requestor that has acquired the bus right is identified.

The control unit controls a plurality of driver units inserted in the address line, command line, and data line according to this identification result (output), and controls the address line, command line, and data line.

Controls the direction of signal flow on the data line.

In this way, the bus requestor (for example, C
P.U.J.? ) address line,
Since the command line and data line driver sections are controlled, the present bus repeater device can also be applied to a multiprocessor system.

(Example) Next, embodiments of the present invention will be described using the drawings.

Before explaining the present invention, first, FIG. 4 shows an example of the configuration of a general multiprocessor system.

In this figure, the same reference numerals are used for the same or corresponding parts as in FIG. 2. In FIG. 4, the basic bus 100 of the basic part 1
A system bus controller (referred to as SBC) section 13 is provided.

In a multiprocessor system, a CPU that has acquired bus rights through bus arbitration can access resources existing on the bus via the bus. Therefore, in a multiprocessor system, 38
There are 0 parts 13 and signals necessary for bus arbitration. This will be explained using FIGS. 5 and 6.

FIG. 5 is a diagram showing signal relationships associated with bus arbitration between the 380 unit 13 and CPU10, 20, and FIG. 6 is a timing chart of bus arbitration.

In FIG. 5, a bus request signal 410 is sent from the CPU 10 to the 380 unit 13 as shown in FIG. 6(a).
). On the other hand, the 380 part 13
10, a bus right permission signal 411 is sent (turned on) as shown in FIG. 10(b).

Upon receiving this bus permission signal 411, the CPU 10 sends out (turns on) a bus busy signal (BBSY) 400 as shown in FIG. is off. Bus request signal 4
10 is turned off, the 380 unit 13 turns off the bus right permission signal 411 as shown in FIG. The same applies to the relationship between the CPU 20 and the 380 unit 13. 420 is a bus request signal from the CPU 20 to the 380 section 13, 421 is a bus permission signal from the 380 section 13 to the CPU 20, and 400 is a signal indicating that the bus is in use.

The present invention provides 380 parts 1 of the CPU 20 existing in the expansion part 2.
bus request signal 420 to 380 unit 13 and CP
With the bus right permission signal 421 to U20, the expansion bus 2
This system identifies whether or not the CPU 20 existing in 00 has acquired the bus right, and controls the address line, command line, and data line drivers according to this identification information, and relates to the bus repeater device 3 in FIG. It is.

FIG. 1 is a block diagram showing one embodiment of a bus repeater device according to the present invention. Here, a case will be described in which the present invention is applied to the bus repeater device 3 shown in FIG. 4 (in the present invention, it is referred to as a bus repeater device 3'). In FIG. 1, the same reference numerals are used for the same or equivalent parts as in FIGS. 3 and 5.

In FIG. 1, 33 is an identification section, and this identification section 3
0 is supplied with a bus request signal 420 from the CPU 20 to the 380 section 13, a bus permission signal 421 from the 380 section 13 to the CPU 20, and a bus busy signal 400. The identification unit 33 identifies whether or not the CPU 20 present at the expansion bus 20 has acquired bus rights, and outputs an identification information signal 300. Here, when the identification information signal 300 is at H level, it indicates that the CPU 20 existing on the expansion bus 200 has acquired the bus right.

34 and 35 are address line and command line drivers, respectively, which are always enabled. The identification part 33 is attached to the direction terminal of the driver 34,35.
The identification information signal 300 is supplied,
The directional control of the drivers 34,35 is based on this identification information signal 3.
Use for 00. Here, the direction (signal flow) of the drivers 34 and 35 is from the expansion bus 200 to the basic bus 100 when the identification information signal 300 is at the H level, and from the basic bus 100 when the identification information signal 300 is at the L level. bus 10
0 to the expansion bus 200. 36
is a decoder connected to the address line 301 between the drivers 34 and 35, and if the information output to the address line 301 selects a resource present on the basic bus 100, this decoder 36 outputs a select signal. 330 is set to the H level, and if the information output to the address line 301 selects a resource existing on the expansion bus 200, the select signal 331 is set to the L level. 37 is a NAND circuit, 38 is an OR circuit, and 39 is an AND circuit. The NAND circuit 37 is supplied with the identification information signal 300 and the select signal 330 from the decoder 36, and the OR circuit 38 is supplied with the identification information signal 300 and the select signal 330 from the decoder 36.
A select signal 331 from 6 is supplied. The outputs of the NAND circuit 37 and the OR circuit 38 are supplied to the AND circuit 39, and the output of the AND circuit 39 is supplied to the enable input terminal E of the driver 40. This driver 40 is a data line driver and is arranged between the data lines 103 and 203. The enable control of the driver 40 is performed by an AND circuit 39.
, that is, the identification information signal 300 and the selection signals 330 and 331. Here, the driver 40 is enabled when the enable input is at L level. Further, 41 is a NAND circuit, 42 is an OR circuit, and 43 is an AND circuit, and the NAND circuit 41 and the OR circuit 42 are supplied with an identification information signal 300 and a signal from a command line 302. . Then, the output of the NAND circuit 41 and the output of the OR circuit 42 are connected to the AND circuit 4.
3, and the output of the AND circuit 43 is supplied to the direction terminal of the driver 40. Therefore, the direction control of the driver 40 is performed by the identification information signal 300 and the signal on the command line 302. Here, the direction of the driver 40 is from the basic bus 100 to the expansion bus 200 when the input to the direction terminal of the driver 40 is at L level, and from the expansion bus 200 when the input to the direction terminal is at H level. 200 to the basic bus 100. Here, the decoder 36, the NAND circuit 37.41, the AND circuit 39.43, and the OR circuit 38.42 constitute a control section 44. The control unit 44 receives the identification result (output) of the identification unit 33.
Accordingly, the driver 34°35 controls the direction of the signal.
．． 40 controls.

The operation based on the above configuration will be explained below.

First, the operation when the CPU 20 residing on the expansion bus 200 acquires the bus right and accesses the resources residing on the basic bus 100 will be described. C existing on the expansion bus 200
As the PU 20 acquires the bus right, the identification information signal 300 output from the identification unit 33 becomes H level, and the direction of the drivers 34 and 35 changes from the expansion bus 200 to the basic bus 100.
Address and command information on the expansion bus 200 are sent to the basic bus 100. That is, the address information is on the address line 20.
1 to driver 35. Address line 301 and driver 3
4 to the address line 101. Also, command information is transmitted from the command line 202 to the driver 35. Command line 102 via command line 302 and driver 34
sent to.

At the same time, the basic bus 100 is on the address line 301.
Since information for selecting a resource existing in is generated, the select signal 330 which is the output of the decoder 36 becomes H level, and as a result, the enable input of the data line driver 40 becomes L level.

Here, when the access type is write, the command line 302 is at L level, so the output of NAND circuit 41 is at H level, and the output of OR circuit 42 is at H level due to the identification information signal 300 at H level. Therefore, the output of the AND circuit 43 becomes H level. Therefore, the input to the direction terminal of the driver 4o becomes H level, and C
Write data from PU204 is transferred from expansion bus 200 to basic bus 10.
Sent to 0. Further, when the access type is read, command i<302 becomes H level, so the output of the NAND circuit 41 becomes L level, and the input to the direction terminal of the driver 40 becomes L level, so the CPU 20 Glued data from resources existing on the selected basic bus 100 is sent to the expansion bus 200.

Note that when the CPU 10 existing on the basic bus 100 accesses a resource existing on the expansion bus 200, the identification information signal 300 which is the output of the identification unit 33 goes to L level,
The select signal 331 which is the output of the decoder 36 becomes L level. Therefore, since the input to the direction terminal of driver 34.5 is at L level, the direction of driver 34.35 is from basic bus 100 to expansion bus 200. Also,
Since the select signal 331 is at the L level and the identification information signal 300 is at the L level, the output of the OR circuit 38 is at the L level.

The output of the AND circuit 39 becomes L level, and the driver 40
The enable input of is at L level. Additionally, the state of command signal 302 determines the direction of driver 40. That is, when the access type is write, the command line 302 becomes L level, the output of the OR circuit 42 is L level, the output of the AND circuit 43 is L level, and therefore the input to the direction terminal of the driver 40 is L level. Therefore, the direction of the driver 40 is from the basic bus 100 to the expansion bus 200. When the access type is read, the command line 302 becomes H level, the outputs of the NAND circuit 41 and the OR circuit 42 are H level, the output of the AND circuit 43 is H level, and therefore the input to the direction terminal of the driver 40 is The signal becomes H level, and the direction of the driver 40 is from the expansion bus 200 to the basic bus 100.

As a result of the above, according to the state of the CPU that has acquired bus rights,
Control of the drivers 34, 35, 40 on the bus repeater device 3' can be carried out.

Therefore, this bus repeater device 3' can also be applied to a multiprocessor system.

Next, FIG. 7 shows details of the identification section 33 of FIG. 1. In the figure, 45 is a NOR circuit, 46 is a NAND circuit, 47 is a D-type flip-flop (hereinafter referred to as a flip-flop), 48 is a NAND circuit, 49.50 is an inverter circuit, and 51 is a NAND circuit.

Here, the bus request signal 420 and the bus permission signal 421
is supplied to the NOR circuit 45, and the output of the NOR circuit 45 and a signal 400 indicating that the bus is in use are supplied to the NAND circuit 46. The output of the NAND circuit 46 is inverted and supplied to the input terminal PR of the flip-flop 47. An identification information signal 300 is output from the output terminal Q of the flip-flop 47. The output terminal Q of the flip-flop 47 is a NAND circuit 51
is supplied to one input terminal of Further, the output from the output terminal of the flip-flop 47 is supplied to one input terminal of the NAND circuit 48. Further, a signal 400 indicating that the basic bus 100 is in use is supplied to the other input terminal of the NAND circuit 48 via an inverter circuit 49. The output of the NAND circuit 48 (signal 400 indicating that the bus is in use on the expansion bus 200 side) is supplied to the clock input terminal of the flip-flop 47, and is also supplied to the other input terminal of the NAND circuit 51 via the inverter circuit 50. supplied to The output of the NAND circuit 51 becomes a signal 400 indicating that the bus side of the basic bus is in use.

After initializing the system, a bus request signal 420. A bus permission signal 421 from the SBC unit 13 to the CPU 20. A signal 400 indicating that the bus is in use is shown in FIGS. 8(a) and 8(b).

As shown in (C), it is at H level. Therefore, NOR circuit 4
5 becomes L level, and the output of NAND circuit 46 becomes H level.
The input terminal PR of the flip-flop 46 is supplied with an H level. Further, after initialization, the identification information signal 300 is at the L level as shown in FIG. 3(d). Next, the CPU 20 sets the bus right request signal 420 to L level (ON) as shown in FIG. , the output of the NOR circuit 45 becomes H level, the output level of the NAND circuit 46 is inverted, and the input terminal PR of the flip-flop 47 is supplied with the L level. As a result, the flip-flop 47 is set, and the identification information signal 300 becomes H as shown in FIG.
level. At the same time, the CPU 20 which has acquired the bus right sets the signal 400 indicating that the bus is in use to the L level (on) as shown in FIG. 4C, and accesses the desired resource. After the access is completed, the CPU 20 sets the signal 400 indicating that the bus is in use to the H level as shown in FIG. 4(C). As a result, the flip-flop 47 is reset, and the identification information signal 300 goes to L level as shown in FIG. 3(d). On the other hand, when the CPU 10 existing on the basic bus 100 acquires the bus right, the identification section 33 does not operate, so the identification information signal 300 remains at the L level.

As described above, it is possible to identify whether or not the CPU 20 existing on the expansion bus 200 has acquired the bus right.

The present invention is not limited to this embodiment, and various applications and modifications can be made without departing from the gist of the present invention.

For example, in this embodiment, C is the bus request source.
Although the case using PU20 was mentioned, other IOC
The same thing can be said when using a processor or the like.

(Effects of the Invention) As described above, if the present invention is used, the address line is changed according to the state of the bus request source that has acquired the bus right.

Controls the driver section of the command line and data line,
Since the direction of the signal flow of the address line, command line, and data line is controlled, the present invention can be applied to a multiprocessor system.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a configuration diagram showing an embodiment of the bus repeater device of the present invention, FIG. 2 is a diagram showing an example of the configuration of a computer system, and FIG. 3 is the bus repeater device shown in FIG. 2. 3. FIG. 4 is a block diagram showing an example of the configuration of a multiprocessor system. FIG. 5 is an explanatory diagram of signals in bus arbitration. FIG. 6 is a timing chart of bus arbitration. 1 is a detailed circuit diagram of the identification unit 33 shown in FIG. 1 on the one-component side, and FIG. 1... Basic part, 2... Extension part, 3'... Bus repeater device, 10.20... CPU
. 12.22...IOC. 13... System bus controller section (SBC section),
33... Identification unit, 34, 35.40... Driver,
10 units...Basic bus, 101.201.301...
Address line, 102, 202.302... Command line, 103, 203... Data line, 200... Expansion bus.

Claims (1)

[Scope of Claims] A basic bus to which at least a central processing unit, a main storage device, and an input/output device constituting a basic part are connected, and an expansion bus to which at least an input/output device constituting an extension part are connected are connected. In the bus repeater device, the bus right is granted based on a bus right request signal from the extension section side to the basic section side, a bus right permission signal sent from the basic section side to the expansion section side, and a signal indicating that the bus is in use. an identification unit for identifying a bus right requesting source that has acquired a bus right; a plurality of driver units inserted into the address line, command line, and data line and controlling the direction of the signal; A bus repeater device comprising: a control unit that controls the plurality of driver units to control the direction of the bus repeater device.