JPH03106476U - - Google Patents

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Publication number
JPH03106476U
JPH03106476U JP1433290U JP1433290U JPH03106476U JP H03106476 U JPH03106476 U JP H03106476U JP 1433290 U JP1433290 U JP 1433290U JP 1433290 U JP1433290 U JP 1433290U JP H03106476 U JPH03106476 U JP H03106476U
Authority
JP
Japan
Prior art keywords
signal
output
outputs
phase
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1433290U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1433290U priority Critical patent/JPH03106476U/ja
Publication of JPH03106476U publication Critical patent/JPH03106476U/ja
Pending legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Circuits Of Receivers In General (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例のブロツク図、第2図
は複数のクロツク発生器を使用した実施例の図、
第3図は従来のこの種の追尾受信機のブロツク図
、第4図は追尾受信機内の信号の周波数スペクト
ラムの説明図である。 1……RF和信号入力端子、2……RF差信号
入力端子、3……位相変調器、4……周波数変換
器、5……電圧制御発振器、6……AGC増幅器
、7……第2の位相検波器、8……第1の位相検
波器、9……基準信号発振器、10……90度移
相器、11……AGCループフイルタ、12……
PLLループフイルタ、13……誤差信号検出器
、14……クロツク発生器、15……周波数制御
回路、16……増幅器、17……誤差信号出力端
子、18……復調信号出力端子。
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram of an embodiment using multiple clock generators,
FIG. 3 is a block diagram of a conventional tracking receiver of this type, and FIG. 4 is an explanatory diagram of a frequency spectrum of a signal within the tracking receiver. 1... RF sum signal input terminal, 2... RF difference signal input terminal, 3... Phase modulator, 4... Frequency converter, 5... Voltage controlled oscillator, 6... AGC amplifier, 7... Second phase detector, 8...first phase detector, 9...reference signal oscillator, 10...90 degree phase shifter, 11...AGC loop filter, 12...
PLL loop filter, 13...Error signal detector, 14...Clock generator, 15...Frequency control circuit, 16...Amplifier, 17...Error signal output terminal, 18...Demodulated signal output terminal.

Claims (1)

【実用新案登録請求の範囲】 1 アンテナからのRF差信号をクロツク信号に
よつて位相変調する位相変調器と、前記位相変調
器の出力信号と前記アンテナからのRF和信号を
合成する合成回路と、局部発信信号によつて前記
合成回路からの出力信号を周波数変換し出力する
周波数変換器と、前記周波数変換器の出力を増幅
するAGC増幅器と、前記AGC増幅器からの出
力を基準信号によつて位相検波し出力する第1の
位相検波器と、前記基準信号を出力する基準信号
発信器と、前記第1の位相検波器からの出力のう
ち所定の低域周波数成分を出力するPLLループ
フイルタと、前記PLLループフイルタの出力電
圧で制御され前記局部発信信号を出力する電圧制
御発振器と、前記基準信号の位相を90度変えて
出力する90度移相器と、前記AGC増幅器より
の出力を前記90度移相器からの出力で検波し出
力する第2の位相検波器と、前記第2の位相検波
器の出力のうち所定の低域周波数成分を出力し前
記AGC増幅器に加え前記AGC増幅器の利得を
制御するAGCループフイルタと、前記第2の位
相検波器の出力を前記クロツク信号で同期検波し
誤差信号を検出して出力する誤差信号検出回路と
を有する追尾受信機において、前記クロツク信号
を発生するクロツク発生器と、このクロツク発生
器に制御信号を送出し前記クロツク信号の周波数
を制御する周波数制御回路を備えたことを特徴と
する追尾受信機。 2 請求項1記載の追尾受信機において、第1の
位相検波器の出力を復調信号として出力する出力
端子を備えたことを特徴とする追尾受信機。 3 請求項1または請求項2記載の追尾受信機に
おいて、出力周波数が互いに異なる複数個のクロ
ツク発生器を備え、前記複数個のクロツク発生器
の出力のうち任意の1個のクロツク発生器よりの
出力を選択し前記位相変調器と前記誤差信号検出
器にクロツク信号を加えるスイツチを備えたこと
を特徴とする追尾受信機。
[Claims for Utility Model Registration] 1. A phase modulator that modulates the phase of an RF difference signal from an antenna using a clock signal, and a combining circuit that combines an output signal of the phase modulator and an RF sum signal from the antenna. , a frequency converter that converts the frequency of the output signal from the synthesis circuit using a local oscillation signal and outputs the frequency converter, an AGC amplifier that amplifies the output of the frequency converter, and an output from the AGC amplifier that converts the frequency of the output signal from the synthesis circuit using a reference signal a first phase detector that detects and outputs the phase; a reference signal oscillator that outputs the reference signal; and a PLL loop filter that outputs a predetermined low frequency component of the output from the first phase detector. , a voltage controlled oscillator that is controlled by the output voltage of the PLL loop filter and outputs the local oscillation signal; a 90 degree phase shifter that changes the phase of the reference signal by 90 degrees and outputs the same; a second phase detector that detects and outputs the output from the 90-degree phase shifter; and a predetermined low frequency component of the output of the second phase detector that outputs a predetermined low frequency component and is added to the AGC amplifier. A tracking receiver that includes an AGC loop filter that controls a gain, and an error signal detection circuit that synchronously detects the output of the second phase detector with the clock signal, detects an error signal, and outputs the detected error signal. 1. A tracking receiver comprising: a clock generator that generates a clock signal; and a frequency control circuit that sends a control signal to the clock generator to control the frequency of the clock signal. 2. The tracking receiver according to claim 1, further comprising an output terminal for outputting the output of the first phase detector as a demodulated signal. 3. The tracking receiver according to claim 1 or claim 2, comprising a plurality of clock generators with different output frequencies, and a clock signal from any one of the outputs of the plurality of clock generators. A tracking receiver comprising a switch for selecting an output and applying a clock signal to the phase modulator and the error signal detector.
JP1433290U 1990-02-15 1990-02-15 Pending JPH03106476U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1433290U JPH03106476U (en) 1990-02-15 1990-02-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1433290U JPH03106476U (en) 1990-02-15 1990-02-15

Publications (1)

Publication Number Publication Date
JPH03106476U true JPH03106476U (en) 1991-11-01

Family

ID=31517701

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1433290U Pending JPH03106476U (en) 1990-02-15 1990-02-15

Country Status (1)

Country Link
JP (1) JPH03106476U (en)

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