JPH0614511Y2 - Phase synchronization receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a phase synchronization receiver for satellite communication, and in particular,
The present invention relates to a phase synchronization receiver that prevents unnecessary phase synchronization with subcarriers that are likely to occur during telemetry reception.

[Prior Art] Conventionally, a receiver of this type is configured to use a highly sensitive phase-locked circuit in a narrow band in order to receive a weak radio wave from a satellite, and the local oscillation frequency is swept due to the narrow band. Then, it was devised to make the received signal easily phase-synchronized.

FIG. 2 shows a conventional device having such a structure.
That is, the mixer 1, the gain control amplifier 2, the phase detector 3, and the voltage control oscillator 4 form a phase locked loop (PLL).
Is formed, and the sweep oscillator 6 is inserted between the phase locked loops via the signal switch 5. The signal switch 5 is controlled by the control signal output through the synchronous detector 7 and the synchronous detector 8, and appropriately outputs the oscillation signal from the sweep oscillator 6 to the voltage controlled oscillator 4 to perform the sweep.

[Problems to be Solved] In the conventional phase locked receiver described above, when the received signal is modulated and includes subcarriers, the phase is synchronized with the subcarriers even if the local oscillation frequency is swept. As a result, the reception accuracy may be extremely reduced, which is a problem.

The present invention has been made in consideration of the above-mentioned problems,
It is an object of the present invention to provide a phase-locked receiver capable of always receiving a clear reception by synchronizing the phase with the main carrier even for a modulated reception signal.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a mixer for frequency-converting a received signal, a gain control amplifier for amplifying the output of the mixer, and an output of the gain control amplifier. A phase detector that detects the phase of the signal, a voltage controlled oscillator that forms a phase locked loop by the output of this phase detector to control the output frequency of the mixer, and an AGC that detects the output amplitude of the gain control amplifier. A synchronous detector that forms a loop to control the output amplitude of the gain control amplifier, and outputs of the phase detector and the synchronous detector are A / D
An A / D converter for conversion, a memory for storing the output from the A / D converter, a D / A converter for outputting a voltage for sweeping the output of the voltage controlled oscillator, and the D / A A signal switcher for selectively sending the output from the converter and the output from the phase detector to the voltage controlled oscillator, and sweep control over a range including the subcarrier of the signal of interest in the D / A converter. , This sweep controlled D
The output of the A / A converter is applied to the voltage controlled oscillator through the signal switch and is swept to obtain the A
Based on the data A / D converted by the / D converter, when the output of the synchronous detector exceeds the set value, it is determined that phase synchronization is possible, and among the plurality of phase-synchronizable D / A sweep voltages, Based on the central voltage value, the processor is configured to control the phase locked loop only around the central voltage value again to receive a signal having the central frequency from among a plurality of received signals. is there.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a phase synchronization receiver according to this embodiment.

In the drawing, 1 is a mixer for frequency-converting a received signal. That is, the mixer 1 converts the frequency of the received signal by comparing it with the output of the voltage controlled oscillator (VCO) 4, and outputs the converted signal to the gain controlled amplifier (AGC AMP) 2. The gain control amplifier 2 amplifies the signal whose frequency has been converted by the mixer 1 and outputs it to the phase detector 3 and the synchronous detector 7. Further, each of the detectors 3 and 7 receives the reference signal from the reference signal oscillator 9.

The phase detector 3 detects the phase of the signal input from the gain control amplifier 2 based on this reference signal. Then, the phase detector 3 normally outputs the detection signal to the voltage controlled oscillator 4 via the signal switch 5. That is, the mixer 1, the gain control amplifier 2, the phase detector 3, and the voltage control oscillator 4 form a phase locked loop (PLL).

Further, the synchronous detector 7 detects the output amplitude of the gain control amplifier 2 based on the reference signal from the reference signal generator 9. The detection signal is added to the gain control amplifier 2 again to form an AGC loop.

On the other hand, each output of the phase detector 3 and the synchronous detector 7 is A
It is converted into a digital quantity by the / D converter 10. Reference numeral 11 in the drawing denotes a memory, which stores the outputs of the respective detectors 3 and 7 converted into the above digital amount.

Further, reference numeral 12 in the figure is a microprocessor, which controls the phase locked loop based on the output data of the respective detectors 3 and 7 converted into the above digital amount according to the program written in the memory 11 and outputs a plurality of received signals. The signal having the center frequency is received from among.

That is, when the phase locked loop is not locked,
The output from the D / A converter 13, which is sweep-controlled by the microprocessor, is added to the voltage-controlled oscillator 4 and swept through the signal switch 5. After that, when the locked state is approached (the output of the A / D converted synchronous detector 7 exceeds the set value), the signal switch 5 is switched to form a phase locked loop by the output of the phase detector 3.

Further, the microprocessor 12 switches the signal switch 5 again even after the phase locked loop is locked, and the D /
Further, the A output is used for further sweeping, and a frequency that may be locked is searched for to find all the sweeping voltages (frequencies) that are locked, and the sweeping voltage is swept again so as to receive a signal having a center frequency.

That is, the microprocessor 12 is the D / A converter 1
In 3, the range including the target signal subcarrier (the range including the carrier of the telemetry signal and its subcarrier)
Is controlled by sweeping, and the output of the sweep-controlled D / A converter 13 is added to the voltage controlled oscillator 4 via the signal switcher 15 to sweep. Then, based on the A / D-converted data obtained by the A / D converter 10 thus obtained, it is determined that phase synchronization is possible when the output of the synchronous detector 7 exceeds a set value, and a plurality of phases are detected. Based on the central voltage value of the synchronizable D / A sweep voltages, the phase locked loop is controlled again only around the central voltage value, and the central frequency is selected from the plurality of received signals. Receive the signal.

Thus, since the signal having the center frequency is considered to be the main carrier, it is possible to surely obtain a clear reception signal in synchronization with the main carrier even when the reception signal is modulated.

[Effect of the Invention] As described above, according to the present invention, the processor controls the phase locked loop based on the data obtained by A / D converting each output of the phase detector and the synchronous detector, and the processor receives a plurality of received signals. Since the signal having the center frequency is received from the inside, there is an effect that it is possible to surely synchronize the phase with the main carrier and always perform clear reception even with respect to the modulated received signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a phase locked receiver according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional phase locked receiver. 1: Mixer 2: Gain control amplifier 3: Phase detector 4: Voltage control oscillator 5: Signal switcher 7: Synchronous detector 9: Reference signal generator 10: A / D converter 11: Memory, 12: Microprocessor 13: D / A converter

Claims (1)

[Scope of utility model registration request] 1. A mixer for frequency-converting a received signal, a gain control amplifier for amplifying an output of the mixer, a phase detector for detecting a phase of an output signal of the gain control amplifier, and the phase detection. -Controlled oscillator for controlling the output frequency of the mixer by forming a phase locked loop by the output of the amplifier, and detecting the output amplitude of the gain control amplifier to form an AGC loop to control the output amplitude of the gain control amplifier. A / D for each output of the above-mentioned phase detector and the above-mentioned synchronous detector.
An A / D converter for conversion, a memory for storing the output from the A / D converter, a D / A converter for outputting a voltage for sweeping the output of the voltage controlled oscillator, and the D / A A signal switcher for selectively sending the output from the converter and the output from the phase detector to the voltage controlled oscillator, and sweep control over a range including the subcarrier of the signal of interest in the D / A converter. , This sweep controlled D
The output of the A / A converter is applied to the voltage controlled oscillator through the signal switch and is swept to obtain the A
Based on the data A / D converted by the / D converter, when the output of the synchronous detector exceeds the set value, it is determined that phase synchronization is possible, and among the plurality of phase-synchronizable D / A sweep voltages, A processor for controlling the phase locked loop only around the central voltage value based on the central voltage value and receiving a signal having the central frequency from among a plurality of received signals. A characteristic phase-locked receiver.