JPH03105486A - Logic lsi incorporating programmable input/output circuit - Google Patents

Logic lsi incorporating programmable input/output circuit

Info

Publication number
JPH03105486A
JPH03105486A JP1241952A JP24195289A JPH03105486A JP H03105486 A JPH03105486 A JP H03105486A JP 1241952 A JP1241952 A JP 1241952A JP 24195289 A JP24195289 A JP 24195289A JP H03105486 A JPH03105486 A JP H03105486A
Authority
JP
Japan
Prior art keywords
input
output
eeprom
output circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1241952A
Other languages
Japanese (ja)
Inventor
Haruo Kojima
治雄 小嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1241952A priority Critical patent/JPH03105486A/en
Publication of JPH03105486A publication Critical patent/JPH03105486A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To select an input/output circuit format in a programmable state and to easily alter it on a user side by replacing a part where an aluminum master slice is applied with an EEPROM, etc., when the logic LSI is manufactured. CONSTITUTION:When only a memory transistor (TR) 5 of the EEPROM is ON, an input/output terminal 4 is a terminal with a pull-up resistance 1. Further, when only an EEPROM TR 6 is ON, the terminal 4 is an output terminal and when only an EEPROM TR 7 is ON, the terminal functions as an input terminal. Thus, the input/output terminal 4 of the LSI functions as combinations of the resistance 1, an output circuit 2, and an input circuit 3 according to combinations of ON/OFF states of the memory TRs 5, 6, and 7 of the EEPROM. Namely, there are three kinds of circuits dedicated to input and output and for both input and output plus whether or not there is the pull-up resistance, i.e. six kinds in total can be selected as the input and output circuits 2 and 3 having the EEPROM TRs 5, 6, and 7.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は,回路形式をユーザが自由に切替え可能なプロ
グラマブル入出力回路を内蔵したロジックLSIに関す
る. 〔従来の技術〕 従来の装置は,特開昭61−134997号公報に記載
のように電気的にプログラム可能な記憶素子を具備する
チップイネーブル端子制御回路のみのものであり、デー
タ等の入出力制御回路についても電気的にプログラム可
能となっているものでない.また,文献rマイクロコン
ピュータの事典」 (朝倉書店出版)に記載のように、
PLA等は、ANDアレイとORアレイから成るプログ
ラマブル交点アレイに電気的にプログラム可能な記憶素
子を組み入れたものであり、本発明でみられる,入力回
路部、出力回路部、プルアップ抵抗部の各論理ブロック
とLSIの外部インタフェース用端子の接続に、AND
アレイとORアレイから成るプログラマブル交点アレイ
を使用していない.〔発明が解決しようとする課題〕 従来のマイクロコンピュータ等のロジックLSIにおい
ては、アルミマスタスライス方式を用いて.LSIを製
造する段階で,ハードウェアの変更により入出力回路形
式を、ユーザの要求に合せて、入力専用、入出力兼用、
出力専用端子の3種の形式に切替えて製造していた.従
って、ユーザ側が一度入出力回路形式を決めた後,入出
力回路形式を変更する為には、再びLSIを製造し直さ
なければならず,多額の費用や時間を要する問題があっ
た. 本発明の目的は、EPROMやEEPROMをロジック
LSIの入出力回路に具備し、入出力回路形式をプログ
ラマブルに選択し,ユーザ側で自由に容易に変更出来る
ようにすることにある。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic LSI incorporating a programmable input/output circuit whose circuit format can be freely switched by the user. [Prior Art] A conventional device is only a chip enable terminal control circuit equipped with an electrically programmable memory element, as described in Japanese Patent Application Laid-Open No. 134997/1983, and is capable of inputting/outputting data, etc. The control circuit is also not electrically programmable. In addition, as stated in "Literature r Microcomputer Encyclopedia" (Asakura Shoten Publishing),
A PLA etc. incorporates an electrically programmable memory element into a programmable intersection array consisting of an AND array and an OR array, and each of the input circuit section, output circuit section, and pull-up resistor section seen in the present invention AND to connect the logic block and the external interface terminal of the LSI.
A programmable intersection array consisting of an array and an OR array is not used. [Problem to be solved by the invention] In conventional logic LSIs such as microcomputers, an aluminum master slice method is used. At the stage of LSI manufacturing, the input/output circuit format can be changed to input-only, input/output, or
It was manufactured with three types of output-only terminals. Therefore, once the user has decided on the input/output circuit format, in order to change the input/output circuit format, the LSI must be manufactured again, posing a problem that requires a large amount of cost and time. An object of the present invention is to provide an input/output circuit of a logic LSI with an EPROM or an EEPROM, to programmably select the input/output circuit format, and to enable the user to freely and easily change the format of the input/output circuit.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は,マイクロコンピュータ等のロジックLSI
を製造する段階で、アルミマスタスライスを適用する部
分をEPROMやEEPROM等の書きかえ可能型読み
出し専用メモリに置き換えることにより達成される.又
.EEFROMのデータ書込み回路において高圧デコー
ダに制御用レジスタを設けることにより、容易に且つ高
速にEEPROMにデーダを書き込むことが出来る.〔
作 用〕 E E P ROMは、ゲート電極を正の高圧にすると
データが消去され、常にON状態となる.ゲート電極を
GNDにすると、データが書き込まれ、常にOFF状態
になる様に動作する.EEPROMのゲート電極は、高
圧デコーダにより、正の高圧を印加するか又は、GND
にするが,プログラマプルな高圧デコーダ制御レジスタ
が,高圧デコ−ダをコントロールして、EEPROMの
メモリトランジスタを選択して,正の高圧を印加させた
り、GNDにさせたりする.このことによって,E E
 P ROMを具備した入出力回路は入力専用のもの、
入出力兼用のもの、出力専用のものの3種に,プルアッ
プ抵抗の有無を合せて計6種の回路をプログラマブルに
選択でき,ユーザ側で自由に容易に変更出来る様になる
The above purpose is for logic LSIs such as microcomputers.
This is achieved by replacing the parts to which aluminum master slices are applied with rewritable read-only memory such as EPROM or EEPROM during the manufacturing stage. or. By providing a control register in the high-voltage decoder in the EEFROM data writing circuit, data can be written to the EEPROM easily and at high speed. [
Operation] EEPROM erases data when a high positive voltage is applied to the gate electrode, and is always in an ON state. When the gate electrode is connected to GND, data is written and the device operates so that it is always in the OFF state. The gate electrode of the EEPROM is applied with a positive high voltage by a high voltage decoder or connected to GND.
However, a programmable high voltage decoder control register controls the high voltage decoder to select memory transistors in the EEPROM to apply positive high voltage or to GND. By this, E E
The input/output circuit equipped with P ROM is for input only.
A total of 6 types of circuits can be programmably selected, including 3 types for both input and output, and 3 types for output only, and with or without a pull-up resistor, allowing the user to freely and easily change the circuits.

〔実施例〕〔Example〕

以下,本発明の一実施例を図面を用いて詳細に説明する
. 第1図は,マイクロコンピュータ等のロジックLSIに
内蔵する.EEPROMを具備した入出力回路図である
。4はLSIの入出力端子、5,6,7はEEPROM
のメモリトランジスタ,1はプルアップ抵抗である.2
はマイクロコンピュータ等のロジックLSI内部の外部
への出力回路、3はマイクロコンピュータ等のロジック
LSI内部への入力回路である.EEPROMのメモリ
トランジスタ5のソース側はプルアップ抵抗1と接続し
、ドレイン側はLSIの人出力端子4と接続する.EE
PROMのメモリトランジスタ6のソース側は出力回路
2と接続し、ドレイン側はLSIの入出力端子4と接続
する。EEPROMのメモリトランジスタ7のソース側
はLSIの入出力端子4と接続し,ドレイン側は入力回
路3と接続する.EEPROMのメモリトランジスタ5
,6,7のゲートは,第4図に示されるように高圧デコ
ーダ10に接続する.EEPROMのメモリトランジス
タ5のみがONの時.LSIの入出力端子4はプルアッ
プ抵抗1付きの端子となる.EEPROMのメモリトラ
ンジスタ6のみがONの時、LSIの入出力端子4は出
力端子としての機能を有する.EEPROMのメモリト
ランジスタ7のみがONの時、LSIの入出力端子4は
入力端子としての機能を有する.このようにE E P
 ROMのメモリトランジスタ5,6.7のON状態、
OFF状態の組み合せにより,LSIの入出力端子4の
もつ機能は、プルアップ抵抗1と出力回路2と入力回路
3の組み合せとなる.EEPROMのメモリトランジス
タ5,6.7をプログラマブルに,常にON状態、もし
くはOFF状態にすることが出来ることを、以下説明す
る。
Hereinafter, one embodiment of the present invention will be explained in detail using the drawings. Figure 1 shows a system built into a logic LSI such as a microcomputer. FIG. 2 is an input/output circuit diagram equipped with an EEPROM. 4 is LSI input/output terminal, 5, 6, 7 are EEPROM
memory transistor, 1 is a pull-up resistor. 2
3 is an output circuit to the outside of a logic LSI such as a microcomputer, and 3 is an input circuit to the logic LSI such as a microcomputer. The source side of the memory transistor 5 of the EEPROM is connected to the pull-up resistor 1, and the drain side is connected to the human output terminal 4 of the LSI. EE
The source side of the PROM memory transistor 6 is connected to the output circuit 2, and the drain side is connected to the input/output terminal 4 of the LSI. The source side of the EEPROM memory transistor 7 is connected to the input/output terminal 4 of the LSI, and the drain side is connected to the input circuit 3. EEPROM memory transistor 5
, 6 and 7 are connected to a high voltage decoder 10 as shown in FIG. When only memory transistor 5 of EEPROM is ON. The input/output terminal 4 of the LSI is a terminal with a pull-up resistor 1. When only the memory transistor 6 of the EEPROM is ON, the input/output terminal 4 of the LSI functions as an output terminal. When only the memory transistor 7 of the EEPROM is ON, the input/output terminal 4 of the LSI functions as an input terminal. Like this E E P
ON state of memory transistors 5, 6.7 of ROM,
Due to the combination of the OFF state, the function of the input/output terminal 4 of the LSI becomes a combination of the pull-up resistor 1, the output circuit 2, and the input circuit 3. The fact that the memory transistors 5, 6, and 7 of the EEPROM can be programmably always turned on or off will be explained below.

第2図はEEFROMのメモリトランジスタ56,7τ
常にON状態、もしくはOFF状態になる原理を示す.
第2図において8は,EEPROMのメモリトランジス
タを示し、ゲート電圧■。
Figure 2 shows EEFROM memory transistors 56, 7τ
Demonstrates the principle of always being in the ON or OFF state.
In FIG. 2, 8 indicates a memory transistor of the EEPROM, and the gate voltage is ■.

を与えると,ソース・ドレイン間の電流は矢印方向に流
れることを示している.第3図においてIDで示される
縦軸はEEPROMのメモリトランジスタ8のソース・
ドレイン間電流を示し、vGで示される横軸はEEPR
OMのメモリトランジスタ8のゲート電圧を示す.(a
)は、EEPROMのメモリトランジスタ8のデータ消
去後の特性EEPROMのメモリトランジスタ8のデー
タ消去後の特性(α)において、しきい値電圧を十分小
さく設定すれば,常にON状態に出来,EEPROMの
メモリトランジスタ8のデータ書込み後の特性(b)に
おいて、しきい値電圧を十分大きく設定すれば,常にO
FF状態に出来る.即ちデータの消去後と書込み後では
,しきい値電圧が大きく異なり、ゲート電圧vaを、デ
ータ消去後の特性(a)とデータ書込み後の特性(b)
におけるしきい値電圧の同に設定することによりデータ
消去後は、常にON状態に,データ書込み後は、常にO
FF状態にすることが出来る。
This shows that the current between the source and drain flows in the direction of the arrow. In FIG. 3, the vertical axis indicated by ID is the source of the memory transistor 8 of the EEPROM.
The horizontal axis, which shows the current between the drains and is shown in vG, is the EEPR.
The gate voltage of memory transistor 8 of OM is shown. (a
) is the characteristic (α) of the EEPROM memory transistor 8 after data erasure.If the threshold voltage is set sufficiently small, it can always be in the ON state, and the EEPROM memory In the characteristic (b) of transistor 8 after data writing, if the threshold voltage is set sufficiently large, O
Can be set to FF state. In other words, the threshold voltage is significantly different after erasing data and after writing data, and the gate voltage va is different from the characteristics after data erasing (a) and the characteristics after data writing (b).
By setting the threshold voltage of
It can be set to FF state.

第4図は、EEPROMのメモリトランジスタのデータ
書込み回路を示す.9はEEPROMのメモリトランジ
スタ、10は高圧デコーダ、11のゲートと接続されて
おり,各E E P ROMのメモリトランジスタ9を
データ書込み状態及びデータ消去状態にする機能を有す
る。高圧デコーダ制御レジスタ11は各高圧デコーダ1
0 (EEPROMのメモリトランジスタ9の数だけ存
在する。)に、各高圧デコーダ10に接続するEEPR
OMのメモリトランジスタ9をデータ書込み状態にする
か又はデータ消去状態にするかを制御する機能を有し,
プログラマプルなレジスタである.高圧デコーダ制御レ
ジスタ11を設けることにより,EEPROMのメモリ
トランジスタ9をプログラマブルに゜常にON状態、O
FF状態にすることが出来、又,一度に全てのEEPR
OMのメモリトランジスタ9を制御出来る. 本発明によれば、EEPROMのメモリトランジスタを
具備する入出力回路部はプログラマブルに,入力専用、
入出力兼用、出力専用のもの3種に、プルアップ抵抗の
有無を合せて計6種の回路を選択出来る効果がある. 〔発明の効果〕 本発明によれば,マイクロコンピュータ等のロジックL
SIの入出力回路を、入力専用回路,入出力兼用回路、
出力専用回路の3種にゾルアップ抵抗の有無を合せた計
6種に、プログラマブルに選択できるので,ユーザ側で
自由に容易に,ユーザ側のアプリケーションに合せて、
マイクロコンピュータ等のロジックLSIの入出力回路
形式を選択出来る効果がある。
FIG. 4 shows a data write circuit for an EEPROM memory transistor. Reference numeral 9 denotes a memory transistor of the EEPROM, 10 a high voltage decoder, which is connected to the gate of 11, and has the function of putting the memory transistor 9 of each EEPROM into a data writing state and a data erasing state. The high voltage decoder control register 11 is for each high voltage decoder 1.
0 (there are as many memory transistors 9 of the EEPROM) as the EEPRs connected to each high voltage decoder 10.
It has a function of controlling whether the memory transistor 9 of the OM is in a data write state or a data erase state,
It is a programmable register. By providing the high voltage decoder control register 11, the memory transistor 9 of the EEPROM can be programmably kept in the ON state or in the OFF state.
It can be set to FF state, and all EEPRs can be turned on at once.
The memory transistor 9 of OM can be controlled. According to the present invention, the input/output circuit section including the memory transistor of the EEPROM can be programmably configured to be input-only, input-only,
The effect is that a total of 6 types of circuits can be selected, including 3 types for both input and output, and 3 types for output only, and with or without a pull-up resistor. [Effects of the Invention] According to the present invention, the logic L of a microcomputer, etc.
SI input/output circuits can be divided into input-only circuits, input/output dual-purpose circuits,
A total of 6 types, including 3 types of output-only circuits and the presence or absence of a sol-up resistor, can be selected programmably, so users can freely and easily select the circuit according to their application.
This has the effect of allowing selection of input/output circuit formats for logic LSIs such as microcomputers.

【図面の簡単な説明】[Brief explanation of drawings]

第l図は,本発明の一実施例のマイクロコンピュータ等
のロジックLSIに内蔵するEEPROMを具備した入
出力回路図、第2図はEEPROMのメモリトランジス
タにおけるゲート電圧V。 とソース・ドレイン間の電流IDの関係を説明するため
の図,第3図は、EEPROMのメモリトランジスタに
ついて、データ書込み後及びデータ消去後の電気的特性
を示した図,第4図は、EEPROMのメモリトランジ
スタのデータ書込み回路を示す図である。 1・・・プルアップ抵抗、2・・・出力回路、3・・・
入力回路,4・・一LSIの入出力端子,5,6,7,
8,9・・・EEPROMメモリトランジスタ、1o・
・・高圧デコーダ、11・・・高圧デコーダ制御レジス
タ。 第 2岡 箭 1 口 第3昆 第 4口
FIG. 1 is an input/output circuit diagram including an EEPROM built into a logic LSI such as a microcomputer according to an embodiment of the present invention, and FIG. 2 shows a gate voltage V in a memory transistor of the EEPROM. Figure 3 is a diagram showing the electrical characteristics of an EEPROM memory transistor after data writing and data erasing. FIG. 2 is a diagram showing a data write circuit of a memory transistor of FIG. 1... Pull-up resistor, 2... Output circuit, 3...
Input circuit, 4...1 LSI input/output terminal, 5, 6, 7,
8, 9...EEPROM memory transistor, 1o.
...High voltage decoder, 11...High voltage decoder control register. No. 2 Okaya 1 mouth No. 3 Kon No. 4 mouth

Claims (1)

【特許請求の範囲】 1、マイクロコンピュータ等のロジックLSIの入出力
回路において、前記入出力回路は、入力回路と、出力回
路と、書きかえ可能型読み出し専用メモリより成り、前
記入力回路と前記出力回路の切替えを前記書きかえ可能
型読み出し専用メモリを用いて可能にし、前記マイクロ
コンピュータ等のロジックLSIの端子の仕様を、プロ
グラマブルに、入力専用端子、出力専用端子、入出力兼
用端子の3種にプルアップ抵抗の有無を合せた計6種に
選択可能にしたことを特徴とするプログラマブル入出力
回路を内蔵したロジックLSI。 2、前記書きかえ可能型読み出し専用メモリはEEPR
OMあるいはEPROMであることを特徴とする特許請
求の範囲第1項記載のプログラマブル入出力回路を内蔵
したロジックLSI。 3、前記EEPROMのデータ書込み回路において、高
圧デコーダ制御レジスタを設け、一度に高圧デコーダ制
御レジスタのビットの数だけ、EEPROMメモリセル
にデータを書けることを特徴とした特許請求の範囲第2
項記載のプログラマブル入出力回路を内蔵したロジック
LSI。
[Claims] 1. In an input/output circuit of a logic LSI such as a microcomputer, the input/output circuit includes an input circuit, an output circuit, and a rewritable read-only memory, and the input circuit and the output It is possible to switch circuits using the rewritable read-only memory, and the specifications of the terminals of the logic LSI of the microcomputer etc. can be programmably divided into three types: input-only terminals, output-only terminals, and input/output terminals. A logic LSI with a built-in programmable input/output circuit, which is characterized by the ability to select from a total of six types, including the presence or absence of a pull-up resistor. 2. The rewritable read-only memory is EEPR.
A logic LSI incorporating a programmable input/output circuit according to claim 1, which is an OM or EPROM. 3. Claim 2, characterized in that the EEPROM data writing circuit is provided with a high voltage decoder control register, and data can be written into the EEPROM memory cells as many times as the number of bits in the high voltage decoder control register at one time.
A logic LSI with a built-in programmable input/output circuit as described in Section 1.
JP1241952A 1989-09-20 1989-09-20 Logic lsi incorporating programmable input/output circuit Pending JPH03105486A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1241952A JPH03105486A (en) 1989-09-20 1989-09-20 Logic lsi incorporating programmable input/output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1241952A JPH03105486A (en) 1989-09-20 1989-09-20 Logic lsi incorporating programmable input/output circuit

Publications (1)

Publication Number Publication Date
JPH03105486A true JPH03105486A (en) 1991-05-02

Family

ID=17082014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1241952A Pending JPH03105486A (en) 1989-09-20 1989-09-20 Logic lsi incorporating programmable input/output circuit

Country Status (1)

Country Link
JP (1) JPH03105486A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0637643A (en) * 1992-07-16 1994-02-10 Matsushita Electric Ind Co Ltd Adm system signal processor
US5375740A (en) * 1991-04-26 1994-12-27 Toppan Printing Co., Ltd. Manual dispenser for dispensing predetermined amounts of viscous material through actuation of a trigger

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5375740A (en) * 1991-04-26 1994-12-27 Toppan Printing Co., Ltd. Manual dispenser for dispensing predetermined amounts of viscous material through actuation of a trigger
JPH0637643A (en) * 1992-07-16 1994-02-10 Matsushita Electric Ind Co Ltd Adm system signal processor

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