JP3036962B2 - Integrated circuit test circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit incorporated in an integrated circuit for outputting a digital signal in response to a digital signal input.

[0002]

2. Description of the Related Art In recent digital integrated circuits, as the degree of integration has been improved, a large number of various circuits have been built in. Therefore, when an integrated circuit is manufactured, a test circuit for determining whether various circuits are operating correctly has become very complicated. A conventional test circuit includes a test control circuit for setting each circuit of an integrated circuit to a test state (setting a test mode) by a test signal applied to a test input terminal from the outside, and controlling a test operation of a circuit to be tested. And a test result output circuit for outputting a test result of the tested circuit. In such a test circuit, a test result of the internal circuit is provided at an output terminal different from an output terminal that is normally used, and is output from this output terminal. Alternatively, when the number of output terminals is limited, a normal output signal and a test result are switched by an output switching circuit controlled by a test control circuit, and the test result is output using a normally used output terminal. doing.

[0003]

However, in the conventional test circuit, when the number of circuits incorporated in the integrated circuit increases, the number of output terminals for outputting test results increases, and the number of output terminals on the integrated circuit chip increases. There is a disadvantage that the terminals cannot be stored. Further, when the common output terminal is also used, the number of switching circuits for switching between a test result and a normal output signal increases, and the number of components of the integrated circuit increases. Further, there is a disadvantage in that a test time is required for setting a test mode in the test control circuit and controlling each switching circuit.

[0004]

An input terminal to which an input signal is applied from the outside of the integrated circuit, a first impedance element connected between the input terminal and a predetermined voltage, and an external instruction. A test control circuit for testing a predetermined circuit inside the integrated circuit, a test result output circuit for outputting a test result of the predetermined circuit tested by the test control circuit, and a test control circuit connected between the input terminal and a predetermined voltage. By providing the second impedance element connected in parallel with the first impedance element and controlled by the output signal of the test result output circuit, the input terminal can also be used as the test result output terminal without providing a switching circuit. Is what you do.

[0005]

According to the above-described means, the internal circuit specified by the test control circuit enters a test state, and when the test is executed, the second impedance element is connected in parallel to the first impedance element according to the test result. Is connected or not connected. Thus, by measuring the input impedance as viewed from the input terminal, it is possible to determine whether the output signal of the test result is “0” or “1”.

[0006]

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is an input terminal of an integrated circuit, 2, 3,.
And 4 are first divided into functional blocks in order to realize a predetermined function by a signal applied to the input terminal 1.
Internal circuit, a second internal circuit, and a third internal circuit,
Reference numeral 5 denotes an output terminal for outputting an output signal of a function realized by the first internal circuit 2, the second internal circuit 3, and the third internal circuit 4 to the outside, and 6 denotes each of the internal circuits 2, 3, and , 4
A test input terminal for setting a test mode in the test control circuit 6, and a test control circuit 8 for controlling the second internal circuit 3 controlled by the test control circuit 6. A test result output circuit for outputting a result. A power supply voltage V _DD is applied to a gate between an input terminal 1 and the ground, and an N channel M constituting a pull-down resistor (first impedance element)
An OS 9 is connected, and an N-channel MOS 1 whose on and off is controlled by the output of the test result output circuit 8
0 (second impedance element) is connected.

In a normal operation state, the input terminal 1 is used as a signal input terminal of the first internal circuit 2, but when a signal of the power supply voltage level V _DD (H level) is not applied to the input terminal 1. Is connected to the ground voltage level (L
Level). The MOS 9 is designed to have a high on-resistance, and reduces the current flowing through the MOS 9 when an H-level signal is applied to the input terminal 1.

The test control circuit 6 controls a test mode of the first internal circuit 2, the second internal circuit 3, and the third internal circuit 4 by data input serially from a test input terminal 7. In the test mode of the second internal circuit 3, the control signal sets the second internal circuit 3 to the test state and the test result output circuit 8 to the output state. As a result, the test result of the second internal circuit 3 is output from the test result output circuit 8 to the MOS 10. This MOS 10 has a relatively high on-resistance like the on-resistance of the MOS 9 for pull-down.
When the signal applied to the gate of the OS 10 is at the H level, the MOS 9 and the MOS 10 are connected in parallel, and the impedance viewed from the input terminal 1 is smaller than that of the MOS 9 alone. Therefore, in the test mode, it is possible to determine whether the output of the test result of the second internal circuit 3 is “1” or “0” by measuring the input impedance of the input terminal 1.

The impedance can be obtained by measuring the current flowing through the input terminal 1 while an H level or L level (negative voltage) signal is applied to the input terminal 1. The test result can be taken out even when a signal is applied to the circuit 2. Also, in the embodiment of FIG.
However, the MOS 10 may be a resistor such as a diffusion resistor instead of the MOS, and the MOS 10 may be a series circuit of a MOS having a small on-resistance and a resistor such as a diffusion resistor. Further, a pull-up resistor is provided between the input terminal 1 and the power supply voltage, and a P-channel MOS controlled by the test result output circuit 8 is provided in the pull-up resistor.
May be connected in parallel.

[0010]

According to the present invention, since the output terminal of the test result can be used also as the input terminal which is normally used, there is an advantage that the number of terminals of the integrated circuit is reduced. This eliminates the need for a switching circuit and a test control circuit for controlling the switching circuit, so that there is an advantage that the circuit scale of the integrated circuit is reduced and the test time is reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 1st internal circuit 3 2nd internal circuit 4 3rd internal circuit 5 Output terminal 6 Test control circuit 7 Test input terminal 8 Test result output circuit 9 MOS 10 MOS

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/28-31/3193

Claims (1)

(57) [Claims] An input terminal to which an input signal is applied from the outside of the integrated circuit, a first impedance element connected between the input terminal and a predetermined voltage, and an inside of the integrated circuit based on an instruction from the outside. A test control circuit for testing a predetermined circuit, a test result output circuit for outputting a test result of the predetermined circuit tested by the test control circuit, and a first impedance connected between the input terminal and a predetermined voltage A test circuit for an integrated circuit, comprising: a second impedance element connected in parallel with the element and controlled by an output signal of the test result output circuit.