JPH03103951A - Memory patrol control system - Google Patents

Abstract

PURPOSE:To avoide a memory patrol to an unnecessary address by not executing the patrol at the time when data of a patrol address is registered in a buffer memory. CONSTITUTION:The write control of a main storage device 111 and a buffer memory 113 is performed in the swap system, and data is written in the buffer memory 113 in accordance with the occurrence of write, and data in the buffer memory 113 is transferred and written in the main storage device 111 when the data is the substitution object. The memory patrol for error correction is performed in the main storage device 111. A memory patrol control means 121 instructs the patrol to the address which is not registered in the buffer memory 113. Thus, the patrol to an unnecessary address is avoided.

Description

[Detailed Description of the Invention] [Summary] A memory patrol control method for compensating for soft errors by periodically reading/writing data to a main storage device, and capable of avoiding memory patrol of unnecessary addresses. A central processing unit has a main memory and a buffer memory, and controls writing to the main memory and buffer memory using a swap method. In the second memory patrol control method, the central processing unit registers data corresponding to the address of the main storage device that performs the memory patrol in the buffer memory. The present invention is characterized in that it includes a memory patrol control means that determines whether or not the address is registered in the buffer memory and instructs the memory patrol execution means to patrol the address that is not registered in the buffer memory.

[Industrial application field]

The present invention relates to a memory patrol control method that periodically reads/writes data to/from a main memory to compensate for soft errors.

[Conventional technology]

In computer systems, high-speed processing is achieved by providing a central processing unit with a buffer memory, storing data stored in a main memory in the buffer memory as appropriate, and accessing the buffer memory.

Incidentally, the swap method, which is one of the methods in which the central processing unit writes data to the buffer memory and the main storage device, is a method in which writing processing is performed only to the buffer memory in response to the occurrence of writing processing. Therefore, in the swap method, when updated data becomes a replacement target, the data is transferred to the main storage, and the contents of the main storage are updated. That is, the contents stored in the buffer memory and the main storage device do not match, and the latest data is stored in the buffer memory.

On the other hand, with memory patrol, the central processing unit periodically and sequentially reads data stored in the main memory, regardless of program access, and performs error checking to compensate for soft errors on a bit-by-bit basis. .

[Problem to be solved by the invention]

Therefore, in a computer system where the main memory and buffer memory are write-controlled using a swap method, memory patrol, which is performed while sequentially updating addresses in the main memory, is performed uniformly even for addresses that do not have the latest data. It is. In other words, it is wasteful to perform memory patrols on addresses in the main memory where data in the backup memory will eventually be replaced, and memory patrols on unnecessary addresses will further increase the memory busy rate. was.

Furthermore, due to such unnecessary memory patrols to addresses, even if a multi-bit error occurs in the memory, error processing is performed in the same way, which inevitably reduces the processing speed of the entire system.

An object of the present invention is to provide a memory patrol control method that can avoid patrolling unnecessary addresses in a computer system that has a main storage device and a buffer memory and performs write control using a swap method. .

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, the memory patrol control method of the present invention includes a main storage device 111, a central processing unit 115, and a main storage control device 119.

The central processing unit 115 has a buffer memory 113,
Writing control of the main storage device 111 and buffer memory 113 is performed using a swap method.

The main storage control device 119 includes a memory patrol execution unit 117 that periodically performs error correction on data stored in the main storage device 111 according to instructions from the central processing unit 115.

In the present invention, the central processing unit 115 determines whether or not data corresponding to the address of the main storage device 111 that performs memory patrol is registered in the buffer memory 113, and stores the data for the address that is not registered in the batza memory 113. It includes a memory patrol control stage 121 that instructs the patrol execution means 117 to perform patrol.

[For production]

Writing control is performed on the main storage device 111 and the buffer memory 113 using a swap method, and writing is performed in the buffer memory 113 in response to write occurrence, and the data in the buffer memory 113 is stored in the main storage device 111. When the data becomes a replacement target, the data is transferred to the main storage device 111 and written.

Furthermore, the main storage device 111 undergoes memory patrol for error correction.

In the present invention, since the memory patrol control means 121 instructs the buffer memory 113 to patrol addresses that are not registered, it is possible to avoid patrolling unnecessary addresses.

〔Example〕

FIG. 2 is a block diagram showing the structure of the portion of the computer system related to the method of the present invention.

In the figure, an address control unit 21 of a central processing unit 210
1, an address or patrol command for accessing the main memory 270 is sent to the address/command gate 251 of the main memory control device 250 via the address/command gate 217, and also for accessing the buffer memory 213. The address is sent to buffer memory 213. Note that an address conversion section 215 is connected to the address control section 211 and performs conversion between a logical address and a real address.

The address/command gate 251 of the main memory device 250 includes a command control unit 252 and an address gate 25 that analyze the bar 1/roll command of the main memory device W270.
A main storage device 270 is connected via 3. Further, the data read from the main storage device 270 is held in the read data register 255, and its output is sent to the error correction unit 255.
7 is input. The output of the error correction unit 257 is
The data is held in the data register 259, and its output is written to the main storage device 270 via the error correction code generator 261. Note that the buffer memory 2 of the central processing unit 210
13 and the main storage device 270 are connected to the central processing unit 21
Data game 1 connected to buffer memory 213 of
2 1 9 and the error correction unit 2 of the main storage control device 250
Data gate 263 connected to read data register 255 and write data register 259 via 57
This is done through the

The address control unit 211 accesses either the buffer memory 213 or the main storage device 270 depending on the access address.

FIG. 3 is a diagram illustrating the operation of the embodiment of memory patrol.

The operation of an embodiment of memory patrol will be described below with reference to FIGS. 2 and 3.

The address control unit 211 compares addresses that are sequentially updated to perform memory patrol (hereinafter referred to as "patrol addresses") with the corresponding addresses in the buffer memory 213, and for patrol addresses that match, Performs control to prevent execution.

That is, by performing control such that the patrol is not executed if data at that address is registered in the buffer memory 213 when executing the patrol, it is possible to avoid memory patrol for unnecessary addresses.

Note that if data of a patrol address in which the patrol address and the corresponding address in the eight sofa memory 213 do not match is registered in the buffer memory 213, the address control unit 211 as usual
70 is subjected to a predetermined memory patrol.

That is, the data at the corresponding address in the main storage device 270 is read into the read data register 255 and checked for errors in the error correction section 257. If a soft error is detected here, the data is corrected and written to the write data register 259. If no error is detected, the data is stored as is in the write data register 259.
will be written to. The data in the write data register 259 is added with a correction code to be used at the next patrol in an error correction code generation section 261, and is stored in the main storage device 2.
It is stored again at the read address of 70.

9 10 [Effects of the Invention] According to the present invention, in a computer system in which buffer memory and main storage are write-controlled in a swap manner, patrol is not executed when data of a patrol address is registered in the buffer memory. Therefore, since memory patrol to unnecessary addresses is not performed, the busy rate of the main storage device can be reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing the structure of a part of a computer system related to the method of the present invention, and Fig. 3 is a diagram explaining the operation of an embodiment of memory patrol. be. In the figure, 111 is a main storage device, 113 is a buffer memory, l1 is a block diagram of the principle of the present invention, FIG. 5 is a central processing unit, 7 is a memory patrol execution means, 9 is a main memory control device, 1 is a memory patrol control means , 0 is the central processing unit, 1 is the address control unit, 3 is the buffer memory, 5 is the address conversion unit, 7, 251 is the address/command gate, 9, 263 is the data gate, 0 is the main memory control unit, 2 is the command 3 is an address gate, 5 is a read data register, 9 is a write data register, 7 is an error correction unit, 1 is an error correction code generation unit, and 0 is a main storage device. 12 Figure 2

Claims (1)

[Claims] (1) It has a main storage device (111) and a buffer memory (113), and has the main storage device (111) and a buffer memory (113).
11) and a central processing unit (115) that performs write control of the buffer memory (113) in a swap manner; In a memory patrol control system comprising a main storage control device (119) including a memory patrol execution means (117) for performing error correction, the central processing unit (115) controls the main storage device (111) for performing memory patrol. The memory patrol execution means (117) determines whether data corresponding to the address is registered in the buffer memory (113), and executes the memory patrol for the address that is not registered in the buffer memory (113).
Memory patrol control means (1) for instructing patrol to
21) A memory patrol control method comprising: