JPH029252A - Line controller - Google Patents

Abstract

PURPOSE:To avoid production of overrun and underrun by comparing priority of processing corresponding to an interruption request from a line with priority set as to the processing corresponding to a software interruption request and executing the processing with higher priority. CONSTITUTION:When a common control circuit 27 detects a software interruption request, a scanning clock output is stopped to suppress the line scanning and an interruption request is outputted to a microprocessor 6. In the execution of the processing corresponding to the software interruption request by the microprocessor 6, the presence of the interruption request form a line is discriminated. When the interruption request from the line is outputted, the priority of the processing A corresponding to the interruption request is compared with the priority of the processing B2 corresponding to the software interruption request stored in the LM7 and if the priority of the processing A is higher than the priority of the processing B2, the processing A is executed as a 2nd processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line control device that sequentially scans a plurality of lines and sequentially processes interrupt requests from the lines.

[Prior Art] Fig. 2 shows an outline of a communication control device. In Fig. 2, 1 is a central processing unit (hereinafter referred to as CPU);
is the basic unit (hereinafter referred to as CCE), 3.3.
... 3 is a line connection unit 1 2 n (hereinafter referred to as LU).

The CPUI and CCE2 are connected via an interface bus 4, and the CCE2 and each LU3 . 3,... 3
and are connected in parallel via the interface 5.

Next, FIG. 3 is a schematic configuration diagram of C and CE 2 shown in FIG. 2. In FIG. 3, 6 is a microprocessor that controls the CeF2, 7 is a local memory that stores line control information (hereinafter referred to as L to 1), and 8 is a line number register that stores a line number (hereinafter referred to as L to 1). 9 is an interface control unit (hereinafter referred to as INT
10 is a line i (hereinafter referred to as 5CAN).

My 7 ob[j Processor 6 and INT9 are connected to -C via interface 11, and INT9 and CP are connected to 1
1 and B are connected via an interface bus 12. The microprocessor 6 and 5CANIO are connected via the interface 1:3, and the microprocessor 6 and LM7 are connected via the data bus 14. Processor 6 and LM
7 and LNR8 are connected to each other via an address bus 16.

one? The microprocessor 6 is composed of a high-speed 71 microprocessor such as a bit slice microprocessor, and has a control memory (hereinafter referred to as CM) 17 containing a procedure control program that can be used for general purposes. I'm here.

Next, FIG. 4 is a block diagram of the conventional S CANIO shown in FIG. 3. This 5CANIO is a "line scanning method" (Japanese Patent Laid-Open No. 615654) for which the applicant had previously applied.
No. 7) 1. I will judge myself.

5CANIO has four circuit boards 22a, 22b, 22c and 22 to which four lines are connected each.
d, and the software interrupt 1 storage circuit 23 is connected.
l, ``C is here.'' Each of these lines is numbered (■) to 15.
It is specified by the circuit number up to the number.

In FIG. 4, 24 is a scan mode register, 25
is a ROM, 2B is a scan register, 27 is a common control circuit,
31a, 31b, 31c, 31a are line agebuta, 32a, 32b, 32c, 32d are buta r quality encoders (hereinafter referred to as ENC), Ha
, 33b, 33c.

33d is an interrupt circuit (hereinafter referred to as INT), 34a
.

34b, 34c, and 34d are AND circuits, 41 is an address switching circuit, and 42 is an interrupt memory.

The scan mode register 24 performs priority scanning, sets the number of priority scan lines and scan skip (-j j
; maintains the number of Uskanski Tubu lines.

T? 5j47, Can is a function that scans high-speed lines more than 1'74 lines and accepts interrupt requests from high-speed lines with priority.

In addition, scan skip means that by suppressing line scanning of unused line slots, line scanning is reduced to: 1lJJ.
It is a function that should be performed in a personal manner.

Lines that undergo priority scanning (hereinafter, lines that perform priority scanning are referred to as priority lines, and lines that do not perform priority scanning are referred to as non-priority lines) are numbered from 0 to 7, depending on the number of priority scan lines. Set in ascending order′, j! do. For example, if you set the number of priority scan lines to 2, the line number O
and 1 becomes the priority line.

\No, the lines on which scan skip is performed (hereinafter referred to as scan skip lines) are set in descending order from line number 15 according to the number of scan skip lines.

For example, if the number of scan skip lines is set to 4, the lines with line numbers i5.14, I3, and 12 become scan skip lines (, -.

Priority scanning: The number of scan lines and the number of scan skip lines are set in the memory (not shown) when the system is generated. It is set in the scan mode register 24 according to the detected installation and non-installation status of each line.

The ROM 25 stores the number of priority scan lines and the number of scan skip lines input from the scan mode register 24 via the transmission line groups S and S7, as well as the scan register 2.
5 through the transmission line groups S and S9] [The priority scanning slot value and It outputs the line 1L scan times UI number without specifying the line number for line scanning.

Note that the line scanning ratio is the line scanning ratio for non-priority lines. This indicates how many times a line scanning time slot is allocated to a priority line while a slot is allocated once.

For example, when the line scanning ratio is 4, line scanning timeslots are allocated four times to the priority line while one line scanning time slot is allocated to the non-priority line.

When the line scanning ratio is 4, the priority scanning time slot value of signal line group S1 is changed from 0 to 1 while scanning all lines once.
．． 2, '3, and so on. The priority line is scanned each time the priority scan timeslot value changes. Therefore, during one cycle of line scanning, the priority line will be scanned four times and the non-priority line will be scanned once.

The scan register 2B samples the priority scanning slot value and the line scanning slot number output from the ROM 25 according to the scanning clock output from the common control circuit 27, and inputs the line scanning time slot number and the number of priority scanning slots to the signal line groups S and Sl. Output.

Signal line group S8 to which the line scanning time slot number is output
The signal line Pt is made up of four signal lines with 2 2'2 2 lumi and 1 line, respectively, in accordance with the maximum number of lines that can be accommodated by 5CANIO, which is 16 lines. '# The signal output from S8 can represent line numbers 0 to 15.

Line adapter 31. What does the information setting circuit 35 and comparison circuit 36 do in a? The information setting circuit 35 outputs the line number 0 assigned to itself to the signal line group S1, and also outputs the installed/uninstalled state of the line to the signal line S18.

Further, when the mounting status is output to the signal line S1o, the comparator circuit 36 becomes f enabled, and compares its own line number output to the signal line group S9 and the line scanning time slot number output to the signal line S8. When both numbers match, a signal line sa interrupt permission signal is output.

Note that other line adapters 31. Similarly to the line adapter 31a, the line adapters b to 31d are also provided with an information setting circuit and a comparison circuit, and output an interrupt t''111i signal to the signal lines S, S, 1, and S.

ENC32a is the interrupt code (interrupt request) from the line with line number C (Figure 1, facing down) IPT, IPT
o2, . . . Outputs the interrupt with the highest priority among the old PT Ons. ENC32b to 32d also have a similar configuration.

AND circuits 34a to 34d each output an interrupt code to common control circuit 27 when an interrupt code is output while an interrupt enable signal is being output.

Next, the conventional 5CAN1. The operation of O will be explained with reference to the timing charts of FIGS. 5 and 6.

First, the operation when the number of priority lines is O and the number of unused lines is 0, that is, all 16 lines are installed, will be described with reference to FIG.

When the number of priority lines and the number of unused lines are both 0, the scan mode register 24 sets 0 to the signal line groups S6 and S7.
Output. Therefore, the scan register 2G sequentially outputs line scanning time slot numbers in accordance with the scanning clock to perform line scanning.

Also, since the number of priority lines is O, 2. Each line scan time slot number is given as l:.

The line scanning time slot numbers are compared with the line numbers stored in the six line information setting circuits, and only the line adapters with matching line numbers are given the right to request an interrupt. For example, in the line adapter 31a, the comparison circuit 36 compares the line scanning time slot number with the information setting circuit 35.
If the line numbers match, an interrupt permission signal is output.

An interrupt code is output to the common control circuit 27 by outputting the interrupt permission signal. Furthermore, an interrupt request is output from the common control circuit 27 to the microprocessor 6, and the microprocessor 6 executes the interrupt process.

Next, the operation when the number of priority lines is 2 and the number of unused lines is 4, that is, the number of accommodated lines is 12 lines, will be explained with reference to the timing chart of FIG.

When the number of priority lines is 2 and the number of skip lines is 4, the scan mode register 24 outputs 2 and 15 to the signal line groups S6 and S7.

Therefore, k・1 is assigned to the priority lines (lines with line numbers 0 and 1).
Then, each time the number of priority scanning slots changes, the line scanning time slot number is output. Also, for non-priority lines (lines with line numbers 3 to 11), the line scan time is increased once during the time when the number of priority scan slots changes from 0 to 1.2.3 and becomes 0 again. The slot number will be output. Furthermore, line scanning time slot numbers are not output to scan skip lines (lines with line numbers 12 to 15). As a result, the line scanning ratio becomes 4, and line scanning for the scan skip line is inhibited.

When the above-described interrupt request is output, the microprocessor 6 reads the interrupt code indicating the type of interrupt request, as shown in the flowchart of FIG. ... Execute processing according to n.

By the way, in multi-line control, it is necessary to execute interrupt processing from each line within a predetermined time, so there is a restriction on one processing time. Therefore, processing that requires a long processing time is executed as split interrupt processing. That is, the divided interrupt processing consists of processing executed in response to an interrupt request from a line and processing executed in response to a software interrupt request.

FIG. 8 is a flowchart showing the operation of the microprocessor 6 when executing divided interrupt processing.

(1) When the common control circuit 27 detects the interrupt request IPT ot from the line 0 by scanning the line, it stops outputting the scanning clock to suppress the line scan and outputs an interrupt code to the microprocessor 6.

(2) Microprocessor 6 reads the interrupt code and starts executing process B corresponding to the interrupt request from line 0. After completing the execution of process B1, the microprocessor 6 accesses the interrupt memory 42 via the address switching circuit 41 using line number 0 as an address, and sets the corresponding bit. this is,
This is done by the software interrupt set command realEY.

(3) When the microprocessor 6 finishes processing B1,
5CANIO starts line scanning again.

During line scanning, the address switching circuit 41 outputs the line scanning time slot number output from the scanning register 26 as an address of the interrupt memory 42. Therefore, when the line with line number 0 is scanned, the interrupt memory 4
The software interrupt request stored in 2 is ENC
32a to 32d. Since the software interrupt request has the highest priority, the common control circuit 27 detects it.

(4) The common control circuit 27 issues a software interrupt request.
When it is output, the output of the scanning clock is stopped to inhibit line scanning, and an interrupt code is output to the microprocessor 6.

The microprocessor 6 reads the interrupt code, recognizes it as a software interrupt request, and executes process B2.

(5) Upon completion of process B2, the microphone processor 6 accesses the interrupt memory 42 using the line number O as an address via the address switching circuit 41, and resets the corresponding bit. This is done by executing a software interrupt reset instruction.

In addition, interrupt processing can be divided into more divided interrupt processing B SB
,... When dividing into B, dividing agent 1 2
This bit remains set until the n-include processing B is completed.

[Problems to be Solved by the Invention] As described above, in the divided interrupt processing, processing B is executed by the second interruption, and processing B2 is executed by the second interruption. In this case, a new interrupt request may be output from the line with line number O while the divided interrupt process is being executed. Software interrupts are interrupt requests from the line I
The highest priority is set for PT to IPT On. Therefore, no interrupt requests from the line will be accepted until the split interrupt processing is completed.

However, reading/receiving data to/from the line control LSI
If the processing corresponding to the write processing request is made to wait, there is a problem in that overruns and underruns may occur during times of high traffic.

The present invention has been made to solve the above problems,
An object of the present invention is to provide a line control device that can accept new processing requests from a line even when interrupt processing by software interrupts is being executed.

[Means for Solving the Problems] A line control device according to the present invention includes a plurality of interrupt request output means that output interrupt requests by line scanning, and an interrupt processing execution unit that executes processing corresponding to the interrupt requests. a priority setting means for setting a priority of a process corresponding to a software interrupt request among the divided interrupt processes; processing control means that compares the priority of the processing corresponding to the interrupt request with the priority set for the processing corresponding to the software interrupt request, and causes the interrupt processing execution means to execute the processing with a higher priority; We are prepared.

[Operation] In the line control device configured as described above, when the interrupt request output means outputs an interrupt request by line scanning, the interrupt processing execution means executes a process corresponding to the interrupt request. When split interrupt processing is executed by an interrupt request, a software interrupt request is output. At this time, the priority setting means sets the priority of the process corresponding to the software interrupt request. Furthermore, when an interrupt request and a software interrupt request from the line are output by the line scan, the processing control means sets the priority of the process corresponding to the interrupt request from the line and the process corresponding to the software interrupt request. The interrupt processing execution means is made to execute the processing with the higher priority by comparing the priority.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a line control device according to an embodiment of the present invention.

In FIG. 1, parts that perform the same functions as those in FIG. 4 are designated by the same reference numerals, and their explanation will be omitted.

Further, in FIG. 1, 61 is a CPU.

62 is a memory, and 63 is an interface.

The memory 62 includes a software interrupt request setting program 64 that sets and resets software interrupt requests among divided interrupt processing, a priority setting program 65 that sets the priority of processing executed by software interrupt requests, and a line scan. When an interrupt request from a line and a software interrupt request are output, a comparison program 66 is stored that executes a process with a higher priority.

Next, the operation of the line control device shown in FIG. 1 will be explained with reference to the flowchart shown in FIG.

The flowchart in FIG.
This shows the operation when an interrupt request for process A, which has a higher priority than process B2, is output while processing is divided into process B2 and process B2.

Note that process B1 is a process executed in response to an interrupt request from a line, and process B2 is a process executed in response to a software interrupt request.

(1) When the common control circuit 27 detects the interrupt request IPTo1 from the line 0 by scanning the line, it stops outputting the scanning clock to suppress the line scan and outputs an interrupt request to the microprocessor 6. The microprocessor 6 reads the interrupt code and starts executing process B1 corresponding to the interrupt request from the four-wire 0.

When the microprocessor 6 finishes executing process B1,
The priority of the next process to be executed, that is, process B2, is stored in LM7 (see FIG. 3), and a software interrupt request is generated.

(3) Once the microprocessor 6 executes process B1, 5CANIO starts line scanning again. During line scanning, the address switching circuit 4I outputs the line scanning S11' slot number output from the scanning register 26 as the address of the interrupt memory 42.

When the line with line number O is scanned, the interrupt memory 42
The software interrupt request stored in ENC3
2a. In this case, even if the line with line number 0 outputs a high-level interrupt request IPT o, the priority encoder 32a will output a software interrupt request code.

Note that a high-level interrupt request is a one-character transmission/reception completion interrupt from a line control LSI, etc., and if the interrupt processing corresponding to the high-level interrupt request is not performed within a certain period of time, the line will be interrupted. An error occurs.

Particularly in high-speed lines, overruns and underruns will occur on the line if processing is not performed in a short period of time.

When the common control circuit 27 detects a software interrupt request, it stops outputting the scanning clock to inhibit line scanning, and outputs an interrupt request to the microprocessor 6.

When executing processing corresponding to a software interrupt request, the microprocessor 6 determines whether or not there is an interrupt request from the line. To determine whether there is an interrupt request from the line, for example, temporarily reset the corresponding bit in the interrupt memory 42, release the software interrupt request, and then re-enter the ENC.
This can be achieved by reading the output of 32.

Since the microprocessor 6 receives an interrupt request from the line, it compares the priority of process A corresponding to the interrupt request with the priority of process B2 corresponding to the software interrupt request stored in LM7. In the microprocessor 6, the priority of process A is process B2.
Since the priority is higher than that of , process A is executed as the second process.

When microprocessor 6 finishes executing process A, 5
CANIO scans the line again. Since there is no new interrupt request from the line, the microprocessor 6 executes process B2 as the third process.

[Effects of the Invention] As explained above, according to the present invention, the priority of the software interrupt request is set when the divided interrupt processing is executed, and the interrupt request from the line and the software interrupt request are When output, the priority of the process corresponding to the interrupt request from the line is compared with the priority set for the process corresponding to the software interrupt request, and the process with the higher priority is executed. Therefore, it is possible to obtain a line control device in which overruns and underruns do not occur.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a line control device according to an embodiment of the present invention, and FIG. 2 is a schematic configuration of a communication control device.
Figure 3 is an outline (X1 diagram) of the basic unit shown in Figure 2, Figure 4 is a schematic configuration diagram of a conventional line control device, and Figures 5 and 6 are FIGS. 7 and 8 are timing charts showing the operation of the control device; FIGS.
The figure is a flowchart showing the operation of the line control device shown in FIG. i o--Line scanning circuit (S CAN), 22a
, 22b. 22c, 22d... Line board, 23... Software interrupt storage circuit, 24... Scan mode register, 25... ROM, 26... Scan register, 27
... common control circuit, 31a, 31, b, 31c,
31d-=line adapter, 32a 132b %32
c, 32d...Priority encoder, 33
a. 33b, 33e, 33d--interrupt circuit, 34a
, 34b, 34c, 34d...AND circuit,
35... Information setting circuit, 38... Comparison circuit, 41.
・Address switching circuit, 42... Interrupt memory, 61...
・CPU, 62...Memory, 63...Interface, C4...Software interrupt request setting program, 65...Priority setting program, 66...
・Comparison program. 5n.

Claims (1)

[Claims] A division consisting of a first process executed by outputting a line interrupt request and a second process executed by a software interrupt request output after the first process is finished. a plurality of interrupt request output means for outputting, by line scanning, interrupt requests from lines corresponding to a plurality of processes including interrupt processing and each having a priority set; and a plurality of interrupt request output means corresponding to the interrupt requests. In a line control device having an interrupt processing execution means for executing a process, a priority setting means for setting a priority of a second process corresponding to the software interrupt request, and a priority setting means for setting a priority of a second process corresponding to the software interrupt request; When the request and the software interrupt request are output, the priority of the process corresponding to the interrupt request from the line is compared with the priority set for the second process corresponding to the software interrupt request. A line control device comprising: processing control means for causing the interrupt processing execution means to execute a process with a higher priority.