JPH0290320A - Pseudo random number generating circuit - Google Patents

Abstract

PURPOSE:To produce in real time a random number series having the high random properties and a long cycle in a simple constitution by combining the pseudo random numbers of different cycles which are read out of a memory circuit based on the output random number value with a pseudo random number of a prescribed cycle via a necessary gate. CONSTITUTION:A pseudo random number of a cycle (n) is produced from an M series generating circuit 11 containing a shift register 1 and an exclusive OR gate 2. At the same time, a pseudo random number generating circuit 12 uses a clock counter 3 as a read control circuit and reads a ROM 4 which stores the random number data having the high random properties and a long cycle n' by means of a physical phenomenon, etc. Thus a pseudo random number of the cycle n' is obtained. These random numbers are processed by the exclu sive OR gates 13a-13e and a pseudo random number of a cycle n'' is produced. In such a simple constitution, it is possible to output in real time a pseudo random number which has the high random properties of the random number of the cycle n' and a long cycle equal to the least common multiple of cycles n and n''. The same effect is also secured with use of an exclusive NOR gate.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a pseudo-random number generation circuit that generates pseudo-random numbers consisting of a signal sequence of 0 and 1. The present invention relates to a pseudorandom number generation circuit suitable for generating pseudorandom numbers.

[Conventional technology]

As for conventional technology, the 1-multiplication type congruence method and the mixed type congruence method are applied to computers, as described in "Knowledge of Random Numbers" by Kazumasa Wakimoto, published by Hokka Publishing, pages 26 to 35, published in 1970. How to generate random numbers by
5. A method of generating pseudorandom numbers using physical phenomena, as described on pages 16 to 20 of the 1978 publication.
There is also a method of generating the M-sequence using an M-sequence generation circuit consisting of a shift register 1 and an exclusive-OR (E-OR) gate as shown in FIG. Regarding M-sequence generation circuits, see "Coding Theory" by Hideki Imai and Yoshihiro Iwadare.

Co-authored by Hiroshi Miyayo, Shokodo, 128-12, published in 1973.
It is described on page 9.

[Problem to be solved by the invention]

Among the conventional techniques mentioned above, methods for generating random numbers by applying the multiplicative congruential method and mixed congruential method to computers generate a large amount of random numbers in a short period of time in order to generate highly random numbers. However, the method of generating random numbers using physical phenomena has problems such as requiring a large-scale device configuration for generating random numbers and making control difficult. Further, the method of generating random numbers using a 1M sequence generation circuit has the advantage that the 0 circuit configuration is simple, but there is a problem that the randomness characteristics of the obtained random number sequence are not good.

An object of the present invention is to generate a random number sequence with high randomness and a long period in real time. The purpose of the present invention is to provide a random number generation circuit with a simple configuration.

[Means to solve the problem]

The above object consists of a first pseudo-random number generation circuit that generates one period of pseudo-random numbers, a memory circuit that stores the generated random number itself as data in advance, and a control circuit that controls data reading from the memory circuit. a second pseudo-random number generation circuit that generates pseudo-random numbers with a period of 9'(rL'≠rL); and an exclusive OR (E-ORI'-to or - This is achieved by constructing a pseudo-random number generation circuit using an E-NOR gate.

[Effect]

Physical dust inside the storage circuit of the second pseudo-random number generation circuit.

Random number data with a high degree of randomness obtained by using an image, etc. is accumulated for a desired period length, and a second pseudo-random number with a high degree of randomness with a period length is generated by reading out the data using a readout control circuit. let Regarding this second pseudo-random number and the first pseudo-random number obtained by the first pseudo-random number generation circuit of one period, an exclusive OR (E-
By performing exclusive OR using the OR) gate, the third pseudo-random number output maintains the properties of the second pseudo-random number and becomes highly random, and its period is Since the period of the third pseudo-random number is longer than the period of the first and second pseudo-random numbers, the period of the third pseudo-random number is the least common multiple of Since the second pseudo-random number is generated, high-speed pseudo-random number generation is possible.
The third pseudo-random number can be generated at high speed by combining a circuit that can generate pseudo-random numbers at a speed equal to or faster than that of the pseudo-random number generation circuit. Similarly, when using an Exclusive Noah (E-NOR) gate, the same effect as the E-OR gate can be obtained by simply inverting the third pseudorandom number ``1'' and O''. It will be done.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows the configuration of an embodiment. The circuit of the embodiment includes a pseudo-random number generation circuit 12 consisting of a counter 3 driven by a clock that provides pseudo-random number generation timing and a read-only memory (ROM) 4 that uses the output of the counter 3 as an address confirmation signal; The input (IN) of shift register 1 is input to the Qc and Qg terminals of shift register 1 and shift register l driven by the clock of
Exclusive OR (E-OR) that outputs a signal to the terminal
An M-sequence generation circuit 11 consisting of a gate 2, one signal among the 5 parallel, 4 first pseudo-random number signals output from the shift register 1 of the M-sequence generation circuit 11, and a ROM 4 of the pseudo-random number generation circuit 12. It is constituted by E-OR gates 13α to 13g which input the 1@ out of the 5 parallel second pseudo-random number signals and output a 5-bit long pseudo-random number signal. In this example, E-OR gates 13α to 13g
Generates a pseudo (IJ random number) with a concave range of O to 31 in decimal value.

Next, I will explain the operation. The pseudo-random number generation circuit of the embodiment is driven by a clock input from the outside, the counter 3 performs a count-up operation based on the clock, and the shift register 1 performs a shift operation. First 0
Regarding the operation of the M-sequence generation circuit 11, the atomic polynomial for M-sequence generation in the embodiment is X'+X''+1,
The internal state of the shift register 1 changes in cycles of 2-1=31 clocks. Therefore, the QA-Q of the shift register
From the 1iX terminal, 31 clocks are counted as one cycle, and 5
Parallel pseudo-random number signals are output and E-OR gate 13α~
Enter in 13g. Next, interference with the pseudo random number generation circuit 12 will be explained. RO consisting of 12 pseudorandom number generation circuits
M4 stores, for example, finite-length pseudo-random number data extracted from an ideal infinite-period random number series obtained in advance by a method using physical phenomena (the counter 3 counts by a clock). The output of counter 3 specifies the read address of ROM 4,
Pseudo-random number data stored in advance is read out from the ROM 4 in sequence and sent to the E-OR gate 13α as 5 parallel pseudo-random number signals.
~131. At this time, the pseudo-random number signal output from the ROM 4 is determined by the count period of the counter 3. E-OR gates 13α to 13g.

The M-sequence generation circuit 11 and the pseudo-random number generation circuit 12 take the exclusive OR of the two received pseudo-random number sequences and output the result as a desired pseudo-random number sequence. At this time, the pseudo-random number signals output from the E-OR gates 13α to 13e have a randomness equal to or greater than the randomness of the pseudo-random number signals input from the pseudo-random number generation circuit 12 to the E-OR gates 13α to 13g. This point will be explained below.

First, the equiprobability of the pseudorandom values output from E-OR (E-OR) 13α to 13- will be explained. Focusing on a particular gate of the E-OR gates 13α to 13g, for example 13α, the E-OR gate 13α receives a pseudo-random number signal from the QA terminal of the shift register 1 and the ROM 4 terminal. The pseudo-random number signal received by the shift register is such that the proportion of the signal value "1" in the total output signal is 1.
6/31. Similarly, the ratio of signal values "1" to the total output signal of the pseudorandom number signal received from ROM4 is 1/5/31.
2+8. Similarly, the ratio occupied by 0'' is 1/2-1.

Here, ε is a value indicating the stochastic bias that occurs when a series of random numbers in a finite interval is extracted from random numbers with an ideal series length of infinite, such as natural random numbers, and stored in the ROM, and RO
The longer the data length accumulated in M4 is, the closer 1ε1 is to O (.From the above, the ratio of the signal value "1" to the pseudorandom signal output from the E-OR gate 13α is P.
The ratio po of 1 and "0" is obtained from the following formula.

, 7 PG ”-×(' ) + as×(2+g)==
1 + 1.

P, = tan x (↓+e) ten tan x (-!-g ＞=1
1゜Here, E-OR13a is present since e is 1 within the membrane.
The difference in the probability of appearance of "0" and "1" in the pseudorandom number signal output from is extremely small (p, -p1=E-t).

The same thing holds true for the pseudo random number signals output from the E-OR gates 13b to 13-. Also, ROM4 glue, -
The pseudo-random number signals simultaneously output from the D4 terminal are independent from each other and also independent from the pseudo-random number signals output from the QA to Qg terminals of the shift register 1 of the 1M sequence generation circuit 11, so as a result, E-OR goo) 1
Regarding the pseudo random number signals output from 3a to 131,
Mutual independence is maintained.

Therefore, the E-OR gates 13a to 13C generate values O to 31 in decimal value with almost equal probability. Furthermore, the pseudo-random number signals output from the Do-D4 terminal of the ROM 4 can be considered to be generated independently of each other in time series within a range of one cycle n or less.

As mentioned above, since the pseudorandom number signals output from the shift register 1OQA to Qg terminals are generated independently, the desired pseudorandom number signals output from the E-OR gates 13α to 131 are generated in a time-series manner. They can be considered to occur independently.

Next, since the period of the pseudorandom number signal from the 1M sequence generation circuit 11 is 2-1 = 31 and the period of the pseudorandom number signal from the pseudorandom number generation circuit 12 is n, the E-OR gate 13α~
The period of the desired pseudorandom signal output from 13g is the length of the least common multiple of both! 0. When rL≠31, the period of the pseudorandom number signal from the M sequence generation circuit 11 is 31.
The length of one period is longer than the period of the pseudorandom number signal from the pseudorandom number generation circuit 12. In particular, rL and 3
If 1 and 1 are mutually cumulative, the period L is the longest and L=
It will be 3 torr.

As described above, according to the present invention, a pseudorandom number signal with high randomness and a long period can be generated in real time with a simple circuit configuration.

FIG. 2 shows the configuration of a second embodiment according to the invention. In this example, the M-sequence generation circuit 11 of the first embodiment is replaced by a counter 10 driven by an input clock.
3 and the output of counter 3 as the address confirmation signal R O
The configuration is such that the pseudo random number generation circuit 112 consisting of M 104 is replaced.

In this example, the difference in the probability of appearance of "0" and "l" in the desired pseudo-random number signals output from the E-OR gates 13α to 13g is po pi = 2'162. here.

ε1. ε2 is a value indicating the probability deviation 9 of 'O' and '1' in the pseudo-random number data stored in ROM4 and ROM 104, respectively.As mentioned in the explanation of the first embodiment, ROM4 , if the pseudorandom number data stored in the ROM 104 is used as randomness quotient data based on a method of utilizing physical phenomena, '1<<1, '2.
<< 1, so the above-mentioned difference in appearance probabilities 2g182 is smaller (becomes smaller).Also, if the data to be stored in ROM4 and ROM104 are selected to be mutually independent, the same explanation of the operation as in the first embodiment can be made. For this reason, from the E-OR gates 13α to 13e, the values O to 31 in decimal value occur with almost equal probability, and can be considered to occur independently of each other in a time series at °C.Period. is the least common multiple of the period fL1 of the counter 3 and the period n2 of the counter 103, and if a rL1≠n2, the same effect as in the first embodiment can be expected.

〔Effect of the invention〕

According to the present invention, pseudorandom numbers with high randomness (long period) can be generated with a simple circuit configuration and at high speed, which is effective in improving performance.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of the first embodiment of the present invention, and FIG. 2 is a diagram of the second embodiment.
FIG. 3 is a block diagram of a prior art pseudo-random number generation circuit. 1...shift register, 2...E-OR goo). 3...Counter, 4...ROM. 11...M series generation circuit. 12... Pseudo-random number generation circuit. 13α~13g---E-OR gate. , 11°103...Counter, 104...ROM. 112...pseudo random number generation circuit. , 12

Claims (1)

[Claims] 1. A first pseudo-random number circuit that generates pseudo-random numbers with a period of n, a second pseudo-random number generator that generates pseudo-random numbers with a period of n (n≠n), and an equation that receives the two systems of pseudo-random numbers as input. In a pseudo-random number generation circuit consisting of an E-OR (E-OR) gate or an Ex-NOR (E-NOR) gate, the second pseudo-random number circuit is connected to a memory circuit in which the output random number itself is stored in advance as data, and from the memory circuit. A pseudo-random number generation circuit comprising: a control circuit for controlling data reading;