JPH0282135U

JPH0282135U -

Info

Publication number: JPH0282135U
Application number: JP16131888U
Authority: JP
Priority date: 1988-12-14
Filing date: 1988-12-14
Publication date: 1990-06-25

Description

[Brief explanation of drawings]

第１図はこの考案に係るタイミング化シリアル
出力回路の実施例を示したブロツク図である。第
２図は従来例のタイミング化シリアル出力回路の
ブロツク図である。主な符号の説明、１ａ〜１ｎ：入力端子、２ａ
〜２ｎ：Ａ／Ｄ変換回路、３：メモリ切換え用第
１のバツフア回路、４：メモリ切換え用第２のバ
ツフア回路、５：第１のメモリ回路、６：第２の
メモリ回路、７：タイミング信号／アドレスコン
トロール回路、８，２２：セレクタ回路、１２：
メモリ切換えＡ信号、１３：メモリ切換えＢ信号
、１４：データ書き込み許可信号、１５：データ
出力許可信号、１６，２３：データセレクト信号
、２０ａ〜２０ｎ：ラツチ回路、２１ａ〜２１ｎ
：パラレル／シリアル変換回路、２４：データ並
び換え回路、２５：タイミング信号、２６：タイ
ミング信号回路。 FIG. 1 is a block diagram showing an embodiment of a timing serial output circuit according to the invention. FIG. 2 is a block diagram of a conventional timing serial output circuit. Explanation of main symbols, 1a to 1n: input terminal, 2a
~2n: A/D conversion circuit, 3: first buffer circuit for memory switching, 4: second buffer circuit for memory switching, 5: first memory circuit, 6: second memory circuit, 7: timing Signal/address control circuit, 8, 22: Selector circuit, 12:
Memory switching A signal, 13: Memory switching B signal, 14: Data write permission signal, 15: Data output permission signal, 16, 23: Data select signal, 20a to 20n: Latch circuit, 21a to 21n
: parallel/serial conversion circuit, 24: data sorting circuit, 25: timing signal, 26: timing signal circuit.

Claims

[Claims for Utility Model Registration] A timing serial output circuit that serializes data converted into digital signals by a plurality of A/D conversion circuits in accordance with a timing signal, rearranges the data, and outputs the same, An A/D conversion circuit, a memory circuit that stores output data of this A/D conversion circuit via a buffer circuit, and a timing signal circuit that controls data of this memory circuit with a timing signal.
A timing serial output circuit comprising: a selector circuit that selects data in the memory circuit according to a data select signal of a timing signal circuit.