JPH0239725A - Information quantity control circuit - Google Patents

Abstract

PURPOSE:To suppress a prepared information quantity by compressing a signal level besides the threshold of the assignment of respective bits. CONSTITUTION:By a blocking circuit 3, an input digital video signal is converted to a continuous signal for a two-dimensional block which is the unit of the encoding, supplied to a maximum value detecting circuit 4, a minimum value detecting circuit 5 and a delaying circuit 6 and a dynamic range DR is obtained from a subtracting circuit 7. At a threshold determining circuit 9, a compression coefficient alpha and thresholds T1, T2, T3 and T4 are obtained so that the rate of the transmission data can be constant. Since a video signal has a two-dimensional correlation and a three-dimensional correlation, the data are quantized by the number of the bits of a 0 bit, 1 bit, 2 bits, 3 bits or 4 bits smaller than 8 bits, and even then, the quantization distortion is not eminent.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to, for example, when recording a variable-length encoded digital video signal onto a magnetic tape, the transmission rate of recorded data is made to correspond to the transmission path. The present invention relates to an information amount control circuit applied to control the amount of information to a predetermined value.

[Summary of the invention]

The invention sets multiple thresholds for data,
It has a processing circuit that processes signals related to each piece of data according to the threshold range to which the data belongs, and sets control data consisting of the threshold value and a coefficient α for compressing the data. By doing so, the amount of transmitted data is kept below the target value.

In order to set the control data to an optimal value, a threshold table consisting of a plurality of control data is stored, for example, in a ROM. Control data is sequentially generated from this threshold table, and the amount of data is calculated based on each control data. In this case, the frequency of occurrence of each piece of data within a predetermined period is aggregated, the amount of data within the predetermined period is calculated based on the aggregation result and the control data, and the calculated data amount is compared with a target value. Ru. Control data (ie, a plurality of threshold values and a coefficient α (α≦1)) for a signal related to the data is determined according to this comparison output.

In other words, the threshold value from the threshold generation circuit is (1/α)
The amount of data is calculated based on the multiple thresholds multiplied by (1/α) and the above-mentioned aggregation results, this calculation output is compared with the target value, and the threshold is set according to this comparison output. A value generation circuit is controlled to determine control data, and signals related to compressed data are processed based on the determined control data.When the amount of data to be transmitted is large, the image quality is The amount of data can be compressed without causing deterioration.

[Conventional technology]

The applicant of this application has determined a dynamic range defined by the maximum and minimum values of a plurality of pixels included in a two-dimensional block, as described in Japanese Patent Application No. 59-266407, and A high-efficiency encoding device that performs adaptive encoding is proposed. Furthermore, as described in Japanese Patent Application No. 60-232789, a high-efficiency encoding device performs encoding adapted to a dynamic range with respect to a three-dimensional block formed from pixels in areas included in each of a plurality of frames. is proposed. Furthermore, as described in Japanese Patent Application No. 60-268817, there is a variable length encoding method in which the number of bits changes depending on the dynamic range so that the maximum distortion caused when quantization is constant. Proposed.

High-efficiency code (AD) adapted to the above-mentioned dynamic range
RC) is suitable for application to digital VTRs because it can significantly compress the amount of data to be transmitted. In particular, variable-length ADRC can achieve a high compression rate.However, variable-length ADRC is not suitable for digital VTRs that record a predetermined amount of data as one track, since the amount of transmitted data varies depending on the content of the image. When using such a fixed rate transmission path, buffering processing is required to control the amount of recorded information.

Conventionally, the output data of a variable length encoding circuit is supplied to an information restriction circuit, the output data of the information restriction circuit is supplied to a buffer memory, and the amount of transmitted data is monitored in the buffer memory. A control signal for controlling the transmission data so as not to exceed the transmission rate is fed back from the buffer memory to the information amount limiting circuit, thereby controlling the amount of generated information.

In conventional buffering, if the sensitivity to the amount of feedback is increased too much, it will oscillate around the target value, and if the sensitivity is decreased too much, convergence will take a long time. When convergence takes time, it is necessary to increase the buffer memory capacity.

As described above, the conventional buffering process has the drawback that it requires a considerable amount of know-how in practical use.

In order to solve this problem, the applicant of the present application filed the patent application No. 61
As described in Japanese Patent No. 257,586, a feedforward type buffering device using a cumulative type frequency distribution table is proposed.

This buffering device changes the frequency distribution of the dynamic range within a block to an integrated type, and sets multiple thresholds for the dynamic range within the block in order to specify the number of bits to be allocated to the frequency distribution. The threshold value is varied so that the amount of information generated as a result of the application is less than or equal to the target value.

According to this buffering device, the convergence time of buffering can be shortened by quickly and easily calculating the amount of generated information.

[Problem to be solved by the invention]

When changing the threshold so that the amount of generated information is below the target value, it is difficult to do so based on experience, and if the threshold is set too large, there is a problem in which deterioration of the restored image such as block distortion becomes visible. . In other words, there is a threshold limit at which deterioration is recognized for each number of allocated bits, for example 0.
When the bit allocation threshold reaches or exceeds the level where
Block distortion becomes visible. If the threshold value is made too large in order to suppress the amount of generated information, deterioration such as block distortion will become noticeable.

Therefore, an object of the present invention is to provide an information amount control circuit that can suppress the amount of generated information to a target value or less by compressing the signal level in addition to the threshold value of each bit allocation.

Another object of the present invention is to prepare control data, which is a combination of a threshold value and a compression coefficient, in advance, and use simple control and high-speed processing to suppress the amount of generated information to below a target value. The object of the present invention is to provide a quantity control circuit.

[Means to solve the problem]

In this invention, a frequency aggregation circuit that aggregates the frequency of occurrence of each flight of data within a predetermined period, a compression circuit that multiplies a signal related to the data by a coefficient α (α≦1), and a A threshold generation circuit that generates control data consisting of a plurality of threshold values and a coefficient α, and a threshold value and frequency aggregation means that multiply the plurality of threshold values from the threshold generation circuit by (1/α). an arithmetic circuit that calculates the amount of data based on the output of the arithmetic circuit, and a setting circuit that compares the output of the arithmetic circuit with a target value and sets control data from the threshold generation circuit so that the amount of data does not exceed the target value. and a processing circuit that processes signals related to data from the compression circuit based on control data from the configuration circuit.

[Effect]

For example, the sum of frequencies is calculated for each range divided by multiple thresholds of the dynamic range, and this sum of frequencies is multiplied by a weight (number of bits).
The generated information amount for each range is calculated, and the generated information amounts for the plurality of ranges are added to calculate the total generated information amount. Therefore, a series of calculations is required each time the threshold value is changed. However, if an integration table of the frequency of occurrence is created, even if the threshold value is changed, the frequency corresponding to the threshold value can be immediately known, and by multiplying each frequency by the number of bits, the amount of information on the occurrence can be immediately calculated. You can know.

Therefore, the convergence time of buffering processing can be shortened,
Also, the hardware can be simplified.

In this invention, the amount of generated information is controlled by controlling the amount of generated information based on a threshold value and compressing the signal level. Control data in which the compression coefficient α and the threshold value are combined is stored in a threshold generation circuit, such as a ROM. The amount of generated information is calculated using the control data read from the ROM, and the amount of generated information is compared with a target value. Based on this comparison output, optimal control data is determined. In other words, the threshold value in the control data is (1/α
) is multiplied by (1/α), the amount of generated information is calculated using the threshold value multiplied by (1/α) and the frequency distribution table, the amount of generated information is compared with the target value, and the control data is calculated according to the comparison output. settings are made. The optimal control data is a value that causes the least deterioration of the restored image within a range that allows the amount of generated information to be less than or equal to the target value. This control data is determined every predetermined period.

[Embodiment] A digital VTR to which the present invention is applied will be described in detail with reference to the drawings. This explanation is made according to the following items.

a. Configuration of the transmitting side and receiving side, variable length quantization and buffering c. Threshold determining circuit d. Modified example In the case of a digital VTR, the transmitting side corresponds to the recording side, and the receiving side corresponds to the reproducing side. handle.

a. Configuration of transmitting side and receiving side In FIG. 1, an analog video signal is supplied to the input terminal indicated by 1, this video signal is supplied to the A/D converter 2, and from the A/D converter 2, for example, 1 is supplied. A digital video signal is obtained in which the samples are quantized to 8 bits. A digital video signal is supplied to a blocking circuit 3.

The blocking circuit 3 converts the input digital video signal into continuous signals for each two-dimensional block, which is a unit of encoding. The blocking circuit 3 subdivides one frame of screen, for example (488 lines x 720 pixels), into a large number of blocks. (2) A block has a size of (4 lines x 4 pixels), for example, as shown in FIG.

A blocking circuit 3 generates a digital video signal converted into a block order.

The output signal of the blocking circuit 3 is supplied to a maximum value detection circuit 4 that detects the maximum value MAX for each block, a minimum value detection circuit 5 that detects the minimum value MIN for each block, and a delay circuit 6. The detected maximum value MAX and minimum value MIN are supplied to the subtraction circuit 7, and the maximum value (fiMAX and minimum value MI
A dynamic range DR, which is the difference of N, is obtained from the subtraction circuit 7. The delay circuit 6 has a maximum value MAX and a minimum value MI
The time required to detect N and the compression coefficient α described later
Determine the time to delay the data.

Video data from delay circuit 6 is supplied to compression circuit 14 . This compression circuit 14 is supplied with a compression coefficient α from a threshold determination circuit 9, which will be described later, and an output signal multiplied by the compression coefficient α (≦1) is obtained from the compression circuit 14. The compression circuit 14 is constituted by, for example, a ROM to which human data and compression coefficient α are supplied as addresses.

The compression coefficient α from the threshold value determination circuit 9 is supplied to the offset value generation circuit 16. This offset value generation circuit 1
From 6 onwards, an offset value corresponding to the compression coefficient α is generated. This offset value generation circuit 16 is constituted by a ROM to which the compression coefficient α is supplied as an address.

The output signal of the compression circuit 14 and the output signal of the offset value generation circuit 16 are supplied to the addition circuit 15, and the addition circuit 15 generates data to which an offset value has been added. The offset value can be added not only to the output side of the compression circuit 14 but also to the output side of the minimum value detection circuit 18, which will be described later.

A maximum value detection circuit 17 for detecting the maximum value MAX of the output signal of the adder circuit 15 for each block. The signal is supplied to a minimum value detection circuit 18 and a delay circuit 19 that detect the minimum value MIN for each block. The detected maximum value MAX and minimum value MIN are supplied to the subtraction circuit 20, and the maximum value MAX and minimum value MI
A dynamic range DR, which is the difference of N, is obtained from the subtraction circuit 20. The delay circuit 19 delays the output data of the compression circuit 14 for the time necessary to detect the maximum value MAX and the minimum value MIN.

The minimum value MIN is subtracted from the output signal of the delay circuit 19 by the circuit 2.
1, and the subtraction circuit 21 obtains data PDI after the minimum value has been removed. Data P after minimum value removal
CI is supplied to the encoding circuit 22. The encoding circuit 22 also receives a threshold set T from the threshold determining circuit 9.
i (T1~' means 4) and the dynamic range DR from the subtraction circuit 20 are supplied.

The encoding circuit 22 performs variable length ADRC encoding to quantize the data PD[. That is, the encoding circuit 22 generates a code signal DT corresponding to the value obtained by dividing the pixel data PDI from which the minimum value MIN shared by the pixel data in the block is removed by the quantization width Δi.

Since the video signal has two-dimensional correlation and three-dimensional correlation, the dynamic range DR within the block is small compared to the original data value (ie, less than 8 bits, 1 bit, Quantization distortion is not noticeable even when data is quantized with a bit number of 2 bits, 3 bits, or 4 bits.The encoding circuit 22 generates a code signal DT from the pixel data PDI, dynamic range DR, and threshold set Ti. It consists of a ROM and a ROM.

With digital VTRs, the transmission rate of recorded data is constant, so if the amount of transmitted data is not limited, some data may not be recorded, or the quality of the reproduced image will deteriorate due to unnecessarily high compression rates. .

I do things. Therefore, buffering processing is performed to perform optimal variable length encoding.

The dynamic range DR for each block detected by the subtraction circuit 7 is supplied to a frequency distribution generation circuit 8, and an integrated frequency distribution table is formed. This frequency distribution table is supplied to the threshold determining circuit 9 through a terminal 10. The threshold value determination circuit 9 is supplied with a reset signal of one frame period and a target value of the amount of generated information from terminals 11 and 12, for example. The threshold value determination circuit 9 sets the compression coefficient α and the threshold values Tl, T'2,
'1'3. T4 is required. Compression coefficient α is output terminal 1
3, and the threshold value cellar) Ti is output from terminal 25.

Threshold cell 1-Tj, dynamic range DR, minimum value MIN, and encoding circuit 22 from the threshold determining circuit 9
The code signal DT from is supplied to the framing circuit 23. The framing circuit 23 includes a code signal DT as variable length data and an additional code Ti as fixed length data.
, DR, and MIN are encoded for error correction and a synchronization signal is added. Output terminal 2 of framing circuit 23
4, the transmission data is obtained. One threshold set Ti is transmitted for one frame of data, DR and MEN data are transmitted for each block, and a code signal DT is transmitted for each pixel.

The received data is supplied to an input terminal indicated by 31 in FIG.
, minimum value MIN. Threshold set Ti1 dynamic range D from frame decomposition circuit 32
R, code signal DT is supplied to the decoding circuit 33.

The decoding circuit 33 is the encoding circuit 2 of the ADRC encoder.
0, the code signal DT is converted to a restored level. This decoding circuit 33 is composed of, for example, a ROM. The restored level from the decoding circuit 33 is supplied to the adding circuit 34, and the minimum value MIN passed through the delay circuit 35 is added to the restored level. The restored data from the adder circuit 34 is supplied to the block decomposition circuit 36. Block decomposition circuit 3
Output data in the same order as the television signal is obtained at the output terminal 6. This restored signal is sent to the D/A converter 3.
7, and the analog video signal reproduced at the output terminal 38 is taken out.

b. Variable length quantization and buffering FIG. 5 explains variable length quantization performed in the encoding circuit 22. In the following description, Tl,
T2. T3. T'4 is a threshold value for determining the number of allocated bits, and is for the dynamic range DR. These threshold values are (T4<T3<T2<Tl
).

The dynamic range DR (=MAX-MIN) is (DR
= T'4-1), as shown in FIG. 5A, only the maximum value MAX and minimum value MIN are transmitted, and on the receiving side,
A level LO between the two is set as a restoration level. Therefore, as shown in FIG. 5A, the dynamic range DR is (
At the time of T4-1), the quantization width becomes ΔO. If the dynamic range DR is (0≦DR≦T4-1),
The number of allocated bits is O bits.

FIG. 5B shows a case where the dynamic range DR is (T3-1). Dynamic range DR is (T4≦DR≦
73-1), the number of allocated bits is 1 bit. Therefore, the detected dynamic range DR is divided into two level ranges, and the level range to which the pixel data PD■ after removing the minimum value of the block belongs is determined using the quantization width Δ1, and the level range corresponding to the level range is determined by using the quantization width Δ1. ° or ““
One code signal of 1'' is assigned, and the restoration level is set to LO or Ll.

In the variable length encoding shown in FIG. 5, the larger the dynamic range, the smaller the quantization width Δi (ΔO<Δ1
Non-linear quantization is performed, which is increased as Δ3 Δ4). Non-direct fit reduces the maximum distortion for blocks with a small dynamic range where quantization distortion is easily noticeable, and conversely increases the maximum distortion for blocks with a large dynamic range, resulting in a higher compression ratio. .

When the dynamic range DR is (T2-1), as shown in FIG. 5C, the detected dynamic range D
R is divided into 4 level ranges, and for each level range, 2 pips 1-(00)(01)(10)(11)
are assigned, and the center level of each level range is taken as the restoration level LO, Ll, L2°L3. Therefore, the level range to which the data PDT belongs is determined using the quantization width Δ2. Dynamic range DR is (T3≦DR≦T2
-1), the number of allocated bits is 2 bits.

Furthermore, when the dynamic range DR is (T 1-1 ), the detected dynamic range DR is divided into eight level ranges, and 3 bits are set for each level range, as shown in Figure 5. (000) (001)
... (111) are assigned, and the center level of each level range is set as the restoration level LO, Ll...L7. Therefore, the quantization width is Δ3. Dynamic range D
When R is (T2≦DR≦Tl-1), the number of allocated bits is 3 bits.

Furthermore, when the dynamic range is maximum 255,
As shown in Figure 5, the detected dynamic range DR is divided into 16 level ranges, and for each level range, 4 bits (0000) (0001)
... (1111) are assigned, and the center level of each level range is set as the restoration level LO, LL...Li2. Therefore, the quantization width is Δ4. When the dynamic range DR is (TI≦DR<256), the number of allocated bits is 4 bits.

FIG. 6 is an example of a frequency distribution with the horizontal axis representing the dynamic range DR in the range (0 to 255) and the vertical axis representing the frequency of occurrence. XI, Xt, X3. X4. As described above, each of XS represents the number of blocks included in the five ranges of the dynamic range DR divided by the threshold values T1 to T4. Since 0 bits are assigned to blocks having a dynamic range DR of (T4-1) or less, the number of blocks X does not contribute to the amount of generated information. Therefore, the amount of generated information is determined by 4X+ +3xt +2X, +X4. This amount of generated information is compared with a target value, and when the amount of generated information exceeds the target value, a larger set of threshold values is applied and the amount of generated information is calculated in the same manner.

To perform the above equation, it is necessary to calculate the sum of the frequency distributions in each range for each set of set threshold values, multiply this sum by the number of allocated bits, and add the sum. However, if the above process is performed every time the threshold set is changed, a problem arises in that it takes time to find the optimal threshold set.

In this embodiment, in the frequency distribution generating circuit 8, the sixth
The frequency distribution shown in the figure is obtained, and then the frequency distribution shown in FIG. 6 is converted into the cumulative type frequency distribution shown in FIG. 7. By converting to a cumulative frequency distribution, different sets of thresholds and the corresponding amount of generated information can be calculated faster.
Therefore, the convergence time until an optimal set of threshold values is obtained is shortened.

As understood from Fig. 7, the dynamic range DR
starts from the maximum frequency of occurrence, and the frequencies of occurrence of smaller dynamic ranges DR are successively integrated to obtain an integrated frequency distribution graph.

Therefore, the cumulative frequency up to the threshold Tl is x, the cumulative frequency up to the threshold T2 is (x++xz), and the cumulative frequency up to the threshold T3 is (x, +xt +X,),
The cumulative frequency up to threshold T4 is (Xl + Xz + X
s 1Xs ).

The amount of generated information for the thresholds T1 to T4 is 4 (x,
-Q) +3 ((X, 10X2) -XI)+
2 ((x+ +Xz +X3) (XI +x
t )) + 1 ((XI +Xt +x, +xa
) (x+ +xt 1Xs) =4 XI”
It is found as 3Xt +2X3 + I Xa. If you first create the cumulative frequency distribution graph (cumulative frequency distribution table) shown in Figure 7, when you update the threshold set,
The amount of generated information can be immediately determined by the sum of the four numbers.

In this embodiment, a compression circuit 14 is provided, and the input level is multiplied by α. This means that the maximum value MAX and the minimum value MIN
will also be compressed, and the dynamic range DR will also be
In Fig. 6, the dynamic range D
This means that the distribution of R moves toward 0. Therefore, by decreasing α, the amount of generated information can be controlled to be smaller.

Since the entire signal level is multiplied by α, when (α<1),
The brightness of the restored image will decrease.

Therefore, when the moving part of the image increases and the information meter increases, the problem arises that the brightness suddenly decreases.

In this embodiment, since an offset value corresponding to the compression coefficient α is added to the data, the overall signal level increases as shown in FIG. Therefore, the reduction in brightness of the restored image is suppressed, and the above-mentioned problem is prevented from occurring. Also,
The offset value is set to a larger value as the value of α is smaller, and thus the compression ratio is larger, and the problem of lowering the overall brightness of the image can be effectively suppressed.

c, L/threshold value determination circuit FIG. 4 shows an example of the threshold value determination circuit 9.

In FIG. 4, reference numeral 41 indicates a ROM in which control data (a table of threshold values) consisting of a threshold set Tj and a compression coefficient α is stored. The ROM 41 is supplied with an address code Pi from an address counter 42 . The address counter 42 is supplied with a reset signal of one frame period from the terminal 11.

An example of the threshold table stored in the ROM 41 is shown in FIG. As shown in FIG. 10, 32 types of control data are prepared, each corresponding to (0 to 31) of the address code P i. The threshold table is configured such that the amount of generated information decreases in order from the one with the largest amount of generated information (Pi-0), and the amount of generated information is the smallest in the control data when (Pi=31). ing. This threshold table can be created by simulation using a computer. Furthermore, the width of change in the compression coefficient α is made small, thereby preventing deterioration of the restored image due to sudden changes in α.

Among the control data read from the threshold table in the ROM 41, the coefficient α is taken out to the output terminal 13, and the threshold set T1 is taken out to the output terminal 25. Further, the threshold set Ti is supplied to the information amount calculation circuit 44 via the calculation circuit 43 which multiplies it by (1/α). The arithmetic circuit 43 is supplied with the coefficient α included in the same control data from the ROM 41 .

The information amount calculation circuit 44 is supplied with an integral type frequency distribution table from the terminal (2)0. As described above, the information amount calculation circuit 44 determines the amount of generated information corresponding to the predetermined threshold set multiplied by (1/α) from the calculation circuit 43. The amount of information generated when input data is compressed by α times can be obtained by multiplying the threshold value by (1/α). The amount of generated information is supplied to a comparison circuit 45. The comparison circuit 45 includes
A target value from terminal 12 is supplied.

The output signal of the comparison circuit 45 is supplied as a clock to the address counter 42, and the address counter 42 is incremented by the output signal of the comparison circuit 45 that is generated when the generated information amount is larger than the target value. In the table shown in FIG. 10, the amount of generated information is sequentially reduced, and when the amount of generated information becomes less than the target value, incrementing is stopped.

The control data at this time is employed as the optimum threshold value t-Ti and compression coefficient α.

As described above, the control data generated from the ROM 41 is determined. The coefficient α in the control data is supplied from the output terminal 13 to the compression circuit 14 and the offset value generation circuit 16. The offset value generation circuit 16 generates an offset value corresponding to the coefficient α, and is added to the output signal of the compression circuit 14. The offset value is level compressed to compensate for the overall reduction in brightness. Further, a threshold set Ti in the control data is supplied from the output terminal 25 to the encoding circuit 22, and ADRC encoding is performed in the encoding circuit 22 using this threshold set Ti.

As described above, when the amount of generated information is large, the input level is compressed and the threshold value is increased, so that the amount of generated information is controlled to be below the target value. ADRC quantization is performed on input data compressed by this compression coefficient α using a threshold set included in the same control data. Therefore, compared to simply reducing the amount of generated information by controlling the threshold, visual deterioration such as block distortion and edge business is reduced in the restored image.

Furthermore, since the compression circuit 14 performs level compression, the overall signal level decreases, but since an offset value corresponding to the compression ratio is added, the decrease in brightness is corrected in the restored image.

In addition to the code signal DT, the dynamic range DR,
Minimum value MIN, threshold value cent Ti, and redundant code of error correction code are transmitted, but since these data have a fixed length, when checking the rate of transmitted data, off-seller I is added to the target value. You can ignore it by having it.

d. Modification This invention can also be applied to ADRC of three-dimensional blocks. For example, when a three-dimensional block is composed of two two-dimensional regions belonging to two frames, the number of pixels in one block is doubled. Also, ADRC of 3D block
In order to increase the compression rate, the presence or absence of movement is determined between two two-dimensional areas, and if there is movement, the pixel data of the two two-dimensional areas, that is, the code of all pixel data in the block, is determined. When there is no movement, the pixel data of one two-dimensional area is encoded. Therefore, the amount of generated information is (1:2) between the still part and the moving image part.

Furthermore, the present invention can also be applied to cases in which the maximum frame difference information for each block is taken into account in the buffering of the three-dimensional blocks described above, and when ADRC is performed after subsampling to increase the compression rate. can also be used.

Furthermore, instead of outputting the threshold set Ti, the address code Pi may be output.

Furthermore, the present invention is not limited to buffering used in conjunction with a high-efficiency encoding method, but can be widely used for the purpose of keeping the amount of transmitted data constant.

FIG. 10 is a route map of an example of a table regarding control data.

〔Effect of the invention〕

In this invention, when the amount of generated information increases, the level of input data is compressed before processing such as encoding.
It is possible to prevent deterioration such as block distortion from becoming noticeable in restored image quality. Further, in the present invention, since the compression coefficient α and the threshold set Ti are determined at the same time, control becomes simple and high-speed processing becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the transmitting side of an embodiment of the present invention, FIG. 2 is a route diagram for explaining the blocks, and FIG.
The figure is a block diagram of the receiving side, Figure 4 is a block diagram of an example of a threshold determination circuit, Figure 5 is a route diagram for explaining variable length quantization, and Figures 6 and 7 are frequency distribution tables. FIG. 8 is a route map for explaining level compression, FIG. 9 is a route map for explaining adding offset values,
Explanation of main symbols in the drawing 1: Analog video signal input terminal, 3-niblock circuit, 4.17: Maximum value detection circuit, 5.18: Minimum value detection circuit, 7.20, 21: Subtraction circuit, 22: Encoding circuit; 9: Threshold determining circuit; 41: ROM in which a threshold table is stored. 42 Near address counter, 43: (1/α) multiplication circuit, 44: Information amount calculation circuit, 45: Comparison circuit. Agent Patent Attorney Tadashi Sugiura Number of knowledge T4 T2 T1 Anti-commitment and division graph 槓廓形库显数 10,000 Figure 1 level / I reduction Figure 8 Figure 9 Figure 10 vli Small 4-direction table -1 row

Claims (1)

[Scope of Claims] Frequency aggregation means for aggregating the frequency of occurrence of each value of data within a predetermined period; compression means for multiplying a signal related to the data by a coefficient α (α≦1); Multiple thresholds for each value and the above coefficient α
threshold generation means for generating control data consisting of (1) the plurality of thresholds from the threshold generation means;
/α) A calculation means that calculates the amount of data based on the multiplied threshold value and the output of the frequency aggregation means, and a calculation means that compares the output of the calculation means with a target value to ensure that the amount of data does not exceed the target value. and a processing means for processing a signal related to the data from the compression means based on the control data from the setting means. Characteristic information control circuit.