JP2730035B2 - Information amount control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a case where a variable-length coded digital video signal is recorded on a magnetic tape and a transmission rate of data to be recorded corresponds to a transmission path. The present invention relates to an information amount control circuit applied to control to a predetermined value.

[Conventional technology]

The present applicant obtains a dynamic range defined by a maximum value and a minimum value of a plurality of pixels included in a two-dimensional block as described in Japanese Patent Application No. 59-266407, and this dynamic range A high-efficiency coding apparatus that performs adaptive coding has been proposed. In addition, Japanese Patent Application No. 60-
As described in the specification of Japanese Patent No. 232789, there has been proposed a high-efficiency coding apparatus that performs coding suitable for a dynamic range with respect to a three-dimensional block formed from pixels in regions included in a plurality of frames. Furthermore, Japanese Patent Application No. 60-
As described in the specification of Japanese Patent No. 268817, there has been proposed a variable length coding method in which the number of bits changes according to a dynamic range in which the maximum distortion generated when performing quantization is constant.

High-efficiency code (AD
RC) is suitable for application to a digital VTR because it can significantly reduce the amount of data to be transmitted. Especially,
The variable length ADRC can increase the compression ratio. However, in the variable-length ADRC, the amount of transmission data varies depending on the content of an image. Therefore, when using a fixed-rate transmission path such as a digital VTR that records a predetermined amount of data as one track, buffering processing is not performed. is necessary.

Conventionally, output data of a variable length encoding circuit is supplied to a control limiting circuit, output data of an information limiting circuit is supplied to a buffer memory, and in the buffer memory, a data amount of transmission data is monitored, and A control signal for controlling the transmission rate so as not to exceed the transmission data is fed back from the buffer memory to the information amount limiting circuit, and the generated information amount is controlled.

In the conventional buffering, if the sensitivity to the feedback amount is too high, oscillation occurs near the target value, and if the sensitivity is too low, convergence takes time. When it takes time to converge, it is necessary to increase the capacity of the buffer memory. As described above, the conventional buffering processing has a drawback that requires considerable know-how in practical use.

In order to solve this problem, the applicant of the present application filed Japanese Patent Application No.
As described in -257586, there is proposed a feed-forward type buffering device which uses an integrated frequency distribution table.

This buffering device changes the frequency distribution of the dynamic range in the block to an integrated type, applies a plurality of thresholds to the frequency distribution to regulate the number of allocated bits, and as a result, The threshold value is varied so that the amount of generated information becomes equal to or less than the target value.

According to this buffering device, the convergence time of buffering can be reduced by quickly and easily calculating the amount of generated information.

[Problems to be solved by the invention]

When moving the threshold value so that the amount of generated information is equal to or less than the target value, it is empirical and difficult to move the threshold value, and if the threshold value is too large, there is a problem that deterioration of the restored image such as block distortion is seen. . That is, there is a limit at which deterioration is recognized for each threshold value. For example, when the threshold value of 0-bit allocation exceeds a certain level, block distortion becomes visible. If the threshold is increased too much to suppress the amount of generated information, deterioration such as block distortion is recognized.

Therefore, an object of the present invention is to note that each threshold has a limit that cannot be increased any more, and that the amount of generated information can be suppressed to a target value or less by using a threshold value up to an allowable limit. Accordingly, it is an object of the present invention to provide an information amount control device capable of achieving a high quality of restored image.

[Means for solving the problem]

The present invention constitutes a block consisting of regions belonging to the same field or a plurality of temporally continuous fields of a digital image signal, performs variable length coding for each of a plurality of pixel data in the block, and generates information generated by the coding. An information amount control circuit for controlling an amount, comprising: a frequency counting circuit for counting the number of occurrences of each value of data within a predetermined period; and a plurality of threshold value sets each including a plurality of threshold values. A threshold setting circuit for setting a set of thresholds for each value; an arithmetic circuit for calculating the amount of generated information based on the set threshold and the output of the frequency counting circuit; The output is compared with the target value, and the threshold for minimizing the quantization distortion in a range where the amount of generated information does not exceed the target value during a predetermined period when the set of thresholds is sequentially changed according to the comparison output. To determine a set of values,
A control circuit that controls the threshold setting circuit; a quantization circuit that quantizes a plurality of data in the block by a quantization bit number based on the determined set of thresholds; And a limit threshold setting circuit for providing a threshold value that minimizes the amount of generated information as a limit threshold value. An information amount control circuit characterized in that when the value exceeds the threshold value, a limit threshold value is given to the quantization circuit and the signal level input to the quantization circuit is compressed.

[Action]

When calculating the amount of generated information, a total sum of frequencies is obtained for each of data divided by a plurality of threshold values, for example, a dynamic range, and the total sum of the frequencies is weighted (number of bits).
Is multiplied to calculate the generated information amount, and the generated information amounts in the plurality of ranges are added. Therefore, every time the threshold is changed, a series of calculations is required. However, if an occurrence frequency accumulation table is formed, even if the threshold value is changed, the frequency value corresponding to the threshold value is immediately known, and the generated information amount is immediately obtained by multiplying each frequency value by the number of bits. You can know. Therefore, the convergence time of the buffering process can be shortened, and the hardware can be simplified.

According to the present invention, a limit threshold value (limit value) at which deterioration of a restored image is recognized is set. When the amount of generated information can be reduced to a target value or less with a threshold value smaller than the limit value, the level of input data is reduced. Do not compress. However, at the limit value, when the amount of generated information exceeds the target value, the amount of generated information is reduced by compressing the input level while keeping the limit value fixed. Therefore, the threshold value does not become smaller than the limit value, and deterioration of the restored image is prevented. That is, by compressing the input level by α (α <1), the frequency distribution of the dynamic range can be made closer to 0 by compression, and the amount of generated information can be reduced without changing the threshold value to a small value. Can be reduced. This compression coefficient α is determined at predetermined intervals.

〔Example〕

A digital VTR to which the present invention is applied will be described in detail with reference to the drawings. This description is made in accordance with the following items.

a. Configuration of the transmitting and receiving sides b. Variable-length quantization and buffering c. Buffering circuit d. Modifications In the case of a digital VTR, the transmitting side corresponds to the recording side, and the receiving side corresponds to the reproducing side. .

a. Configuration of the transmitting side and the receiving side In FIG. 1, an analog video signal is supplied to an input terminal indicated by 1, and this video signal is supplied to the A / D converter 2, and the A / D converter 2 outputs, for example, 1 A digital video signal in which the samples are quantized to 8 bits is obtained. The digital video signal is supplied to the blocking circuit 3. The blocking circuit 3 converts the input digital video signal into a continuous signal for each two-dimensional block which is a unit of encoding. In the blocking circuit 3, for example, (488 lines × 7
A screen of one frame (20 pixels) is subdivided into many blocks. One block is, for example, as shown in FIG.
(4 lines × 4 pixels). From the blocking circuit 3, a digital video signal converted in the order of blocks is generated.

The output signal of the blocking circuit 3 is supplied to a maximum value detection circuit 4 for detecting the maximum value MAX for each block, a maximum value detection circuit 5 for detecting the minimum value MIN for each block, and a delay circuit 6. The detected maximum value MAX and minimum value MIN are subtracted by the subtraction circuit 7.
And the dynamic range DR, which is the difference between the maximum value MAX and the minimum value MIN, is obtained from the subtraction circuit 7. Delay circuit 6
Delays the data by the time required to detect the maximum value MAX and the minimum value MIN and the time required to determine the compression coefficient α.

The video data from the delay circuit 6 is supplied to the compression circuit 14. The compression circuit 14 is supplied with an address code Pi from a buffering circuit 9 to be described later.
An output signal multiplied by a compression coefficient α (≦ 1) corresponding to Pi is obtained from the compression circuit 14. If the address code Pi is (P0 ~
In the range of (P15), (α = 1) is set, and the address code P
When i is in the range of (P16 to P31), (α <1) is set. The compression circuit 14 is constituted by, for example, a ROM to which input data and a compression coefficient α are supplied as addresses.

The output signal of the compression circuit 14 is supplied to a maximum value detection circuit 15 for detecting the maximum value MAX for each block, a minimum value detection circuit 16 for detecting the minimum value MIN for each block, and a delay circuit 17. The detected maximum value MAX and minimum value MIN are supplied to the subtraction circuit 18, and a dynamic range DR that is a difference between the maximum value MAX and the minimum value MIN is obtained from the subtraction circuit 18. The delay circuit 17 delays data for a time necessary to detect the maximum value MAX and the minimum value MIN.

The minimum value MIN is subtracted from the output signal of the delay circuit 17 in the subtraction circuit 19, and the subtraction circuit 19 obtains the data PDI from which the minimum value has been removed. The data PDI from which the minimum value has been removed is supplied to the encoding circuit 20. The encoding circuit 20 performs variable-length ADRC encoding for quantizing the data PDI. That is, the encoding circuit
In 20, the minimum value MIN shared by the pixel data in the block
A code signal DT corresponding to a value obtained by dividing the pixel data PDI from which is removed by the quantization width Δi is formed. The encoding circuit 20 has an address code from the buffering circuit 9.
The dynamic range DR from Pi and the subtraction circuit 18 is supplied. The encoding circuit 20 includes a threshold value table for generating a threshold value from the address code Pi.

Since the video signal in the block has a two-dimensional correlation and a three-dimensional correlation, the dynamic range DR is smaller than the value of the original data, and 0 bits, 1 bits, less than 8 bits. Even when quantization is performed with the number of bits of 2, 3, or 4 bits, quantization distortion is not conspicuous. The encoding circuit 20 includes a ROM in which a threshold table is stored, and a ROM that generates a code signal DT from the pixel data PDI, the dynamic range DR, and the above-described threshold.

With a digital VTR, the transmission rate of the recorded data is constant, so if the amount of transmitted data is not limited, some data cannot be recorded or the compression rate will be higher than necessary and the quality of the reproduced image will deteriorate. Or Therefore, a buffering circuit 9 is provided, and the frequency distribution of the dynamic range DR of all the blocks of one screen to be ADRC-coded is examined, and optimal variable-length coding is performed.

The dynamic range DR for each block detected by the subtraction circuit 7 is supplied to the frequency distribution generating circuit 8 to form an integrated frequency distribution table. This frequency distribution table is supplied to the buffering circuit 9 through the terminal 10. The buffering circuit 9 is supplied with, for example, a reset signal in a two-frame cycle and a target value of the generated information amount from the terminals 11 and 12.
In the buffering circuit 9, thresholds T 1, T 2, T 3, and T 4 for obtaining a constant transmission data rate are obtained, and an address code Pi corresponding to these thresholds is output from a terminal 13.

The address code Pi from the buffering circuit 9, the dynamic range DR and the minimum value MIN, and the code signal DT from the encoding circuit 20 are supplied to the framing circuit 21. The framing circuit 21 performs error correction encoding on the code signal DT as variable-length data and the additional codes Pi, DR, and MIN as fixed-length data, and adds a synchronization signal. Transmission data is obtained at the output terminal 22 of the framing circuit 21.
One address code Pi is transmitted in two frames, DR and MIN data are transmitted for each block, and a code signal DT is transmitted for each pixel.

The received data is supplied to an input terminal indicated by reference numeral 31 in FIG. 3, and the address code Pi, dynamic range DR, code signal DT, minimum value
Decomposed into each of MIN. The decoding circuit 33 converts the code signal DT to a restoration level, as opposed to the coding circuit 20 of the ADRC encoder. The decoding circuit 33 is constituted by, for example, a ROM. The restoration level from the decoding circuit 33 is an addition circuit
The minimum value MIN supplied to the delay circuit 35 is supplied to the restoration level, and the restoration data from the addition circuit 34 is supplied to the block decomposition circuit 36. Output data in the same order as the television signal is obtained at the output terminal of the block decomposition circuit 36. The restored signal is supplied to the D / A converter 37, and the analog video signal reproduced at the output terminal 38 is extracted from the D / A converter 37.

b. Variable-Length Quantization and Buffering FIG. 5 illustrates variable-length quantization performed in the encoding circuit 20. T1, T2, T3, and T4 are threshold values that determine the number of allocated bits. is there. These thresholds are
(T4 <T3 <T2 <T1).

When the dynamic range DR (= MAX−MIN) is (DR = T4−
In the case of 1), as shown in FIG. 5A, only the maximum value MAX and the minimum value MIN are transmitted, and on the receiving side, the intermediate level L0 between them is set as the restoration level. Therefore, as shown in FIG. 5A, when the dynamic range DR is (T4-1),
The quantization width becomes Δ0. When the dynamic range DR is (0 ≦
When DR ≦ T4-1), the number of allocated bits is 0.

FIG. 5B shows a case where the dynamic range DR is (T3-1). Dynamic range DR is (T4 ≦ DR ≦ T3-1)
In the case of, the number of allocated bits is one bit. Therefore, the detected dynamic range DR is divided into two level ranges, and the pixel data PDI after removing the minimum value of the block.
Is determined using the quantization width Δ1,
One of the code signals “0” or “1” corresponding to the level range is assigned, and the restoration level is set to L0 or L1.

In the variable length coding shown in FIG. 5, as the dynamic range becomes larger, the quantization width Δi becomes (Δ0 <Δ1 <Δ
Non-linear quantization that is increased to 2 <Δ3 <Δ4) is performed. The non-linear quantization reduces the maximum distortion in a block having a small dynamic range in which quantization distortion is conspicuous, and increases the maximum distortion in a block having a large dynamic range.

When the dynamic range DR is (T2-1), the fifth
As shown in FIG. C, the detected dynamic range DR is divided into four level ranges, and two bits (00) (01) (10) (11) are assigned to each of the level ranges. The level in the middle of the level range is the restoration level L0, L1, L
2, L3. Therefore, the data PD is calculated using the quantization width Δ2.
The level range to which I belongs is required. When the dynamic range DR is (T3 ≦ DR ≦ T2-1), the number of allocated bits is 2 bits.

When the dynamic range DR is (T1-1), as shown in FIG. 5D, the detected dynamic range DR is divided into eight level ranges, and each of the level ranges has 3 bits. (000), (001),... (111) are assigned, and the center level of each level range is set as a restoration level L0, L1,. Therefore, the quantization width becomes Δ3. When the dynamic range DR is (T2 ≦ DR ≦ T1-1), the number of allocated bits is 3 bits.

Furthermore, if the dynamic range is the maximum of 255,
As shown in FIG. 5E, the detected dynamic range
The DR is divided into 16 level ranges, and 4 bits (0000) (0001)... (1111) are assigned to each of the level ranges, and the center level of each level range is the restoration level.
L0, L1,..., L15. Therefore, the quantization width is Δ4. When the dynamic range DR is (T1 ≦ DR <256), the number of allocated bits is 4 bits.

FIG. 6 shows a dynamic range D in the range of (0 to 255).
It is an example of a frequency distribution in which R is the horizontal axis and the frequency of occurrence is the vertical axis. _{x 1, x 2, x 3} , x 4, each of the x _5, as described above, represents the number of blocks included five pieces of the dynamic range DR separated by threshold T1~T4 . (T4−
1) A block having the following dynamic range DR is 0
Since bits are allocated, the number of blocks x ₅ does not contribute to the amount of information generated. Thus, generation amount of information, obtained in _{4x 1 + 3x 2 + 2x 3} + x 4. This amount of generated information is compared with the data threshold, and if it exceeds the data threshold, a larger set of thresholds is applied, and the amount of generated information is calculated in a similar manner. In order to perform the calculation of the above equation, it is necessary to perform a process of obtaining the sum of the frequency distributions in each range for each set of the set thresholds, multiplying the sum by the number of allocated bits, and adding the sum. However, if the above processing is performed every time the set of thresholds is changed, it takes a long time until an optimal set of thresholds is determined.

In this embodiment, the frequency distribution shown in FIG. 6 is obtained by the frequency distribution generating circuit 8, and then the frequency distribution shown in FIG. 6 is converted into an integrated frequency distribution shown in FIG.
By converting to an integrated frequency distribution, the amount of generated information corresponding to a different set of thresholds can be calculated more quickly, and thus the convergence time until an optimal set of thresholds is obtained is reduced.

As can be understood from FIG. 7, the dynamic range DR
Starts from the maximum occurrence frequency, the occurrence frequencies of the smaller dynamic range DR are sequentially integrated, and an integrated frequency distribution graph is obtained. Therefore, the integration degree is x ₁ next up threshold T1, the accumulated power up threshold T2 (x ₁ + x ₂₎
Next, the accumulated power up threshold T3 is _{(x 1 + x 2 + x} 3) , and the the accumulated power up threshold _{T4 (x 1 + x 2 +} x 3 + x 4).

Generated information quantity for threshold T1~T4 is, 4 (x ₁ -0)
+3 _{[(x 1 + x 2) -x} 1 ] + 2 _{[(x 1 + x 2 + x} 3) - (x 1 +
x _2)] + 1 _{[(x 1 + x 2 + x} 3 + x 4) - (x 1 + x 2 + x 3) = 4x
Obtained a _{1 + 3x 2 + 2x 3 +} 1x 4. Once the cumulative frequency distribution graph (cumulative frequency distribution table) shown in FIG. 7 is created, when the set of thresholds is updated, the amount of generated information is immediately obtained by summing the four numbers. Can be.

In this embodiment, a compression circuit 14 is provided, and the compression circuit 14 multiplies the input level by α. This means
The maximum value MAX and the minimum value MIN are also compressed, and the dynamic range DR is also compressed by α times. In FIG.
This means that the distribution of the dynamic range DR moves toward zero. Therefore, even if the set of thresholds is fixed at the limit value, the amount of generated information can be controlled to be smaller by reducing α.

The limit value of each threshold is a value immediately before deterioration of a restored image is recognized when each threshold is gradually reduced,
Such a limit value can be set in advance by simulation or the like. However, since the value of the compression coefficient α differs depending on the input data, it is determined in the buffering circuit 9. In other words, when the amount of generated information does not fall below the target value even if the threshold value is reduced to the limit threshold value, the threshold value sets T1 to T4 are simultaneously set to (1 / α) times and the amount of generated information is obtained.

c. Buffering Circuit FIG. 4 shows an example of the buffering circuit 9. 4th
In the figure, 41 is a ROM storing a threshold value table
Is shown. The address code Pi is supplied to the ROM 41 from the address counter 42. The address counter 42 has a terminal
A reset signal is supplied every 11 to 2 frames. The address code Pi generated from the address counter 42 is taken out to the output terminal 13 and supplied to the encoding circuit 20 and the encoding circuit 21.

FIG. 8 shows an example of the threshold value table stored in the ROM 41. The ROM 41 stores (P0 to P3
1), for example, the threshold value (T4 = 10, T3) at the time of (P15)
= L1, T2 = l2, T1 = l3) are the limit values. Up to this limit, the compression factor is (α = 1). As the address code Pi increments to (P16, P17,..., P31), the compression coefficient α is changed to (α16, α17,. However, (1>α16>α17>...> α31)
And the dynamic range DR of all blocks is 25
Even when the value is set to 5, α is determined so that the generated information amount does not exceed the target value, and this α is set as the minimum compression coefficient α31. The manner and magnitude of the change of the thresholds T1 to T4 are set while observing the image quality. The threshold value of the first address code P0 is a very small value. When calculating the amount of generated information, the address code is set to P3
When sequentially changing toward 1, the amount of generated information monotonically decreases.

At the same time, when the set of thresholds is (Pi = P16), the range is (Pi ≧ P16) so that (l0 / α16, l1 / α16, l2 / α16, 13 / α16). The threshold is multiplied by (1 / α).

The threshold table generated from the ROM 41 is supplied to the information amount circuit 43. The information amount calculation circuit 43 is supplied from the terminal 10 with an integrated frequency distribution table. As described above, the amount of generated information corresponding to the threshold value table from the ROM 41 is obtained by the information amount calculation circuit 43. The generated information amount is supplied to the comparison circuit 44. The target value is supplied from the terminal 12 to the comparison circuit 44. The output signal of the comparison circuit 44 is supplied as a clock to the address counter 42, and the address counter 42 is incremented by the output signal of the comparison circuit 44 generated when the amount of generated information is larger than the target value.
When the amount of generated information falls below the target value, the increment is stopped.

The information amount calculation circuit 43 of the buffering circuit 9 uses the integrated frequency distribution table to determine the amount of generated information for the set of thresholds in the threshold table, that is, the selected set of thresholds. The total number of bits of the code signal DT when ADRC encoding is performed by applying the above is calculated. in this case,
The calculation of the amount of generated information is started from a set of threshold values that minimize the quantization distortion (a set of threshold values specified by the address code P0).

The calculated amount of generated information and the target value are compared by the comparison circuit 44. The target value is the maximum value of the transmission rate of the transmission data, and is, for example, (2 bits / pixel). When the set of thresholds reaches the limit value (10 to 13), when the amount of generated information is equal to or less than the target value, quantization of ADRC is performed using the set of thresholds. Therefore, the address code Pi when the amount of generated information becomes equal to or less than the target value is supplied to the encoding circuit 20. The compression coefficient is (α = 1). If the amount of generated information exceeds the target value, the address counter 42 is incremented, the set of thresholds is updated, and then, for a new set of thresholds that can reduce the amount of generated information,
The same processing as described above is repeated.

If the set of thresholds exceeds the limit value (that is, if the address code Pi is equal to or greater than P16), calculation of the amount of generated information and the target value And a comparison is made. When the amount of generated information falls below the target value, the address code Pi at that time is supplied to the compression circuit 14 and the encoding circuit 20. Therefore, the level of the input data is compressed by the compression coefficient α. On the other hand, in the encoding circuit 20, when the address code is equal to or larger than P15, as shown in FIG. 9, encoding is performed using a threshold value fixed to a limit value. FIG. 9 is an example of a threshold value table provided in the encoding circuit 20. Even when coding is performed with the threshold value fixed at the limit value, the amount of generated information is controlled to be equal to or less than the target value because the input level is compressed.

In addition to the code signal DT, a dynamic range DR, a minimum value MIN, an address code Pi, and a redundant code of an error correction code are transmitted, but since these data have a fixed length, when the rate of the transmission data is inspected. In addition, by giving the target value an offset, it can be ignored.

d. Modifications The present invention can be applied to ADRC of a three-dimensional block. When the three-dimensional block is composed of, for example, two two-dimensional regions respectively belonging to two frames, the number of pixels in one block is doubled. In addition, in ADRC of three-dimensional block,
For the purpose of increasing the compression ratio, it is determined whether or not there is motion between the two two-dimensional regions, and when there is a motion, the pixel data of the two two-dimensional regions, that is, encoding of all the pixel data in the block is performed. When there is no motion, a process of encoding pixel data of one two-dimensional area is performed. Therefore, the amount of generated information is (1: 2) between the stationary part and the moving image part.

In addition, the present invention can be applied to the case where the maximum frame difference information for each block is also taken into account in the above-described buffering of a three-dimensional block, and when ADRC is performed after performing sub-sampling to increase the compression ratio. Can also be applied.

Further, the present invention is not limited to buffering used in combination with a high-efficiency encoding method, and can be widely used for the purpose of keeping the amount of transmission data constant.

〔The invention's effect〕

According to the present invention, when the amount of generated information is large, processing such as encoding is performed after compressing the level of input data.
With the threshold value fixed at the limit value, the amount of generated information can be suppressed to a target value or less. Therefore, the threshold value does not become larger than the limit value, and it is possible to prevent the deterioration of the restored image quality such as block distortion from being noticeable.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a transmitting side according to an embodiment of the present invention, FIG. 2 is a schematic diagram for explaining blocks, and FIG.
FIG. 4 is a block diagram of a receiving side, FIG. 4 is a block diagram of an example of a buffering circuit, FIG. 5 is a schematic diagram for explaining variable-length quantization, and FIGS. 6 and 7 are frequency distribution tables. FIG. 8 is a block diagram for explanation, FIG. 8 is a schematic diagram of an example of a threshold table used for buffering, and FIG. 9 is a schematic diagram of an example of a threshold table used for encoding. . Explanation of main symbols in the drawing 1: input terminal of analog video signal, 3: blocking circuit, 4,15: maximum value detection circuit, 5,16: minimum value detection circuit, 7, 18, 19: subtraction circuit, 20 : Encoding circuit, 9: buffering circuit, 41: ROM storing a threshold table, 42: address counter, 43: information amount calculation circuit, 44: comparison circuit.

Claims (1)

(57) [Claims] 1. A block comprising an area belonging to the same field or a plurality of temporally continuous fields of a digital image signal, wherein variable-length coding is performed for each of a plurality of pixel data in the block and generated by coding. An information amount control circuit for controlling the amount of information to be provided, comprising: frequency counting means for counting the number of occurrences of each value of data within a predetermined period; and a plurality of threshold value sets each including a plurality of threshold values, Threshold value setting means for setting the threshold value set for each value of the data; and calculation for calculating the amount of generated information based on the set threshold value set and the output of the frequency counting means. Means, comparing the output of the arithmetic means with a target value, and in accordance with the comparison output, the amount of generated information during the predetermined period when the set of thresholds is sequentially changed does not exceed the target value Control means for controlling the threshold value setting means so as to determine the set of the threshold values having the minimum quantization distortion in the range; and a set of the determined threshold values for a plurality of data in the block. And a limit threshold value setting means for setting, as a limit threshold value, a value that minimizes the amount of generated information in the set of threshold values. Even when the threshold value is set to the limit threshold value by the control means, when the amount of generated information exceeds the target value, the limit value is given to the quantization means, An information amount control circuit wherein a signal level input to a quantization means is compressed.