JP2827224B2 - High efficiency coding device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency coding apparatus applied to an image signal, and more particularly to transmission of data to be recorded when a digital video signal is recorded on a magnetic tape. The present invention relates to a high-efficiency coding apparatus applied to control a rate to a predetermined value corresponding to a transmission path.

[Summary of the Invention] In the present invention, when performing variable length coding in which the number of coded bits is variable according to the dynamic range, a highly efficient coding apparatus that controls the amount of generated information so as not to exceed the transmission capacity of the transmission path In the above, a frequency distribution in which a block motion amount expression value is introduced is formed, and not only the threshold value in the level direction for determining the number of coded bits but also the motion threshold value for the frame dropping process is changed. The amount of information is controlled, and the amount of generated information is well controlled without increasing the quantization error.

The motion amount for each sample is compared with a threshold value, the number exceeding the threshold value is counted, and this count value is used as the block motion amount expression value. Therefore, it is possible to prevent the stationary block from being erroneously determined to be the moving block due to the nozzle, and to reduce the amount of generated information.

[Conventional technology]

The applicant of the present application obtains a dynamic range that is a difference between a maximum value and a minimum value of a plurality of pixels included in a two-dimensional block, as described in JP-A-61-144989.
A high-efficiency coding apparatus that performs coding adapted to the dynamic range has been proposed. Further, as described in JP-A-62-92620, a high-efficiency coding apparatus that performs coding adaptive to a dynamic range with respect to a three-dimensional block formed from pixels in an area included in each of a plurality of frames has been proposed. Proposed. Further, as described in Japanese Patent Application Laid-Open No. 62-128621, a variable length encoding method in which the number of bits changes according to the dynamic range so that the maximum distortion generated when performing quantization is constant. Proposed.

High-efficiency coding (referred to as ADRC) adapted to the above-described dynamic range is suitable for application to a digital VTR because the amount of data to be transmitted can be significantly reduced. In particular, the variable length ADRC can increase the compression ratio. However, in the variable-length ADRC, the amount of transmission data varies depending on the content of an image. Therefore, when using a fixed-rate transmission path such as a digital VTR that records a predetermined amount of data as one track, buffering processing is not performed. is necessary.

As a buffering method of the variable length ADRC, the present applicant forms an integral type dynamic range frequency distribution as described in Japanese Patent Application Laid-Open No. 63-111781, It proposes a method in which a set of prepared thresholds is applied to determine the amount of generated data in a predetermined period, for example, one frame period, and control is performed so that the generated data amount does not exceed a target value.

FIG. 8 shows a cumulative frequency distribution graph shown in the above-mentioned application. The horizontal axis in FIG. 8 is the dynamic range DR, and the vertical axis is the frequency of occurrence in block units. T1 to T4 written on the horizontal axis are threshold values. The threshold bits T1 to T4 determine the number of quantization bits. That is, (maximum value ~
In the case of the dynamic range DR in the range of (T1), the number of quantization bits is 4 bits. In the case of the range of (T1-1 to T2), the number of quantization bits is 3 bits. 1 to T3)
, The number of quantization bits is 2 bits,
In the range of (T3-1 to T4), the number of quantization bits is 1 bit, and in the range of (T4-1 to the minimum value), the number of quantization bits is 0 bit (when the code signal is Not transmitted).

When calculating the frequency distribution of the dynamic range DR within one frame period, the frequency distribution of the accumulation type is calculated from the threshold (T1-1) with respect to the frequency of occurrence of the dynamic range DR from the maximum value to the threshold T1. The occurrence frequency up to the threshold value T2 is integrated. The frequencies from the next threshold value (T2-1) to the threshold value T3 are also integrated. Hereinafter, the same processing is repeated. Therefore, the frequency of occurrence of the minimum value of the dynamic range DR is equal to the total number (M × N) of blocks included in one frame.

Thus, to form a frequency distribution of cumulative type, integration degree is x ₁ next up threshold T1, the accumulated power up threshold T2 is (x ₁ + x _2), and the integration of up to threshold T3 The frequency is (x ₁ +
x ₂ + x ₃ ), and the integrated frequency up to the threshold T4 is (x ₁ + x ₂ +
x ₃ + x ₄ ). Therefore, the amount of generated information (total number of bits) in one frame period is represented by the following equation.

4 (x ₁ -0) +3 _{[(x 1 + x 2) -x} 1 ] + 2 [(x ₁ + x ₂ +
_{x 3) - (x 1 +} x 2) ] + 1 _{[(x 1 + x 2 + x} 3 + x 4) - (x 1 +
x ₂ + x _3)] = as _{4x 1 + 3x 2 + 2x 3} + x 4 generated information quantity described above does not exceed the target value, the threshold T1~T4 is set. By changing the threshold value, the case of obtaining the optimum threshold value of the above x ₁ ~x ₄ is changed, the calculation of the generated information amount for each set of each threshold is made in accordance with the threshold value . Therefore, once an integrated frequency distribution table is created, the amount of generated information can be calculated quickly.

As described above, the method of converging the transmission data rate to the target value by changing, for example, four threshold values in the level direction is insufficient in performance in terms of reducing distortion such as quantization noise. there were.

Therefore, in the case of ADRC of a three-dimensional block composed of two regions respectively belonging to two frames, not only the threshold value in the level direction is changed, but also the threshold value for the frame drop processing is changed. There has been proposed a high-efficiency coding apparatus capable of performing transmission data buffering processing while suppressing deterioration of restored image quality.

For example, in JP-A-63-299587, as shown in FIG. 9, the dynamic range DR3 of a block and the maximum frame difference ΔF within a block (the absolute value of the difference in sample units between two regions constituting one block) Is the maximum value of, for example, 0
The maximum frame difference exceeding 19 is clipped in the range of ~ 19) and the frequency distribution table is formed on the axis. That is, a value of +2 is assigned to a range equal to or smaller than the maximum frame difference ΔF of each block, and a value of +1 is assigned to a range exceeding the maximum frame difference ΔF. This is because the threshold value MTH of the motion determination is compared with the maximum frame difference ΔF of the block at the time of the motion determination for determining the presence or absence of the frame drop. When (ΔF ≧ MTH), the frame is not dropped. , when the ([Delta] F <MTH), been decimating, amount of information generated when it is the decimating is because the _^1/2 of the amount of information generated when not is decimating.

The above-described frequency distribution table for the blocks included in the entire screen is formed, and then the frequency is integrated from 255 of the dynamic range DR3 toward 0 for each maximum frame difference ΔF, thereby obtaining an integrated frequency distribution table. Is obtained. FIG. 10 shows an integration type frequency distribution table obtained for each of the maximum frame differences ΔF in this manner. Using this cumulative frequency distribution table, a threshold value set and a motion threshold value for a level at which the amount of generated information does not exceed a target value
MTH is required. The motion threshold MTH is used to perform frame drop processing, and a set of thresholds is used to adjust the variable length of ADRC (dynamic range adaptive coding).
Is made.

Japanese Patent Application Laid-Open No. 63-299588 discloses a frequency distribution table in consideration of the fact that the dynamic range DR2 of a still block becomes smaller than the dynamic range DR3 of a motion block because the frame dropping process is an averaging process. Is described. FIG. 11 shows that both the dynamic ranges DR2 and DR3 of each block are obtained, and the dynamic range DR3 within the maximum frame difference ΔF of the block is +2.
Is assigned, and +1 is assigned to a range exceeding the maximum frame difference ΔF.

Further, JP-A-2-33283 discloses a maximum frame difference Δ
A method is shown in which the frequencies of blocks are totaled at a position determined by F and the dynamic range DR3, and a frequency distribution table is created. The creation of the frequency distribution table will be described with reference to FIGS. 12, the vertical axis indicates the dynamic range DR3, and the horizontal axis indicates the maximum frame difference ΔF. The maximum frame difference ΔF can take a value in a range of (0 to 255). For simplicity of the processing, all the maximum frame differences equal to or larger than the predetermined value may be replaced with the predetermined value as described above.

The occurrence frequency is written at a position defined by the dynamic range DR3 of each block and the maximum frame difference ΔF,
Counts are aggregated over two frame periods. In FIG. 12, the frequencies of occurrence of the regions not shown are all set to 0 for simplicity.

The frequency distribution table totaled over the two frame periods is converted to an integration type. The integration is performed in the directions of both the maximum frame difference ΔF and the dynamic range DR3. FIG. 13A
12 is obtained as a result of integrating the table shown in FIG. 12 in the direction from the maximum frame difference ΔF of 255 to 0. Next, the table shown in FIG. 13A is integrated in the direction from 255 of the dynamic range DR3 to 0 to obtain the table shown in FIG. 13B. The table shown in FIG. 13B is an integrated frequency distribution table. The frequency (47 in FIG. 13B) when (ΔF = 0, DR3 = 0) is the total number of blocks in the two-frame period.

The optimal threshold value set and the motion threshold value MTH are determined using the cumulative frequency distribution table. As a method for this determination, an initial value that does not cause jerkiness in the restored image is given as a motion threshold MTH, and the amount of generated information (total number of bits) is set to a target value by moving the threshold in the level direction. Determine a threshold set that does not exceed
If the target value cannot be reached, the motion threshold MT
By moving H, a threshold set that does not exceed the target value is searched again.

With reference to FIG. 14A, a process of calculating the amount of generated information using the frequency distribution table shown in FIG. 13 will be described.

When a motion threshold MTH is given, the range of (ΔF ≦ MTH) is treated as a still block, and the range of (ΔF> MTH) is treated as a motion block. For a still block, an encoded code signal of 16 pixels (pixels included in one block) is generated, and for a motion block, an encoded code signal of 32 pixels is generated.

When the threshold values T1 to T4 in the level direction are given, the number of coded bits is allocated as described below.

When (T4> DR3), 0 bits (T3> DR3 ≧ T4), 1 bit (T2> DR3 ≧ T3), 2 bits (T1> DR3 ≧ T2), 3 bits (DR3 ≧ T1) ), The frequency distribution table is divided into ten regions as shown in FIG. 14A by the 4-bit motion threshold value MTH and the threshold values T1 to T4 in the level direction. The sum of the frequencies included in each area is M00 to M41
The data amount DAv (the number of bits) of the code signal in two frame periods is calculated by the following equation.

DAv = 1 × 16 × M10 + 1 × 32 × M11 2 × 16 × M20 + 2 × 32 × M21 3 × 16 × M30 4 × 16 × M40 + 4 × 32 × M41 = 16 ｛M10 + 2M11 + 2M20 + 4M21 + 3M30 + 6M31 + 4M40 + 8M4
1｝ = 16 ｛(M10 + M11 + M20 + M21 + M30 + M31 + M40 + M41) +
(M11 + M21 + M31 + M41) + (M20 + M21 + M30 + M31 + M40
+ M41) + (M21 + M31 + M41) + (M30 + M31 + M40 + M41)
+ (M31 + M41) + (M40 + M41) + (M41)｝ For the amount of information generated during two frame periods, add a fixed data amount DAf (number of bits) to the variable data amount DAv according to the dynamic range of the above formula It was done. The fixed data amount DAf is the number of bits obtained by multiplying 17 bits obtained by adding DR3 and MIN3 and the judgment code SJ by the total number of blocks.

As can be seen from the above equation, the frequencies M00 to M41 of the plurality of regions
Are selectively integrated to calculate the data amount DAv.
The integrated value of the frequency enclosed in parentheses in the above equation can be immediately obtained from the integrated frequency distribution table shown in FIG. 13B.

FIG. 14B shows the positions of integrated values N10 to N41 enclosed in parentheses in the above equation in the integrated frequency distribution table. These integrated values correspond as follows.

N10 = (M10 + M11 + M20 + M21 + M30 + M31 + M40 + M41) N11 = (M11 + M21 + M31 + M41) N20 = (M20 + M21 + M30 + M31 + M40 + M41) N21 = (M21 + M31 + M41) N30 = (M30 + M31 + M40 + M41) N31 = (M30 + M31 + M40 + M41) N = (M31 + M40) = 41 In order to calculate the data amount DAv, DAv = 16 {N10 + N11 + N20 + N21 + N30 + N31 + N40 + N41} is performed.

[Problems to be solved by the invention]

As described above, the information amount control device proposed earlier determines a motion block and a still block by comparing the maximum frame difference ΔF representing the motion amount of the block with the motion threshold value MTH. Was. Maximum frame difference ΔF
Is the maximum value among the absolute values of the differences between the sample data of the current frame and the sample data of the previous frame obtained for a plurality of pixels in the block. Therefore, when a maximum frame difference ΔF of a prominent level occurs due to noise, the block is erroneously determined to be a motion block despite being a still block. As a result, the percentage of motion blocks increases,
Since the amount of generated information increases, there is a problem that the image quality of the restored image is deteriorated.

Accordingly, an object of the present invention is to provide a high-efficiency coding apparatus in which a determination of a motion block and a still block is prevented from being erroneously performed by introducing a value having a small influence of noise as a value representing a motion amount in block units. Is to provide.

[Means for solving the problem]

The present invention relates to a circuit 3 for obtaining a dynamic range DR3 which is a difference between a maximum value MAX3 and a minimum value MIN3 of a plurality of pixel data included in a block composed of regions belonging to a plurality of frames of a digital image signal; Circuit 3 for detecting the amount of motion
And a circuit 5 for comparing the amount of motion with a threshold value, counting the number of samples exceeding the threshold value, and outputting a count value N, and a dynamic range DR3 for each block and a predetermined period of time with the count value N as an axis. A circuit 6 for obtaining a frequency distribution table; circuits 12 and 14 for averaging the corresponding pixel data between a plurality of fields for a block having a count value N equal to or less than a predetermined value MTH and performing frame drop processing; Circuits 13 and 15 for compressing and encoding according to the dynamic range DR3 of the block
By applying a threshold value T1 to T4 that is applied to the dynamic range DR3 to determine the number of encoded bits and a count value N to the frequency distribution table, the amount of generated information is obtained. Threshold so that the volume does not exceed the transmission capacity
A circuit 8 for setting T1 to T4 and a predetermined value MTH of the count value N.

[Action]

According to the present invention, when performing high-efficiency encoding, a single image is divided into a number of three-dimensional blocks by a high-efficiency encoding device that controls the amount of generated information so as not to exceed the transmission capacity of the transmission path. The maximum value MAX3, the minimum value MIN3, and the dynamic range DR3 of the pixel data included in each block are obtained, and the motion amount (for example, frame difference FDi ) Is detected. The frame difference FDi is compared with a threshold, and the number of samples exceeding the threshold is counted. The count value is subjected to an isolated point removal process as necessary, and is set to a value N representing a block motion amount. This value N is compared with the motion threshold MTH, where N is the motion threshold MTH
For smaller still blocks, the amount of generated information is reduced by the frame drop process.

When determining the amount of generated information, a frequency distribution table is formed with the dynamic range DR3 and the block motion amount N as axes.
The frequency distribution table is formed by writing the frequency for each block into the memory using the dynamic ranges DR3 and N as addresses, and totaling the frequency in a predetermined period, for example, two frame periods. This frequency distribution table is converted into an integration type frequency distribution table.

Using the cumulative frequency distribution table, threshold values T1 to T4 in the level direction and the motion threshold value MTH are determined so that the amount of generated information does not exceed the target value. A frame drop process is performed according to the magnitude relationship of the block N value with respect to the motion threshold value MTH. Also, by the threshold values T1 to T4 in the level direction,
The number of coding bits in variable-length high-efficiency coding, for example, in ADRC is controlled. Then, the encoded data obtained by the variable length ADRC is recorded on a magnetic tape.

According to the present invention, the movement threshold value MTH, which is a criterion for determining whether or not to perform the frame dropping process, is also moved. Therefore, good buffering that cannot be achieved only by changing the threshold value in the level direction can be performed. Can be. In addition, since the value N representing the block motion amount is hardly affected by noise, it is possible to correctly determine a still block and a motion block, and to prevent deterioration of the image quality of a restored image.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in the following order with reference to the drawings.

a. Configuration on the recording side b. ADRC encoder c. Block motion amount detection circuit a. Configuration on the recording side FIG. 1 shows the configuration on the recording side of one embodiment of the present invention, and is indicated by 1 in FIG. For example, 1
A digital video signal whose samples are quantized to 8 bits is supplied. This digital video signal is supplied to the blocking circuit 2. The blocking circuit 2 converts data in the order of television scanning into data in the order of blocks.

In the blocking circuit 2, for example, a screen of one frame of (520 lines × 720 pixels) is (M ×
N) Subdivided into blocks. One block has a size of (4 lines × 4 pixels), for example, as shown in FIG.
Areas. Each region belongs to two temporally consecutive frames. Further, as shown in FIG. 4, the sampling pattern has an offset between blocks due to subsampling. In FIG. 4, ○ indicates a pixel to be transmitted, △ indicates a pixel not to be transmitted, and in a spatially corresponding block after the next two frames, transmission and thinning pixels have the opposite relationship. Such a sampling pattern enables good interpolation in a still area when interpolation is performed on the thinned pixels on the receiving side. From the blocking circuit 2, B ₁₁ , B ₁₂ , B ₁₃ ,.
A digital video signal converted to the order of the _MN blocks is generated.

An output signal of the blocking circuit 2 is supplied to the detection circuit 3 and the delay circuit 4. The detection circuit 3 calculates the maximum value of each block.
The maximum value MIN3 and the minimum value MIN3 are detected, and the dynamic range DR3, which is the difference between the maximum value MIN3 and the minimum value MIN3, is detected. The difference between the data of the pixels at the same position is obtained between the two regions constituting one block, and the difference between the pixels is converted into an absolute value, which is used as the frame difference FDi. That is, the data of the current frame and x _m i, the data of the previous frame and x _m-1 i, frame FDi sample units, FDi = | is obtained as _{| x m i-x m-} 1 i.

The frame difference FDi from the detection circuit 3 is supplied to a block motion amount (N) detection circuit 5, and the dynamic range DR3 from the detection circuit 3 is supplied to a frequency distribution generation circuit 6.
As will be described later, the block motion amount detection circuit 5 compares each of the 16 frame differences FDi for each block with a threshold value and counts the number of frame differences FDi exceeding the threshold value. This count value is subjected to an isolated point removal process, and is set as a block motion amount N. The block motion amount N is supplied to the frequency distribution generation circuit 6.

This frequency distribution generating circuit 6 has a dynamic range DR3
The vertical axis is (= MAX3−MIN3 + 1), the block motion amount N is the horizontal axis, and the frequency of occurrence in block units is totaled over two frame periods. The frequency distribution table formed in this manner is supplied to the integrated frequency distribution generating circuit 7 to form an integrated frequency distribution table.

Threshold value determination circuit 8 using an integrated frequency distribution table
Determine the optimal thresholds (thresholds T1 to T4 for level and motion threshold MTH). The optimal threshold is
It means a threshold value at which encoding can be performed so that the total number of bits per two frames does not exceed the transmission capacity of the transmission path. This optimum threshold is obtained using the motion threshold MTH as a parameter. A ROM 9 is provided in association with the threshold value determination circuit 8. The ROM 9 stores a program for obtaining an optimum threshold.

The pixel data PD that has passed through the delay circuit 4 is supplied to the frame difference detection circuit 10. This frame difference detection circuit 10
The frame difference FDi is detected in the same manner as the detection circuit 3 described above. The frame difference FDi and the pixel data PD from the frame difference detection circuit 10 are supplied to a block motion amount (N) detection circuit 11 similar to the block motion amount detection circuit 5, and a value N representing the motion amount in block units is detected. You. The block motion amount N and the pixel data PD are supplied to the motion determination circuit 12. The motion determination circuit 12 compares the motion threshold value MTH from the threshold value determination circuit 8 with the block motion amount N, and determines whether the block to be processed is a motion block or a still block.

A block having a relationship of (block motion amount N> motion threshold MTH) is determined as a motion block, and a block having a relationship of (block motion amount N ≦ motion threshold MTH) is determined as a still block. The pixel data of the motion block is
It is supplied to the three-dimensional ADRC encoder 13. The pixel data of the still block is supplied to the averaging circuit 14. The averaging circuit 14 after adding a data each other pixels at the same position in the two areas included in one block ^_1/2,
To form a _^1/2 the number of pixels of the block of the number of pixels original 1 block. Such a process is called a frame drop process.
The output signal of the averaging circuit 14 is supplied to a two-dimensional ADRC encoder 15. These encoders 13 and 15 are supplied with threshold values T1 to T4 from the threshold value determination circuit 8.

In the three-dimensional ADRC encoder 13, (4 lines x 4 pixels x
Maximum value MAX3, out of a total of 32 pixel data (2 frames)
The minimum value MIN3 is detected, and the dynamic range DR3 is obtained from (MAX3-MIN3 + 1 = DR3). The number of bits of the code signal DT3 is determined from the relationship between the dynamic range DR3 of the block and the threshold values T1 to T4. That is, (DR3 ≧
In the block of (T1), a 4-bit code signal is formed. In the block of (T1> DR3 ≧ T2), a 3-bit code signal is formed. In the block of (T2> DR3 ≧ T3),
A 2-bit code signal is formed, and in a block of (T3> DR3 ≧ T4), a 1-bit code signal is formed and (T4
> DR3), 0 bits, that is, no code signal is transmitted.

For example, in the case of 4-bit quantization encoding, the detected dynamic range DR3 is divided into 16 (= 2 ⁴ ) and corresponds to the range to which the data level after removing each minimum value MIN3 of the pixel data belongs. The generated 4-bit code signal DT3 is generated.

In the two-dimensional ADRC encoder 15, the maximum value MIN2, the minimum value MIN2,
The dynamic range DR2 is detected, and a code signal DT2 is formed. However, the subject to coding, the pre-stage of the averaging circuit 14, a data number of pixels is ^_1/2.

Output signal of 3D ADRC encoder 13 (DR3, MIN3, DT3)
And output signal of 2D ADRC encoder 15 (DR2, MIN2, DT2)
Is supplied to the selector 16. The selector 16 is controlled by a judgment signal SJ from the motion judgment circuit 12. That is, in the case of a motion block, the selector 16 selects the output signal of the three-dimensional ADRC encoder 13, and in the case of a stationary block, the selector 16 selects the output signal of the two-dimensional ADRC encoder 15. The output signal of the selector 16 is supplied to the framing circuit 17.

To the framing circuit 17, in addition to the output signal of the selector 16, a threshold code Pi specifying a threshold set and a determination code SJ are supplied. The threshold code Pi changes in units of two frames, and the judgment code SJ changes in units of one block. The framing circuit 17 converts the input signal into recording data having a frame structure. In the framing circuit 17, an error correction code is encoded as necessary. The recording data obtained at the output terminal 18 of the framing circuit 17 is supplied to a rotary head via a recording amplifier, a rotary transformer, etc., though not shown, and is recorded on a magnetic tape.

b. ADRC Encoder FIG. 5 shows an example of the configuration of the three-dimensional ADRC encoder 13. In FIG. 5, reference numeral 21 denotes an input terminal, to which a maximum value detection circuit 22, a minimum value detection circuit 23, and a delay circuit 24 are connected. The maximum value MAX3 detected by the maximum value detection circuit 22 is supplied to the subtraction circuit 25. The minimum value MIN3 detected by the minimum value detection circuit 23 is supplied to the subtraction circuit 25, and the output signal of the subtraction circuit 25 is added to the +1 addition circuit 27.
Supplied to From the +1 adder circuit 27 (MAX3-MIN3 + 1)
The dynamic range DR3 represented by is obtained.

The pixel data that has passed through the delay circuit 24 is supplied to the subtraction circuit 26. The minimum value MIN3 is supplied to the subtraction circuit 26,
The pixel data PDI after the removal of the minimum value is generated from the subtraction circuit 26. This pixel data PDI is supplied to the quantization circuit 30.
The dynamic range DR3 is taken out to the output terminal 31 and supplied to the ROM 28. The ROM 28 is supplied with a threshold code Pi generated by the threshold determination circuit 8 from a terminal 29. From the ROM 28, a quantization step Δ and a bit number code Nb indicating the number of bits are generated.

The quantization circuit 30 is supplied with the quantization step Δ, and the code signal DT3 is formed from the data PDI after the removal of the minimum value and the quantization step Δ. This code signal DT3 is output terminal 34
Is taken out. Output signals generated at these output terminals 31, 32, 33, 34 are supplied to the framing circuit 17. The bit number code Nb is used in the framing circuit 17 to select valid bits.

The formation of the code signal DT3 in the quantization circuit 30 will be described. In general, in the case of encoding in which n bits are allocated, when the level of the original data PD is represented by Li and the quantization code is represented by Qi, Is required. [] Means truncation.

On the decoding side, when the restoration level is represented by i, i = (DR3 / 2 ⁿ ) × (Qi + 0.5) + MIN3 = Δ × (Qi + 0.
5) + MIN3 processing is performed.

c. Example of block motion amount detection circuit The value N representing the block motion amount is obtained by comparing the frame difference FDi, which is the motion expression value of each sample in the block, with a threshold value, and counting the number of samples equal to or larger than the threshold value Is obtained by performing an isolated point removal process on this count value. As the motion expression value of the sample, a square difference of each sample may be used instead of the frame difference FDi.

The circuits 5 and 11 for detecting the value N representing the block motion amount have the configuration shown in FIG. In FIG. 6, a frame difference FDi from an input terminal indicated by 41 is compared with a comparison circuit 42.
Supplied to The comparison circuit 42 has a threshold value Tm
Is supplied. The comparison circuit 42 generates a high-level comparison output when (FDi> Tm), and the comparison output of the comparison circuit 42 is supplied to the enable terminal EN of the counter 44.

The counter 44 is connected to the terminal 45 during the period when the comparison output is at the high level.
, And is cleared by the clock of the block cycle from the terminal 46. In this example, since 16 frame differences FDi are obtained per block, the count value n of the counter 44 takes any value in the range of (0 to 16). The count value n of the counter 44 has a large value when the motion amount of the block is large, and has a small value when the motion amount of the block is small, and indicates the amount of motion of the block. When the maximum value of the frame difference is used as the expression value of the block motion amount, the maximum value becomes considerably large due to the prominent noise. Since counting is performed, the influence of noise is reduced.

The count value n of the counter 44 is supplied to the ROM 47. In the ROM 47, an isolated point removal process is performed. That is, the output N from the ROM 47 is N = 0 (n <Km) and N = n (n ≧ Km), where the isolated point threshold is Km. When the count value n of the counter 44 is smaller than the threshold value Km, the possibility of an isolated point as noise is high.
(N = 0). The output signal of the ROM 47 is extracted as an output signal via the register 48. Register 48 has a terminal
The output signal of the ROM 47 is output to the outside in synchronization with the clock of the block cycle from 49.

The above-described block motion amount value N is applied as an axis of the motion amount of the frequency distribution table, and a frequency distribution table having N and the dynamic range DR3 as two axes is formed as shown in FIG. As described at the beginning, the frequency distribution table is formed by assigning (+1) to a portion of the table treated as a still block and (+2) to a portion treated as a motion block.
Or a method of allocating the number of blocks in which one screen (two frame periods) occurs. In practice, the frequency distribution table uses memory, and the horizontal and vertical addresses of the memory are N
And DR3.

This frequency distribution table is obtained by the integrated frequency distribution generation circuit 7.
It is converted into an integrated frequency distribution table. Threshold value determination circuit 8
In the integration type frequency distribution table, the motion threshold MTH
The generated information amount is calculated by applying the thresholds T1 to T4 regarding the level and the level. The calculated amount of generated information is compared with the target value, and the motion threshold value MTH and the threshold values T1 to T4 are determined in a range where the generated information amount does not exceed the target value. Frame drop processing is performed by the motion threshold MTH, and the thresholds T1 to T4 are used by the ADRC encoders 13 and 15.

Since the total number of samples in a block is constant,
The number of samples in which the frame difference FDi is equal to or less than the threshold value may be counted, and the counted value may be used. In FIG. 1, the frame difference detection circuit 10 and the block motion detection circuit 11 are provided separately from the detection circuit 3 and the block motion detection circuit 5. The obtained frame difference FDi and the block motion amount N may be stored, and motion determination may be performed using the stored values. Furthermore, 3D ADRC encoder
13 and the two-dimensional ADRC encoder 15 can have a common circuit configuration.

〔The invention's effect〕

The present invention relates to a high-efficiency encoding apparatus such as a variable-length ADRC of a three-dimensional block, in which, in a stationary area, the amount of generated information is reduced from a target value in consideration of the fact that the amount of transmitted information is compressed by frame drop processing. To keep it small, a motion threshold is introduced as well as the dynamic range DR. Therefore, by moving the motion threshold value, the area treated as a still block increases, and the threshold value in the level direction does not have to be strict. Therefore, according to the present invention, the quantization noise of the restored image can be reduced. Further, in the present invention, as the value indicating the amount of motion of the block, not the maximum frame difference ΔF, but the number N where the frame difference of each sample exceeds the threshold value, the influence of prominent noise can be reduced, It is possible to correctly determine a still block and a moving block. Therefore, it is possible to reduce the possibility that a still block is determined to be a motion block due to noise, reduce the amount of information generated by the frame dropping process, eliminate the need for strict thresholds for levels, and improve the image quality of a restored image. Can be planned.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration on the recording side according to an embodiment of the present invention, FIGS. 2, 3, and 4 are schematic diagrams for explaining the configuration of the block, and FIG. 5 is an ADRC encoder. FIG. 6 is a block diagram of an example of a block motion amount detection circuit, FIG. 7 is a schematic diagram showing a frequency distribution table, and FIG. FIG. 9, FIG. 10, FIG. 10 and FIG. 11 are schematic diagrams used to explain another example of the buffering circuit proposed earlier, FIG. 12, FIG.
FIGS. 13 and 14 are schematic diagrams used to explain still another example of the buffering circuit proposed previously. Explanation of main symbols in the drawings 1: Digital video signal input terminal, 2: Blocking circuit, 3: Detection circuit, 5, 11: Block motion amount detection circuit, 6: Frequency distribution generation circuit, 7: Integration type frequency distribution Generation circuit, 8: threshold value determination circuit, 10: frame difference detection circuit, 12: motion determination circuit, 13: three-dimensional ADRC encoder, 14: averaging circuit, 15: two-dimensional ADRC encoder.

Claims (1)

(57) [Claims] A means for obtaining a dynamic range, which is a difference between a maximum value and a minimum value of a plurality of pixel data included in a block including an area belonging to a plurality of frames of a digital image signal; Means for detecting the amount; means for comparing the amount of motion with a threshold value, counting the number of samples exceeding the threshold value, and outputting a count value; and a dynamic range for each block and the count value as an axis. Means for obtaining a frequency distribution table for a predetermined period of time, means for performing a frame drop process by taking an average of corresponding pixel data between a plurality of fields for a block whose count value is equal to or less than a predetermined value, and a plurality of pixel data in the block Means for compression encoding according to the dynamic range of the block, and the number of encoded bits applied to the dynamic range The generated information amount is obtained by giving the determined threshold value and the count value to the frequency distribution table, and the threshold value and the total amount are calculated so that the generated information amount does not exceed the transmission capacity. Means for setting a predetermined value of a numerical value.