JPH02307275A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02307275A JPH02307275A JP1129401A JP12940189A JPH02307275A JP H02307275 A JPH02307275 A JP H02307275A JP 1129401 A JP1129401 A JP 1129401A JP 12940189 A JP12940189 A JP 12940189A JP H02307275 A JPH02307275 A JP H02307275A
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- Prior art keywords
- upper electrode
- capacitor
- insulating film
- film
- semiconductor device
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000003990 capacitor Substances 0.000 claims abstract description 32
- 230000015654 memory Effects 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 46
- 239000010409 thin film Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 230000010287 polarization Effects 0.000 abstract description 8
- 229910020698 PbZrO3 Inorganic materials 0.000 abstract description 3
- 229910003781 PbTiO3 Inorganic materials 0.000 abstract 3
- 239000000126 substance Substances 0.000 abstract 3
- 239000002075 main ingredient Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、強誘電体を用いた、不揮発性メモリに関し、
特にキャパシタに適用して有効な技術に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a nonvolatile memory using ferroelectric material.
In particular, it relates to techniques that are effective when applied to capacitors.
半導体不揮発性メモリとしては、絶縁ゲート中のトラッ
プまたは浮遊ゲートにシリコン基板からの電荷を注入す
ることにより、シリコン基板の表面ポテンシャルが変調
される現象を用いた、ＭＩＳ型トランジスタか、一般に
使用されており、ＥＰＲＯＭ （紫外線消去型不揮発性
メモリ）やＥＥＰＲｏＭ（ｇ気的書き換え可能型不揮発
性メモリ）などとして実用化されている。しかしこれら
の不揮発性メモリは、情報の書き換え電圧が、通常約２
０Ｖ前後と高いなどの欠点を有する。電気的に分極が反
転可能である強誘電体を用いた、不揮発性メモリについ
ては、書き込み電圧も、通常用いられているＳＶであり
、また電源を切っても分極は保持されるため、理想的な
不揮発メモリーとなる可能性を有する。Semiconductor non-volatile memories are commonly used MIS type transistors, which utilize a phenomenon in which the surface potential of the silicon substrate is modulated by injecting charges from the silicon substrate into traps or floating gates in an insulated gate. It has been put into practical use as EPROM (ultraviolet erasable nonvolatile memory) and EEPRoM (electronically rewritable nonvolatile memory). However, in these nonvolatile memories, the information rewriting voltage is usually about 2
It has drawbacks such as high voltage of around 0V. For non-volatile memories that use ferroelectric materials whose polarization can be electrically reversed, the write voltage is the commonly used SV, and the polarization is maintained even when the power is turned off, making it ideal. It has the potential to become a non-volatile memory.
この様な強誘電体を用いた不揮発性メモリ構造の一つに
、Ｗ、Ｉ、ＫＩＮＮＥＹ：’ Ａ Ｎ０Ｎ−ＶＯＬＡ
ＴＩＬＥ ＭＥＭＯＲＹ ＣＥＬＬＢＡＳＥＤ
ＯＮ ＦＥＲＲＯＥＬＥＣＴＲＩＣ３ＴＯＲＡＧＥ
ＣＡＰＡＣＩＴＯＲ５’、ＩＥＤＭ、８７．ｐｐ８５
０−に開示された、第３図に代表される様な、キャパシ
タをトランジスタの上に絶縁膜を介して積層する、いわ
ゆるスタックド型構造がある。One of the nonvolatile memory structures using such ferroelectric material is W, I, KINNEY:' A N0N-VOLA.
TILE MEMORY CELLBASED
ON FERROELECTRIC 3TORAGE
CAPACITOR5', IEDM, 87. pp85
There is a so-called stacked structure in which a capacitor is stacked on a transistor with an insulating film interposed therebetween, as typified by FIG.
強誘電体を用いたキャパシタの理想的な印加電圧と、蓄
積電荷との関係を示したのか、第４図−Ｃある。しかし
第３図のキャパシタの場合、印加電圧と、蓄積電荷との
関係は、第５図の様になる。Figure 4-C shows the relationship between the ideal applied voltage and accumulated charge in a capacitor using a ferroelectric material. However, in the case of the capacitor shown in FIG. 3, the relationship between the applied voltage and the accumulated charge is as shown in FIG.
これは、第６図の様に、キャパシタの電極端の電界か、
前記電極下の外側に回わりこむため、その部分の分極が
必要になるためである。したかって、理想的な場合と比
較すると、分極が生じさせたり、分極を反転させるには
、高い電圧か必要となる。This is the electric field at the electrode end of the capacitor, as shown in Figure 6.
This is because since it goes around to the outside under the electrode, it is necessary to polarize that part. Therefore, compared to the ideal case, a higher voltage is required to generate polarization or reverse polarization.
またこれを不揮発性メモリーのキャパシタとして用いれ
ば、書き込み電圧を高く設定してやる必要かあるし、書
き込み時間も長時間となる。また分極電荷ら一定でない
。また、高い電圧が必要のため、不揮発性メモリ段別の
マージンもなくなるし、低電圧動作させた場合、不安定
となる。Furthermore, if this is used as a capacitor for a non-volatile memory, it is necessary to set a high write voltage and the write time will be long. Also, the polarization charge is not constant. Furthermore, since a high voltage is required, there is no margin for each stage of nonvolatile memory, and when operating at a low voltage, it becomes unstable.
そこで本発明は、この様な問題を解決するもので、その
目的とするところは、低電圧動作か可能で、分極速度も
速（、安定した高誘電体膜を用いたキャパシタ及び不揮
発性メモリーを提供するところにある。The present invention is intended to solve these problems, and its purpose is to develop capacitors and non-volatile memories that are capable of low voltage operation, have a fast polarization speed (and have a stable high dielectric constant film). It's there to provide.
本発明の半導体装置は、
（１）半導体基板上に絶縁膜が形成されており、前記絶
縁膜上に下部電極が形成されており、前記下部電極上に
強誘電体薄膜が形成されており、前記強誘電体薄膜上に
第１上部電極が形成されているキャパシタにおいて、前
記第１上部電極上に第２絶縁膜が形成されており、前記
第１上部電極の端上に前記第２絶縁膜を介して一定電圧
を印加した第２上部電極か形成されていることを特徴と
する。The semiconductor device of the present invention includes: (1) an insulating film is formed on a semiconductor substrate, a lower electrode is formed on the insulating film, and a ferroelectric thin film is formed on the lower electrode; In the capacitor in which a first upper electrode is formed on the ferroelectric thin film, a second insulating film is formed on the first upper electrode, and the second insulating film is formed on an end of the first upper electrode. A second upper electrode is formed to which a constant voltage is applied via.
（２）請求項１紀載の半導体装置において、前記強誘電
体薄膜の主成分が少なくともＰｂＴｉＯｓＰＺＴ （Ｐ
ｂＴｉＯｓ ／ＰｂＺｒＯ３） 、ＰＬＺＴ （Ｌ ａ
／ Ｐ ｂ Ｔ Ｌ Ｏ３／ Ｐ ｂ Ｚ ｒ Ｏ３
）のうちのいずれかであることを特徴とする。(2) In the semiconductor device according to claim 1, the main component of the ferroelectric thin film is at least PbTiOsPZT (P
bTiOs /PbZrO3), PLZT (La
/ P b T L O3 / P b Z r O3
).
（３）請求項１記載の半導体装置において、前記第２上
部電極は、高濃度に不純物を注入された多結晶シリコン
膜もしくはそのポリサイド膜から成ることを特徴とする
。(3) In the semiconductor device according to claim 1, the second upper electrode is made of a polycrystalline silicon film into which impurities are implanted at a high concentration or a polycide film thereof.
（４）請求項１記載の半導体装置において、前記キャパ
シタを不揮発性メモリのキャパシタとして用いたことを
特徴とする。(4) The semiconductor device according to claim 1, wherein the capacitor is used as a capacitor of a nonvolatile memory.
第１図は本発明の１実施例における半導体装置の１折面
図である。また
第２図（ａ）〜第２図（ｃ）はその製造工程ごとの主要
断面図である。FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. Moreover, FIGS. 2(a) to 2(c) are main sectional views for each manufacturing process.
なお実施例の全図において、同一の機能を有するものに
は、同一の符号を付け、その繰り返しの説明は省略する
。In all the figures of the embodiment, parts having the same functions are denoted by the same reference numerals, and repeated explanations thereof will be omitted.
以下、第２図（ａ）〜第２図（ｃ）に従い、説明してい
く。ここでは説明の都合上、Ｎチャネルトランジスタを
用いた例につき説明する。Hereinafter, the explanation will be given according to FIGS. 2(a) to 2(c). For convenience of explanation, an example using an N-channel transistor will be described here.
まず、第２図（ａ）の如く、例えばＰ型の８１基板１を
用いる。比抵抗は２００ｈｍ、ａｍ程度が適当てあろう
。それに素子分離用絶縁膜２を例えばＬＯＣＯ３法によ
り約６００ＯＡ形成する。First, as shown in FIG. 2(a), for example, a P-type 81 substrate 1 is used. A suitable resistivity would be about 200 hm or am. Then, an element isolation insulating film 2 of about 600 OA is formed by, for example, the LOCO3 method.
７はゲート膜であり、前記素子分離用絶縁膜２を形成後
、酸化雰囲気中て熱酸化させ形成する。例えば３００八
程度が適当であろう。A gate film 7 is formed by thermal oxidation in an oxidizing atmosphere after the element isolation insulating film 2 is formed. For example, about 3008 would be appropriate.
４はゲート電極となる、例えば多結晶Ｓｉてあり、例え
ば４０００への膜厚で形成する。５と６は、ＭＯＳｌ−
ランジスタのソース、ドレインとなるＮ型拡散層であり
、例えば前記ゲート電極４を形成したあとに、イオン注
入法により、リンを４×ＩＱ”ｃｍ−２注入することに
より形成する。３は、前記Ｓｉ基板１に形成したＭＯ８
型トランジスタと分離するための第１層間絶縁膜であり
、化学気相成長法（ＣＶＤ法）により例えば２０００人
の５１０２を形成する。Reference numeral 4 serves as a gate electrode, and is made of polycrystalline Si, for example, and is formed to a thickness of, for example, 4000 nm. 5 and 6 are MOSl-
These are N-type diffusion layers that become the source and drain of the transistor, and are formed by, for example, implanting 4×IQ"cm-2 of phosphorus by an ion implantation method after forming the gate electrode 4. MO8 formed on Si substrate 1
This is a first interlayer insulating film for isolating from a type transistor, and is formed by chemical vapor deposition (CVD) to form a film 5102 of, for example, 2,000 layers.
そしてキャパシタの下部電極８として、例えばＰｔを、
スパッタ法により例えば５０００人形成する。そしてフ
ォト・エツチングの工程により所定形のパターンを形成
する。なお本実施例では、下部電極はキャパシタの固定
電位（接地）になっている。For example, Pt is used as the lower electrode 8 of the capacitor.
For example, 5,000 layers are formed by sputtering. Then, a predetermined pattern is formed by a photo-etching process. In this embodiment, the lower electrode is at a fixed potential (ground) of the capacitor.
次に第２図（ｂ）の如く、強誘電体膜９を例えばＰｂＴ
ｉ０．を、例えばスパッタ法により５０００Ａ形成する
。そして次に例えば、Ｎ２雰囲気中で５５０℃で、１時
間熱処理を行なう。次に前記強誘電体膜９を、フォト・
エツチングの工程により所定形のパターンに形成する。Next, as shown in FIG. 2(b), the ferroelectric film 9 is made of, for example, PbT.
i0. 5000A is formed by, for example, a sputtering method. Then, for example, heat treatment is performed at 550° C. for 1 hour in a N2 atmosphere. Next, the ferroelectric film 9 is photo-photographed.
A predetermined pattern is formed by an etching process.
次に第１上部電極１０として、例えばｐｔを５００ＯＡ
、スパッタ法により形成し、フォト・エツチングの工程
により、所定形のパターンに形成する。Next, as the first upper electrode 10, for example, 500OA of PT is used.
, a sputtering method, and a photo-etching process to form a predetermined pattern.
次に第２図（ｃ）の如く、第２層間絶縁膜１１を形成す
る。化学気相成長法で５００への５ｉＯ７を形成するの
が適当であろう。次に、前記第１上部電極１０の端上に
第２上部電極１２を形成する。例えば、前記第１上部電
極１０と同し様にｐｔで形成しても良いが、Ｐ（リン）
などを５×Ｉ Ｑ ”ｃ ｍ−２以上の高濃度に不純物
を注入した多結晶Ｓｉ膜や、そのポリサイド膜ならば、
メモリーセル部以外（例えば入力出回路など）では、配
線として用いることか可能である。なお、この第２上部
電極１２は、一定電圧（例えば４Ｖ）に印加してお（。Next, as shown in FIG. 2(c), a second interlayer insulating film 11 is formed. It may be appropriate to form 500 to 5iO7 by chemical vapor deposition. Next, a second upper electrode 12 is formed on the end of the first upper electrode 10. For example, it may be formed of PT like the first upper electrode 10, but it may be formed of P (phosphorus).
If it is a polycrystalline Si film or its polycide film into which impurities are implanted at a high concentration of 5×I Q ”cm-2 or more,
It is possible to use it as wiring in areas other than the memory cell portion (for example, input/output circuits). Note that a constant voltage (for example, 4V) is applied to the second upper electrode 12 (.
そして最後に、第３層間絶縁膜１３を化学気ト（１成長
法により形成し、前記第１上部電極１０及び前記ソース
５上に接続穴を、フォト・エツチングの工程により形成
し、例えばＡＬ膜１４を１μｍはどスパッタ法により形
成し、前記第１上部電極１０及び前記ソース５を接続す
るように、前記ＡＬ膜１４をフォト・エツチングするこ
とにより、第１図の様な本実施例を得る。Finally, a third interlayer insulating film 13 is formed by a chemical vapor deposition method, and connection holes are formed on the first upper electrode 10 and the source 5 by a photo-etching process. 14 is formed to a thickness of 1 μm by sputtering, and the AL film 14 is photo-etched so as to connect the first upper electrode 10 and the source 5, thereby obtaining this embodiment as shown in FIG. .
なお、本実施例では、強誘電体膜としてＰｂＴ１０３を
用いたが、Ｐ Ｚ Ｔ （Ｐ ｂ Ｔ ｉ ０３ ／
Ｐ ｂＺ、ｒ０３） 、ＰＬＺＴなどを用いても良い。In this example, PbT103 was used as the ferroelectric film, but P Z T (P b T i 03 /
P bZ, r03), PLZT, etc. may also be used.
この様に、キャパシタの前記第１上部電極１０の端上に
前記第２絶縁膜１１を介して前記第２上部電極１２を形
成することにより、第７図の様に、キャパシタの電極端
の電界がキャパシタ外に回りこむことがなくなり、前記
第１上部電極１０と前記下部電極８とにはさまれた部分
のみ強誘電体膜が分極することになる。したがって、印
加電圧と蓄積電荷２の関係は、第４図の様な理想的な関
係に近ずく。よって、強誘電体膜に分極を生じさせたり
、反転されるのにより低電圧ですむことになる。また不
揮発性メモリーのキャパシタとして用いれば、書き込み
電圧をより低く設定してやることも可能であるし、書き
込み時間も短カニくなる。In this way, by forming the second upper electrode 12 on the end of the first upper electrode 10 of the capacitor via the second insulating film 11, the electric field at the electrode end of the capacitor is reduced as shown in FIG. The ferroelectric film will not go around to the outside of the capacitor, and the ferroelectric film will be polarized only in the portion sandwiched between the first upper electrode 10 and the lower electrode 8. Therefore, the relationship between the applied voltage and the accumulated charge 2 approaches the ideal relationship as shown in FIG. Therefore, since polarization is caused or reversed in the ferroelectric film, a low voltage is required. Furthermore, if it is used as a capacitor in a non-volatile memory, the write voltage can be set lower and the write time can be shortened.
また低い電圧での動作が可能となるため、不揮発性メモ
リーの設計マージンもあり、低電圧で動作させても、安
定動作することか可能となる。In addition, since it can operate at low voltages, there is a margin in the design of nonvolatile memory, and it is possible to operate stably even at low voltages.
また、前記第２上部電極１２は、前記第１上部電極１０
端すべてにあることか望ましいか、一部分でもその分の
効果は期待できる。Further, the second upper electrode 12 is connected to the first upper electrode 10.
Whether it's desirable to have it all over the place, even just one part can be expected to have an effect.
また本発明は、強誘電体膜を用いたキヤパンク特性の改
碧であるため、キャパシタ以外の構造に関しては、本実
施例で説明した構造ばかりでなくＣＭＯ３構造、バイポ
ーラ構造などても良いことは言うまでもない。Furthermore, since the present invention is an improvement of the capacitor characteristic using a ferroelectric film, it goes without saying that structures other than the capacitor may be not only the structure explained in this embodiment but also a CMO3 structure, a bipolar structure, etc. stomach.
また本実施例では、下部電極を接地し、第１上部電極に
電圧を印加してキャパシタとする構造であるが、その逆
の構造で、上部７ｆＳ極が接地され、下部電極に電圧を
印加するキャパシタの場合、下部電極端の下に絶縁膜を
介して第２下部電極を形成し、一定電圧を印加しても本
発明と同しである。Furthermore, in this embodiment, the structure is such that the lower electrode is grounded and a voltage is applied to the first upper electrode to form a capacitor, but in the opposite structure, the upper 7fS pole is grounded and a voltage is applied to the lower electrode. In the case of a capacitor, the second lower electrode may be formed under the lower electrode end via an insulating film, and a constant voltage may be applied.
なおかならずしも電極の一方を接地する必要はない。Note that it is not necessarily necessary to ground one of the electrodes.
以上述べてきた様に、本発明の半導体装置によれば、強
誘電体膜を用いたキャパシタの第１上部電極端上に絶縁
膜を介して第２上部電極を形成し、一定電圧を印加する
ことにより、第１上部電極と下部電極とにはさまれた部
分のみ強誘電体膜が分極することになり、低電圧動作、
安定動作が可能なキャパシタを作ることができ、低電圧
動作が可能で、書き込む時間の短かい不揮発性メモリー
を作ることができる。As described above, according to the semiconductor device of the present invention, a second upper electrode is formed on the end of the first upper electrode of a capacitor using a ferroelectric film via an insulating film, and a constant voltage is applied. As a result, the ferroelectric film is polarized only in the portion sandwiched between the first upper electrode and the lower electrode, resulting in low voltage operation.
Capacitors that can operate stably can be created, and nonvolatile memories that can operate at low voltages and have short write times can be created.
第１図は、本発明の半導体装置及び半導体記憶装置の一
実施例を示す主要断面図。
第２図（ａ）〜第２図（ｃ）は、本発明の半導体装置及
び半導体記憶装置の製造方法の一例を工程順に説明する
ための主要断面図。
第３図は、従来の半導体装置及び半導体記憶装置を示す
主要断面図。
第４図は、強誘電体膜を用いたキャパシタの理想的な、
印加電圧と、分極した電荷の関係の図。
第５図は、従来構造の強誘電体膜を用いたキャパシタの
印加電圧と分極した電荷の関係の図。
第６図は、従来の強誘電体膜を用いたキャパシタの電界
のかかり方を示した図。
第７図は、本発明の半導体装置の電界のかかり方を示し
た図。
１・・・シリコン基板
２・・・素子分離用絶縁膜
３・・・第１層間絶縁膜
４・・・ゲー１へ電極
５・・φソース
６・・・ドレイン
７・・・ゲート膜
８・・・下部電極
９・・・強誘電体膜
１０・・・第１上部電極
１１・・・第２層間絶縁膜
１２・・・第２上部電極
１３・・・第３層間絶縁膜
１４・・・ＡＬ膜
１５・・・電界
以上
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴 木 喜三部（ｆｌ！！１名）艶
３ 図FIG. 1 is a main sectional view showing an embodiment of a semiconductor device and a semiconductor memory device of the present invention. FIGS. 2(a) to 2(c) are main cross-sectional views for explaining an example of the method for manufacturing a semiconductor device and a semiconductor memory device of the present invention in the order of steps. FIG. 3 is a main cross-sectional view showing a conventional semiconductor device and semiconductor memory device. Figure 4 shows an ideal capacitor using a ferroelectric film.
A diagram of the relationship between applied voltage and polarized charge. FIG. 5 is a diagram showing the relationship between applied voltage and polarized charge of a capacitor using a ferroelectric film with a conventional structure. FIG. 6 is a diagram showing how an electric field is applied to a capacitor using a conventional ferroelectric film. FIG. 7 is a diagram showing how an electric field is applied to the semiconductor device of the present invention. 1... Silicon substrate 2... Insulating film for element isolation 3... First interlayer insulating film 4... Electrode 5 to gate 1... φ Source 6... Drain 7... Gate film 8... ...Lower electrode 9...Ferroelectric film 10...First upper electrode 11...Second interlayer insulating film 12...Second upper electrode 13...Third interlayer insulating film 14... AL film 15...More than electric field Applicant Seiko Epson Co., Ltd. Agent Patent attorney Kisanbe Suzuki (fl!! 1 person)
3 diagram
Claims (4)
縁膜上に下部電極が形成されており、前記下部電極上に
強誘電体薄膜が形成されており、前記強誘電体薄膜上に
第１上部電極が形成されているキャパシタにおいて、前
記第１上部電極上に第２絶縁膜が形成されており、前記
第１上部電極の端上に前記第２絶縁膜を介して一定電圧
を印加した第２上部電極が形成されていることを特徴と
する半導体装置。(1) An insulating film is formed on a semiconductor substrate, a lower electrode is formed on the insulating film, a ferroelectric thin film is formed on the lower electrode, and a ferroelectric thin film is formed on the ferroelectric thin film. In the capacitor in which a first upper electrode is formed, a second insulating film is formed on the first upper electrode, and a constant voltage is applied to an end of the first upper electrode via the second insulating film. A semiconductor device characterized in that a second upper electrode is formed.
Ｏ＿３、ＰＺＴ（ＰｂＴｉＯ＿３／ＰｂＺｒＯ＿３）、
ＰＬＺＴ（Ｌａ／ＰｂＴｉＯ＿３／ＰｂＺｒＯ＿３）の
うちのいずれかであることを特徴とする請求項１記載の
半導体装置。(2) The main component of the ferroelectric thin film is at least PbTi.
O_3, PZT (PbTiO_3/PbZrO_3),
2. The semiconductor device according to claim 1, wherein the semiconductor device is one of PLZT (La/PbTiO_3/PbZrO_3).
た多結晶シリコン膜もしくはそのポリサイド膜から成る
ことを特徴とする請求項１記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the second upper electrode is made of a polycrystalline silicon film into which impurities are implanted at a high concentration or a polycide film thereof.
して用いたことを特徴とする請求項１記載の半導体装置
。(4) The semiconductor device according to claim 1, wherein the capacitor is used as a capacitor of a nonvolatile memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1129401A JPH02307275A (en) | 1989-05-23 | 1989-05-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1129401A JPH02307275A (en) | 1989-05-23 | 1989-05-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02307275A true JPH02307275A (en) | 1990-12-20 |
Family
ID=15008649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1129401A Pending JPH02307275A (en) | 1989-05-23 | 1989-05-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02307275A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8941974B2 (en) | 2011-09-09 | 2015-01-27 | Xilinx, Inc. | Interdigitated capacitor having digits of varying width |
| US9270247B2 (en) | 2013-11-27 | 2016-02-23 | Xilinx, Inc. | High quality factor inductive and capacitive circuit structure |
| US9524964B2 (en) | 2014-08-14 | 2016-12-20 | Xilinx, Inc. | Capacitor structure in an integrated circuit |
-
1989
- 1989-05-23 JP JP1129401A patent/JPH02307275A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8941974B2 (en) | 2011-09-09 | 2015-01-27 | Xilinx, Inc. | Interdigitated capacitor having digits of varying width |
| US9270247B2 (en) | 2013-11-27 | 2016-02-23 | Xilinx, Inc. | High quality factor inductive and capacitive circuit structure |
| US9524964B2 (en) | 2014-08-14 | 2016-12-20 | Xilinx, Inc. | Capacitor structure in an integrated circuit |
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