JPH0629549A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To provide a field-effect transistor with a structure to increase the times for writing and erasing information. CONSTITUTION:An SiO2 film 47 and Pb(Zr-Ti)O3, namely a thin film 49 of PZT, are formed on a p-type silicon substrate 41 in this order as a gate insulation film 51. A gate electrode (control gate) 53 is provided on the gate insulation film 51. A source region 43 and a drain region 45 are provided at each side of the silicon substrate 41. Therefore, an FET can be maintained to be on or off utilizing the polarization of the PZT thin film 49, thus forming '1' or '0' state needed for a memory cell. Since no current needs to be fed to the gate insulation film, deterioration in the insulation film can be suppressed, thus increasing the times of writing and erasing information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor suitable for use as a cell transistor of a nonvolatile memory.

[0002]

2. Description of the Related Art Field-effect transistors having two structures (hereinafter
Also called "FET". ) Have been proposed (for example, Document I “Physics of Semiconductor Devices”, A Wiley-In
terscience Publication (1981) p. 496-49
7). One is a so-called floating gate type FET, and the other is a MIO (Metal-Insu).
It is an FET called a lator-Oxide-Semiconductor type. The principle of operation of these will be briefly described according to the above-mentioned document I. 7 (A) and 7 (B) are diagrams used for the explanation. FIG. 7 (A) is a sectional view schematically showing the structure of a floating type, and FIG. 7 (B) is MI.
It is sectional drawing which showed the structure of OS type thing roughly.

In the floating gate type FET, a first insulating film 17 as a gate insulating film is formed on a silicon substrate 15 on which a source region 11 and a drain region 13 are formed,
The floating gate 19, the second insulating film 21, and the control gate 23 as a gate electrode were laminated in this order. The floating gate 19 is electrically insulated from the surroundings.

In this FET, the floating gate 1
Whether or not the charge is accumulated in 9, whether the sign of the accumulated charge is positive or negative, or the magnitude of the accumulated charge is
A storage state "1" or "0" is formed. The charge is injected into the floating gate 19 by applying a predetermined voltage between the control gate 23 and the substrate 15 to apply an electric field to the first insulating film 17 and the second insulating film 21, and thereby the control gate 23 to the substrate 15. This can be done by passing an electric current. At this time, the first insulating film 17 and the second insulating film 17
The currents flowing in the insulating film 21 can be expressed as J ₁ (ε ₁ ) and J ₂ (ε ₂ ) by the electric fields applied to these insulating films. Where J ₁ is the current flowing through the first insulating film 17 and J ₂
Is the current flowing through the second insulating film 21, and ε ₁ is the first insulating film 17
, Ε ₂ is an electric field applied to the second insulating film 21. When the current flows in this way, the floating gate 19 has ∫ ₀ ^t [J ₁ (ε ₁ ) −J
_The charge defined by ₂ (ε ₂ )] dt is accumulated. Note that ∫ ₀ ^t means that the integration range is 0 to t. Further, in order to efficiently accumulate this charge, the first insulating film 17
It is preferable that the second insulating film 21 and the second insulating film 21 are made of materials having different electric currents flowing in the same electric field.

In this FET, as another method of injecting charges into the floating gate 19, this F
A method is also known in which ET is turned on and so-called channel hot electrons generated by the drain current are drawn into the floating gate 19.

On the other hand, the MIOS type FET has a silicon substrate 3 on which a source region 31 and a drain region 33 are formed.
5, a gate insulating film 37 formed by stacking a first insulating film 37a and a second insulating film 37b on top of each other and a control gate 39 are provided in this order. However,
The first insulating film 37a is made of a material having a low electron trap density, and the second insulating film 37b is made of a material having a high electron trap density. In this MIOS type FET,
When a voltage is applied between the control gate 39 and the substrate 35 with a predetermined polarity and electrons are injected from the substrate 33 side to the control gate 39 side, the electrons are trapped in the second insulating film 37b. "0" or "1" could be stored depending on whether or not electrons were trapped in the second insulating film 37b.

[0007]

However, in the above-mentioned conventional FET for a memory cell, when writing and erasing information, the floating type has the first insulating film 17 and the MIOS type. As a result, it is necessary to pass a current through each of the first and second insulating films 37a and 37b. A weak electric field causes only a minute current to flow through these insulating films, and therefore information writing and erasing cannot be performed in a practical time. Therefore, a high electric field is applied to avoid this. However, in that case, the breakdown voltage of the insulating film is deteriorated and dielectric breakdown is likely to occur, so that the number of times of writing and erasing information is naturally limited. Therefore, how to increase the number of times of writing and removing information has been an important issue in FETs for memory cells.

The present invention has been made in view of the above circumstances, and therefore an object of the present invention is to provide a field effect transistor having a structure capable of improving the number of times of writing and erasing information as compared with the prior art.

[0009]

In order to achieve this object, according to the present invention, in a field effect transistor having a gate insulating film and a gate electrode on a semiconductor substrate in this order, the gate insulating film is formed on the semiconductor substrate. It is characterized in that it is composed of a laminated body of an insulating film other than the ferroelectric substance and a ferroelectric thin film provided in order from the side.

Here, various ferroelectric materials can be used as the constituent material of the ferroelectric thin film. For example, a perovskite-based material such as Pb (Zr-Ti) O ₃ so-called PZT,
BaTiO ₃ or the like can be used. As the insulating film other than the ferroelectric material, for example, a silicon oxide film, a silicon nitride film, or the like can be used.

[0011]

According to the structure of the present invention, the part of the gate insulating film formed of the insulating film other than the ferroelectric film functions as a conventional gate insulating film, and the part formed of the ferroelectric thin film becomes strong. An FET that functions as a dielectric thin film capacitor is obtained. In this ferroelectric thin film capacitor, electrostatic induction occurs according to the voltage applied to the gate electrode, and exhibits a polarization value corresponding to this voltage. In addition, a voltage corresponding to the above-mentioned polarization value is applied to a portion formed of an insulating film other than the ferroelectric substance. These polarization values and voltages are held by floating the gate electrode. The polarization value of the ferroelectric thin film capacitor can be a polarization value that gives a voltage that can turn on the FET, or the FET can be turned off by devising the voltage applied to the gate electrode. It can be a polarization value that gives a voltage. Such an ON state or OFF state of the FET is the storage state "1" in the memory cell.
Or it can be used as "0". As described above, in the FET of the present invention, the memory states of "0" and "1" are not formed by injecting charges through the insulating film but formed by using electrostatic induction. Therefore, the deterioration of the insulating film due to the current can be prevented, so that the limitation on the number of times of writing information can be eliminated, and the writing time can be expected to be improved. The retention time of memory can be determined only by the characteristics of the ferroelectric thin film.

[0012]

Embodiments of the field effect transistor of the present invention will be described below with reference to the drawings. However,
Each of the drawings used for the description only schematically shows the shape, size and arrangement relationship of each constituent component to the extent that the present invention can be understood.

1. Structure and Description of Manufacturing Method Thereof FIG. 1 is a cross-sectional view schematically showing the structure of a field-effect transistor of an embodiment. Here, an example of an N-channel field effect transistor will be described.

This field effect transistor comprises a p-type silicon substrate 41 as a semiconductor substrate, a source region 43 and a drain region 45, and a SiO ₂ film 47 as an insulating film other than the ferroelectric substance on the silicon substrate 41. And Pb (Zr-Ti) O ₃ as a ferroelectric thin film, so-called P
The gate insulating film 51 is formed by stacking a ZT thin film 49 in this order, and a gate electrode (control gate) 53 is further provided on the gate insulating film 51. Incidentally, reference numeral 55 in FIG. 1 denotes a threshold adjustment ion implantation region.

This FET can be formed by the following procedure, for example. An insulating film (not shown) for element isolation is formed on the p-type silicon substrate 41 by a known method. Next, a SiO ₂ film is formed on the surface of the silicon substrate 41 by, for example, a thermal oxidation method. Next, in order to adjust the threshold value of the field effect transistor, a predetermined impurity is implanted into this silicon substrate 41 by an ion implantation method. Next, S of the silicon substrate 41
A thin film of PZT is formed on the iO ₂ film. The PZT thin film can be formed by a suitable method such as a sputtering method, a CVD method, or a spin coating method using a coating solution. Next, after the thin film is annealed for the purpose of improving the characteristics of the PZT thin film, a thin film for forming a gate electrode is formed on the thin film. This thin film for forming a gate electrode can be made of n ⁺ polysilicon, or n ⁺ polysilicon and W silicide formed thereon, or tungsten (W). Next, a gate electrode forming thin film, a PZT thin film, and a SiO film are formed by ordinary lithography and etching techniques.
Each of the _two films is processed into a gate electrode shape. As a result, the gate electrode 51, the PZT thin film 49 and the SiO ₂ film 47 are formed on the substrate 41. Next, the source region 43
And the gate electrode 5 to form the drain region 45.
3 is used as a mask to implant an n-type impurity into the silicon substrate 41 by an ion implantation method.

2. Explanation of Operating Method Next, in order to deepen the understanding of the present invention, the operation of the case where the nonvolatile memory device is constructed using the field effect transistor of the embodiment will be explained. FIG. 2 is an equivalent circuit diagram of one memory cell portion of the nonvolatile memory device configured by using the FET of FIG. In FIG. 2, 61 is a control gate line, 63 is a word line, and 65 is a bit line.

In the non-volatile memory device, the polarization state of the capacitor C _f differs depending on the combination of the pulse applied to the control gate line 61 and the pulse applied to the bit line 63, and these polarization states will be described in detail later. Depending on the difference, the FET can be turned on or off, and the "0" state or "1" state of the memory cell can be formed in these on state or off state. The storage state of each cell is the word line 63 and the bit line 65.
To scan the conductive state between these lines 63 and 65, that is, F
It can be read by detecting the on / off state of ET.

Hereinafter, the information ("0",
The writing procedure of "1") will be described in detail. Figure 3
5A to 5C are diagrams used for the description. Here, FIG. 3 is an equivalent circuit diagram of a portion of the FET of FIG. 1 which is composed of the capacitor C _o composed of the SiO ₂ film 47 and the capacitor C _f composed of the PZT thin film 49. Moreover, FIG. 4 shows PZT.
Fig. 5 is a characteristic diagram showing the relationship between the voltage applied to the thin film 49 of Fig. 4 and the polarization due to this voltage (hysteresis curve).
Is. In Fig. 4, the values shown in (a) and (b) are PZ.
The electric field applied to the thin film 49 of T corresponds to the holding polarization −P _r or P _r when the electric field is 0. Further, FIG. 5 shows the change in voltage applied to the capacitor C _f (solid line) and the capacitor C ₀ when the voltage applied to the control gate line 61 is changed.
It is a characteristic view which each showed the change (broken line) of the voltage applied to. However, in FIG. 5, the potential difference in the inversion layer formed on the silicon substrate is ignored, and the thickness of the SiO ₂ film 47 is 20 nm and the thickness of the PZT thin film 49 is 250 nm.
It is shown assuming that

Now, the control gate line 61 is ± 1
When the voltage is changed and applied in the range of 0 V, the ferroelectric capacitor is polarized, so that the voltage applied to each of the capacitors C ₀ and C _f changes as shown by the solid line in FIG. 5 for the capacitor C ₀ . , The capacitor C _f is shown in FIG.
It changes as shown by the broken line in the figure. Therefore, the points corresponding to (a) and (b) in FIG. 4 are the points indicated by (1) and (2) for the capacitor C _f in FIG. 5 and (a) and (a) for the capacitor C _0. It becomes the point shown in b). Therefore, in this non-volatile memory device, the voltage between the control gate line 61 and the bit line 65 is 0 →
By changing from 10V → −10V → −2.3V, the voltage applied to the capacitor C _f can be made zero, and the retained polarization in the capacitor C _f can be made −P _f, and the capacitor C ₀ can still be applied. The voltage can be -2.3V. Also,
By changing the same voltage from 0 → −10V → + 10V → 2.7V, the voltage applied to the capacitor C _f can be zero and the holding polarization in the capacitor C _f can be P _f .
Naturally, the voltage applied to the capacitor C ₀ can be 2.7V. At this time, if the control gate line 61 is floated, the voltage applied to the holding polarization and the capacitor C ₀ is held.

By the way, as described above, the holding voltage (2.7 V or -2.3 in the above example) is applied to the SiO ₂ film capacitor C _0.
V voltage) means that the film thickness is 20n
It is equivalent to the holding voltage (voltage of 2.7 V or -2.3 V) being applied to the gate insulating film of the FET having the m gate insulating film. Therefore, if the threshold value Vth of this FET is adjusted in advance in the threshold value adjustment ion implantation so as to satisfy 2.7>Vth> -2.3, FIG.
In the state of (a), this FET is turned off, and in the state of (b), this FET is turned on. Such an off state or an on state of the FET can be read as a conduction state between them by scanning the word line 63 and the bit line 65 (see FIG. 2). Therefore, the storage states "0" and "1" of the memory cell can be formed by utilizing the two polarization states as described above.

When the memory states "0" and "1" are formed by the polarization states of P _r or -P _{r in} the ferroelectric capacitor C _f as described above, no electric field is applied to the ferroelectric thin film capacitor C _f. This is suitable in terms of reliability because the state of "0" or "1" of the memory cell can be obtained in this state.
However, the control gate line 61 has 0 → 10V →
-10V → -2.3V or 0 → -10V → + 10V →
In some cases, it is not practical to apply a voltage of 2.7 V in terms of the circuit configuration. In that case, for example, the following is preferable. FIG. 6 (A)-
(C) is a diagram for explaining the above, in which the voltage applied to the control gate line 61 is V _c , and the bit line 65 is
FIG. 9 is a diagram illustrating pulses applied to the terminals V _c and V _b when “0” is written in the memory cell and when “1” is written in the case where the voltage applied to the memory cell is indicated as V _b .

When a pulse is applied to each of the terminals V _c and V _{b under} the conditions shown in FIG. 6 (B), V _c and V _{b in} FIG. 6 (A) are applied.
Since a combined voltage of these is applied between the terminals, 10 V →
The voltage is applied in the order of 0V → 10V → 0V. Therefore, the capacitor C ₀ formed of the SiO ₂ film is used.
When the voltage related to is considered to be the starting point at point (c) in Fig. 5.
(c) → (f) → (b) → (d) → (f) → (d) and eventually (d)
It becomes the value indicated by. On the other hand, the terminals V _c, figure V _b 6
When the pulse is applied under the condition shown in FIG.
Between V _c and V _b terminals (A) -10V → 0V → -1
Since the voltage is applied in the order of 0V → 0V, S
When the voltage related to the capacitor C ₀ composed of the iO ₂ film is considered as the starting point in FIG. 5, (c) → (e) → (c) →
It changes from (e) to (c) and eventually becomes the value shown in (c).

Therefore, all the memory cells of this non-volatile memory device are first brought to the state of point (c) in FIG. 5 and this state is set to the storage state "0". When writing "1" to the memory cell, a pulse is applied to the V _c and V _b terminals under the conditions shown in FIG. 6B, and the voltage applied to the capacitor C ₀ is shown at point (d) in FIG. State.
Respectively applying the pulse to V _c and V _b terminals conditions that shown in Fig. 6 (C) in the case of the memory cell remains "0". In the case of the driving method described with reference to FIG. 6, FIG.
The potential difference between points (c) and (d) is about 1.5V.
That is, a difference of about 1.5 V can be produced in the voltage applied to the capacitor C ₀ in both the memory states “0” and “1”. Note that this voltage difference can be increased by changing the ferroelectric material and adjusting the film thickness of the thin film portions of the capacitors C _f and C ₀ . In the case of the driving method described with reference to FIG. 6, it is premised that the threshold value Vth of the FET is adjusted so as to satisfy (d)> Vth in FIG. 5> (c) in FIG. Is. More preferably,
It is preferable to set the threshold value Vth to a value that satisfies (d)> Vth in FIG. 5> (c) in FIG. 5 and is a negative value. Vth,
If (d)>Vth> (c) and a negative value, at least the FET is turned on while 10 V is applied to the control gate line in FIGS. 6B and 6C, so one of the write terminals To the bit line 65 (see FIG. 2)
Because it can be

Although the embodiment of the field effect transistor of the present invention has been described above, the present invention is not limited to the above embodiment.

For example, in the above-mentioned embodiment, the ferroelectric thin film is made of PZT thin film, and the insulating film other than the ferroelectric is made of SiO 2.
_Although it is composed of _two films, the same effect as that of the embodiment can be obtained when these materials are replaced with other suitable materials. Further, although the embodiment has been described by taking the example of the N-channel FET, the present invention can of course be applied to the P-channel FET.

[0026]

As is apparent from the above description, according to the field effect transistor of the present invention, since the gate insulating film is composed of the laminated body of the insulating film other than the ferroelectric and the ferroelectric thin film, The FET can be held in the ON state or the OFF state by utilizing the polarization of the ferroelectric thin film. The on-state and the off-state are used as the storage state of the memory cell. These storage states are not formed by injecting charges through the insulating film, but are formed by utilizing electrostatic induction. Therefore, the deterioration of the insulating film due to the current can be prevented, so that the number of times of writing and erasing information can be increased more than before, and the improvement of the writing time can be expected.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining a field effect transistor of an example.

FIG. 2 is an equivalent circuit diagram of a memory cell configured using the field effect transistor of the embodiment.

FIG. 3 is an equivalent circuit diagram of a gate insulating film portion of a field effect transistor of an example.

FIG. 4 is a characteristic diagram (hysteresis curve) showing the relationship between electric field and polarization in the ferroelectric thin film used in the field effect transistor of the example.

FIG. 5 is a diagram for explaining the operation of the memory cell configured using the field effect transistor of the embodiment.

6A to 6C are explanatory views of a driving method when information is written to a memory cell configured by using the field effect transistor of the embodiment.

7A and 7B are diagrams for explaining a conventional field effect transistor.

[Explanation of symbols]

41: Semiconductor substrate (p-type silicon substrate) 43: Source region 45: Drain region 47: Insulating film other than ferroelectric (eg SiO ₂ film) 49: Ferroelectric thin film (eg PZT thin film) 51: Gate insulating film 53: gate electrode (control gate) 55: ion implantation region for threshold adjustment 61: control gate line 63: word line 65: bit line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location G11B 17/00 8110-5D H01L 27/10 421 8728-4M 41/24

Claims (1)

[Claims] 1. A field effect transistor comprising a gate insulating film and a gate electrode in this order on a semiconductor substrate, wherein an insulating film other than a ferroelectric and a ferroelectric thin film are provided in which the gate insulating film is provided in order from the semiconductor substrate side. A field-effect transistor comprising a laminated body of.