JPH02302188A - Standard/high definition television receiver - Google Patents

Abstract

PURPOSE:To simplify the scale of a processing circuit by using a scanning system conversion circuit so as to convert a video signal with 1125 lines of interlace scanning and 16:9 aspect ratio into a video signal with 525 lines of interlace scanning and 16:9 aspect ratio for moving picture processing only. CONSTITUTION:When a standard/high definition signal changeover circuit 117 selects the position of high definition signal (position b), a MUSE system base band signal is inputted to a scanning system conversion circuit 118. The circuit 118 converts an arrival signal with 1125 vertical interlace scanning lines into an RGB color signal with 525 interlace scanning lines and a synchronizing signal in matching therewith and they are supplied to the changeover circuit 117. In this case, the naturality of the picture is not lost even when the horizontal resolution is decreased in matching with the decrease in the vertical resolution resulting from halved vertical scanning lines. Thus, the decode processing of the MUSE system signal is limited to the moving picture processing only to simplify the processing together with the scanning line conversion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is a device capable of receiving two types of television signals, an S-semi television signal and a high-definition television signal, and which The present invention relates to a processing method and circuit for a standard/high definition television receiver having a display having a 7:9 aspect ratio.

[Conventional technology]

In response to demands for higher image quality in television receivers, new high-definition televisions have been developed in recent years.

This high-definition television was proposed to the world by the Japan Broadcasting Corporation (NHK) and has an aspect ratio of 16:1.
9 (or 5:3), the number of scanning lines is 1125, and the current standard television format (aspect ratio 4:3. number of scanning lines 525).
This method is different from the book).

As a transmission method for this high-definition television, a high-definition satellite transmission method (hereinafter, this transmission method will be abbreviated as MUSE) uses a broadcasting satellite to transmit band-compressed signals.
is being developed. Regarding the principles of MUSE, signal format, and general configuration of the receiving device, please refer to [Ninomiya et al., FMUSE
Development of method.

NHK Technical Research Journal, Vol. 39, No. 2; pp18-53,
(1987) J, “Ninomiya et al., “High Visibility Satellite Transmission System-MtJSE-Jl, Journal of the Television Society Vol.
．． 42. l1a5, pp, 468-477, (1988
) shown in J. When such high-definition television broadcasting begins, a receiving device needs to be able to receive two types of signals: a conventional standard television signal and a MUSE signal. In response to these demands, a number of
For example, JP-A-59-70369 and JP-A-59-1048, which describe a conversion system between a high-definition television system and a standard television system, have been devised.
No. 66, JP-A No. 61-206380, No. 61-206381, 63 showing a method for resolving differences in aspect ratio.
No.-26172, No. 63-263783, Japanese Patent Application Laid-open No. 62 (1983) that shares image memory used for processing of both television systems.
-206977, Japanese Patent Application Laid-Open No. 63-6798, for transmitting and receiving signals between a recording/reproducing device and a receiving device in the form of digital signals.
Examples include No. 4.

Furthermore, recently, a signal conversion device has been developed that allows the current receiving device having a 7-spectrum ratio of 4:3 to display an image signal transmitted by the above-mentioned MUSE method. However, in order to fit a 16:9 aspect ratio screen into a 4:3 7-spectrum screen, the left and right sides of the screen must be truncated, or a no-signal period must be added at the top and bottom of one screen. Information on the left and right sides of the screen was missing, and the latter had the disadvantage of significantly reducing vertical resolution to nearly 30%.

[Problem to be solved by the invention]

The above conventional technology requires complex decoding processing to reproduce video signals transmitted using the 1MUSE method, such as switching between video processing and still image processing depending on the presence or absence of movement in the image. The problem was that it was large. Furthermore, the relationship between existing recording and playback devices and television receivers equipped with display devices with an aspect ratio of 16:9 (or 5:3) compatible with high-definition television systems is not considered, and MUSE A new dedicated recording and reproducing device is used for image signals transmitted by this method! (For example, a VTR) had to be provided.

An object of the present invention is to solve the above problems and provide a simple standard/high-definition television receiver with a small circuit scale and equipped with a display device having an aspect ratio of 16:9 (or 5:3). There is a particular thing.

Another object of the present invention is to provide an M
An object of the present invention is to provide a processing method and circuit for a standard/high-definition television receiving device that enables recording and reproduction of video signals transmitted by the USE method.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a device capable of receiving two types of television signals, a standard television signal and a high-definition television signal, which has an aspect ratio of 16:9 (or 5:3). a display device; a scanning method converter for converting the high definition television signal into a standard television signal having an aspect ratio of the high definition television signal and half the vertical resolution; aspect ratio converting means for converting an aspect ratio to match a display device having an aspect ratio; The system is equipped with high-quality signal switching means.

In order to achieve the other object described above, the present invention further includes an encoding means for encoding the output signal of the scanning method converting means into a luminance signal and a color signal of a standard television signal, and an output terminal for outputting the output signal of the encoding means. and an input terminal that can independently input the brightness signal and color signal of the standard television signal.

aspect ratio selection means for supplying a standard television signal having the same aspect ratio as the high-definition television signal input from the input terminal to the standard/high-definition signal switching means without converting the aspect ratio; It is prepared.

[Effect]

The above scanning format conversion circuit converts a video signal with an aspect ratio of 16:9 with 1125 lines of interlaced scanning into a video signal with an aspect ratio of 16=9 with 525 lines of interlaced scanning using only video processing. . In addition, the above aspect ratio conversion circuit compresses the time axis of a video signal having an aspect ratio of 4:3 and adds no-signal areas to the left and right sides, resulting in 16
:Convert to a video signal with an aspect ratio of 9. One of the two converted video signals is selected by a standard/high-definition signal switching means and supplied to a display device having an aspect ratio of 16:9. As a result, images transmitted using high-definition television systems can be transmitted using a simple circuit scale.
It can be reproduced as an image with an aspect ratio of 16:9, and an image transmitted by the standard television system can also be displayed on a part of a display device with an aspect ratio of 16:9.

In addition, since the scanning format conversion circuit converts the video signal transmitted in the high-definition television format into a 525-line interlaced scan video signal, this output signal is encoded by the luminance signal and color of the standard television signal. By encoding the signal into a signal and outputting it to an output terminal, it becomes possible to record it on an existing video recording and reproducing device such as a VTR. In addition, an input terminal is provided for the reproduced video signal, and the aspect ratio selection means does not convert the aspect ratio of the standard television signal to 16:1.
By supplying the image to a display device having an aspect ratio of 9, it can be reproduced. Here, in a separate video signal type VTR that records and reproduces the luminance signal and color signal separately,
The frequency characteristic of the luminance signal has a band of approximately 5 MHz or more. Therefore, even if a high-definition television format video signal is converted to a standard television format video signal and recorded and played back, the frequency of the standard television signal is approximately 3.8MHz.
With the above frequency band, it is possible to achieve sufficient performance for home use.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention. In FIG. 1, 101 is a U-VHF antenna, and 102 is a U-V I-I F that converts a high-frequency standard television signal input from the antenna 101 into a low-frequency video signal.
103 is a BS antenna, 104 is a BS tuner, 105 is a video signal input terminal, 106 is a video signal switching circuit, 107 is a luminance signal (Y) and a color signal (C) of the video signal.
), 108 is an output terminal that outputs the luminance signal and color signal separated by the Y/C separation circuit 107, 109 is an input terminal of a type that separates the luminance signal and chrominance signal, 110 1 is a recording/reproducing device (VTR) that transmits and receives video signals between the output terminal 108 and the input terminal 109; 111 is an input selection switching path for selecting the input of the video signal; Sync signal (HD)
This is a color signal/synchronization reproducing circuit that reproduces vertical synchronization signals (VD) and vertical synchronization signals (VD). These configurations are the same as those of conventional television receivers, and detailed operational explanations will be omitted. Further, 113 is a display device having an aspect ratio of 16:9, 114 is a deflection circuit of the display device 113, and 115 is a case where the video signal reproduced by the color signal/synchronization reproduction circuit 112 has an aspect ratio of 4:3. 116 is an aspect ratio selection circuit that switches according to the aspect ratio of the input video signal; 117 is a switch between a standard television signal and a high-definition television signal; A standard/high-definition signal switching circuit 118 converts the high-definition television signal into 16
119 is an encoder that encodes the luminance signal and chrominance signal of the standard television signal from the output signal of the scanning format conversion circuit 118. 120 is an output terminal for outputting the output signal of the encoder circuit 119, and 121 is a switching control circuit.

Further, FIG. 2 shows an example of one display screen, and FIG. 3 shows an example of scanning method conversion performed by the scanning method converting circuit 118. Hereinafter, the operation of the circuit shown in FIG. 1 will be explained using FIGS. 2 and 3.

First, consider a case where the standard/high-quality signal switching circuit 117 selects the standard signal side (α side) by the switching control circuit 121. Antenna 101 or BS antenna 103
The high-frequency television signal input to the video signal switching circuit 1 passes through the respective tuners 102 and 104.
Selected in 06.

After passing through the Y/C separation circuit 107, the input selection switching circuit 111, and the color signal/synchronization reproduction circuit 112, the T
These become GB color signals and synchronization signals. The ROB color signal and synchronization signal are input to the aspect ratio conversion circuit 115, where the time axis in the horizontal direction is compressed, and no-signal levels are added to the left and right sides. The output signal of the aspect ratio conversion circuit 115 is output from the aspect ratio selection circuit 116. It is supplied to the display device 113 via the standard/high-quality signal switching circuit 117, and the signal shown in FIG.
) to play an image like the one shown. In other words, the image is reproduced on a 4:3 portion of the screen having an aspect ratio of 1620.

Next, consider a case where the standard/high-quality signal switching circuit 117 selects the high-quality signal side (side b).

The MUSE baseband signal reproduced by the BS tuner 104 is input to the scanning method conversion circuit 118. In the scanning method conversion circuit 118, as shown in FIG.
It converts into 25 interlaced scan RGB color signals and matching synchronization signals (HD, VD) and supplies them to the standard/high-quality signal switching circuit 117. At this time, in the same way that the vertical resolution is reduced by approximately halving the number of vertical scanning lines, the naturalness of the image will not be lost even if the horizontal resolution is reduced accordingly. Therefore, decoding processing of MUSE signals can be limited to video processing only, and can be easily performed simultaneously with scanning conversion. The converted video signal input to the standard/high quality signal switching circuit 117 is transferred to the display device 11.
As shown in FIG. 2 (α), the image is reproduced with an aspect ratio of 1629.

Next, consider signal exchange between the recording/reproducing device 110 and the device of the present invention. There is no need to explain the recording and playback of images with an aspect ratio of 4:3; therefore, what we are talking about here is to record and reproduce a high-definition television signal with an aspect ratio of 16:9 as it is. This section describes the circuit configuration for converting standard television signals into standard television signals and recording and reproducing them.

The MUSE baseband signal reproduced by the BS tuner 104 is converted to the standard television signal scanning format by the scanning format conversion circuit 118, so the encoding circuit 1
Just go through 19.

It can be output to the output terminal 120 as a video signal that can be recorded by the recording/reproducing device 110. This output terminal 120
Since the video signal (y, c) output from the is a video signal having an aspect ratio of 16:9, when it is recorded and played back by the recording/playback device 1110 and inputted from the input terminal 109, it is converted by the aspect ratio conversion circuit 115. If you convert the aspect ratio, the image will be reproduced as a shrunk image in the horizontal direction of the screen. In order to prevent this, the aspect ratio selection circuit 1
16 is provided so that the RGB color signals and synchronization signals reproduced from the color signal and synchronization reproduction circuit 112 can be supplied as they are to the standard/high-quality signal switching circuit 117. With this configuration, one video signal input from the input terminal 109 can be displayed all at once in the horizontal direction, as shown in FIG. 2 (α).

As described above, with the configuration shown in FIG. 1, it is possible to provide a standard/high-definition television receiving device with a small circuit scale and a display device having an aspect ratio of 16:9 (or 5:3). Also.

Video signals transmitted using the MUSE method can be recorded and played back using existing recording and playback devices.

Next, the main circuit configuration of the circuit shown in FIG. 1 will be explained in more detail.

FIG. 4 is a diagram showing an example of a more detailed configuration of the aspect ratio conversion circuit 115 shown in FIG. 1, and FIG. 5 is an example of signal waveforms at main parts in FIG.

The operation of the aspect ratio conversion circuit 115 is basically speed conversion, but it also compresses only the video signal in the horizontal direction while keeping the period of the horizontal synchronization signal the same, and inserts a fixed level into the remaining portion. do. Ite in Figure 4, 401,4
02, 403 is an input terminal for ROB color signal, 404 is an input terminal for horizontal synchronization signal (HD), 405, 406.4'0
7 is a line memory for storing each RGB color number m, 408 to 411 are line memories 405, 406°4
07 is an input terminal for inputting the control signal; 412 is a level generation circuit that generates a fixed level for the surplus portion of the luminance signal;
413 is a switching circuit for switching between the output signal of the line memories 405, 406, and 407 and the output signal of the level generation circuit 412; 414 is an input terminal for inputting a control signal for switching the switching circuit 413; and 415 is for aspect ratio conversion. 416, 417, 418 are RGB color signal output terminals, and 419 is a sync signal output terminal.

In addition, a write clock is input to the control signal input terminal 408 of the line memories 405, 406, and 407, a write reset is input to 409, and a read reset is input to 410.
411 are respectively supplied with a read clock.

Line memory 405 and other line memories 406.4
07 are memories with the same configuration that operate with the same control signal, so the line memory 405 will be explained as an example. A memory input video signal as shown in FIG. 5(CL) is input to the input terminal 401, and a write reset (WRES) signal as shown in FIG. 5(b) is input to the input terminal 409.
Based on the signal, the data is written into the line memory 405 using a write clock input from the input terminal 408. A read reset clock having a frequency approximately 1.3 times (corresponding to the difference in aspect ratio) the write clock of the input terminal 408 is supplied to the input terminal 411, and the read reset (RRES) in FIG. 5(C) is performed. Based on the signal, a memory read signal as shown in FIG. 5(d) is output. This output signal is supplied to the a input of the switching circuit, the other b input is supplied with the signal from the level generation circuit 412, and this is inputted from the input terminal 414. By switching using the control signal, a compressed video signal as shown in FIG. 5(1) is obtained at the output terminal 416. The same applies to output terminals 417 and 418. In addition, the input terminal 404
A horizontal synchronization signal is input to , and the synchronization delay circuit 415
The synchronization signal is delayed so as to match the video signal and is output to the output terminal 419. The signals of the output terminals 416 to 419 and the vertical synchronization signal are sent to the display device 113 and the deflection circuit 1.
14, a display screen as shown in FIG. 2(b) can be reproduced.

In FIG. 4, line memories 405, 406, 407
By providing the synchronous delay circuit 415, the memory capacity that normally requires two lines of memory capacity can be realized with one line's worth of memory capacity.

Next, the scanning method conversion circuit 118 will be explained.

FIG. 6 is a diagram showing an example of a more detailed configuration of the scanning method conversion circuit 118 shown in FIG. 1. In Figure 6, 201
202 is the input terminal for the MUSE video signal, and 202 is the A/D.
conversion circuit, 203 is a de-emphasis circuit, 204 is M
This is a USE synchronization/clock regeneration circuit. Further, 205 is a TCI decoding/speed conversion circuit that matches the MUSE system video signal with the standard television system synchronization signal;
6 is MUS with offset sampling and color line sequentialization
An in-field video signal processing circuit that converts the E signal into an RGB color signal through in-field processing; 207 is an RGB color signal;
Color signal output terminal.

208 is an NTSC synchronization/clock regeneration circuit that uses the synchronization signal and clock reproduced by the MUSE synchronization/clock regeneration circuit 204 to reproduce a synchronization signal and clock compatible with NTSC; 209 is an output terminal for a horizontal synchronization signal (HD);
10 is an output terminal for a vertical synchronization signal (VD). Further, in the intra-field video signal processing circuit 206, 21
1 and 212 are field interpolation circuits; 213 is a line-sequential decoding circuit for restoring a line-sequential multiplexed signal of color signals; 214;
and 215 are blanking period gate circuits for the luminance signal and color difference signal, respectively, and 216 is an RGB matrix circuit.

The feature of this circuit configuration is that it tolerates deterioration of the highest image quality of the original MUSE signal to the extent that the image quality of the video signal transmitted by the MUSE method is slightly superior to that of the video signal of the NTSC method. The purpose of this invention is to reproduce an image with an aspect ratio of 16:9 suitable for NT and SC synchronization with a simple configuration.

In FIG. 6, the video signal transmitted by the MUSE method is supplied from the input terminal 201 to the A/D conversion circuit 202, and is reproduced by the 1MUSE synchronization/clock regeneration circuit 204 using the same clock as the 16.2 MHz transmission lock. DeA/
D-converted. One of the video signals converted to a digital signal is supplied to a de-emphasis circuit 203 for de-emphasis processing, and the other is supplied to an MtJSE synchronization/clock regeneration circuit 208 for use in synchronization and clock regeneration. Furthermore, the signal is also supplied to an audio signal processing circuit (not shown), but its explanation will be omitted since it has little bearing on the present invention. Next, the de-emphasis circuit 20
The output signal of No. 3 is the TCI decode/speed conversion circuit 205.
is supplied to the MUSE synchronization/clock recovery circuit 204.
The signal is separated into a luminance signal and a color difference signal corresponding to NTSC synchronization using the synchronization and clock reproduction signals reproduced by the NTSC synchronization and clock reproduction circuit 208. This signal is
It is input to the intra-field video signal processing circuit 206, subjected to interpolation processing, line-sequential decoding processing, etc., and outputted to the output terminal 207 as an RGB color signal.
09 and 210, the synchronization signal regenerated by the NTSC synchronization/clock regeneration circuit is output, and the representation section fi! of FIG. 1 is output.
113 so that images can be played back.

In FIG. 6, TCI decoding/speed conversion circuit 205
and intra-field video signal processing circuit 206 both perform video signal processing within the field, and can greatly simplify the circuitry compared to signal decoding processing of the original MUSE system. This is because the signal decoding process of the original MUSE method requires large-scale signal processing circuits such as a motion detection circuit that uses frame memory, and an interfield interpolation circuit and an interframe interpolation circuit to reproduce higher frequencies. This is because it requires

FIG. 7 shows an example of a more detailed circuit configuration of the TCI decoding/speed conversion circuit 205. Further, FIG. 8 shows main signal waveforms in FIG. 7.

The operation of the TCI decoding/speed conversion circuit shown in Figure 7 is based on the MUSE method, with a buffer memory having a capacity corresponding to approximately one field of the luminance signal and a buffer memory having a capacity corresponding to approximately one field of the color difference signal. The luminance signal and color difference signal of the video signal to be transmitted are intermittently stored and read out simultaneously in NTSC synchronization to obtain an output corresponding to the NTSC video signal.

In FIG. 7, 301 is an input terminal, 302 and 303 are buffer memories for luminance signals, 304 and 305 are buffer memories for color difference signals, 306 to 309 are output terminals, and 304 and 305 are buffer memories for color difference signals;
10 to 313 are AND circuits for generating write clocks for the buffer memories 302 to 305; 314 and 31;
5 is an AND circuit for generating the read clock;
316 is an inverter circuit for inverting two horizontal period pulses (HP) that repeat high and low levels every horizontal period; 317 to 324 are buffer memories 302 to 30;
This is the input terminal for the control signal of No. 5.

The operation will be explained below. A video signal according to the MUSE method as shown in FIG.
, B Y) are stored, respectively. The input terminal 317 has 1, which is a MUSE type transmission lock (CLK).
A 6.2MHz clock signal is input to the input terminal 31.
8 is inputted with a pulse (YEN) indicating the luminance signal position as shown in FIG. A pulse (CEN) indicating the color difference signal position as shown in FIG. 8(b) is input. AND circuit 310~
313 and an inverter circuit 316 combine the signals input to the input terminals 317 to 320 to create a write clock for the buffer memories 302 to 305. Buffer memories 302 and 303 store the luminance signal portion every horizontal scanning period (1/33.75K)lz). Further, buffer memories 304 and 305 similarly store color difference signal portions.

The buffer memory 304 stores the color difference signal R-Y, and the buffer memory 305 stores the color difference signal B-Y. On the other hand, the stored video signal is stored in the buffer memory 30.
2 to 305 at the same time and output terminals 306 to 3.
Supplied on 09. Circuits that create control signals for reading are AND circuits 314 and 315. Input terminal 3
A field pulse (VD) is input to the input terminal 324 once per field in order to initialize the write address and read address of the buffer memories 302 to 305 during the vertical retrace period, and the input terminal 324 is input with a field pulse (VD) as shown in FIG. ) The horizontal scanning period (1/15.7) compatible with NTSC synchronization as shown in
A read gate pulse (YCEN) of 5KHz) is input. Further, a signal with a ratio of 7.0875M1 is inputted to the input terminal 323 as a readout clock (YCK) of the luminance signal, and a signal with a ratio of 1.771875M is inputted to the input terminal 322 as a readout clock (CCK) of the color signal. These clocks are read gate pulses (YCN) and are gated by AND circuits 314 and 315 and supplied to the buffer memories 302 to 305. Therefore, from the buffer memories 302 to 305, the eighth
The readout clock CCK of the 0 color difference signals R-Y and B-Y from which the output signals shown in FIG. It is read out at the rate of 4 pixels of luminance and 1 pixel of color difference. In this way, a video signal transmitted using the MUSE system can be read out in accordance with NTSC synchronization, and TCI decoding and speed conversion can be performed simultaneously. In addition,
The subsequent intra-field video signal processing circuit 206
When using the luminance signal and the color difference signal in a vertically shifted manner, the pulses input to the input terminal 324 may be used independently.

Here, a clock generation circuit for reproducing NTSC signals will be explained. FIG. 9 is a diagram showing an example of the NTSC synchronization/clock recovery circuit 208. In FIG. 9, 501 is an input terminal for a clock signal (CLK);
2 is a frame pulse (PP
603 is an input terminal for the sub-sample phase control signal of the luminance signal, and 504 is the input terminal for the sub-sample phase control signal of the color difference signal. The video signal is reproduced and supplied using a video signal transmitted using the MtJSE method.

Further, 505 is a PLL circuit that generates a clock signal (14,175 MHz) that is 7/8 times the transmission lock frequency of MUSE, 506 is a horizontal counter that divides the frequency by 900, 507 is a vertical counter that divides the frequency by 262, and 508 509 is a horizontal pulse decoder, 510 is a vertical pulse decoder, 511 to 514 are exclusive OR circuits, 515° and 516 are AND circuits, 517 to
526 is an output terminal, and 527 is a subsample phase determining circuit.

In order to reproduce the NTSC system clock from the MtJSE system transmission lock, it is necessary to satisfy the following conditions when determining the frequency.

(1) Ability to reproduce the necessary luminance signal band.

(2) Must be an integral multiple of the horizontal period.

(3) Ability to reproduce interlaced scanning synchronization.

(4) The effective display area transmitted using the MUSE method is NTS
To have an appropriate effective display area even after converting to the C format.

(5) It can be generated by a simple integer ratio relationship with the MUSE transmission lock.

Examples of frequencies that satisfy these conditions (1), (3), and (5) are shown in FIG. There are eight types of frequencies between 12MHz and 15MIIz, and their relationship with transmission lock, horizontal scanning frequency (/H), number of horizontal pixels, number of scanning lines per field, and transmission using the MUSE method. Each pixel indicates the proportion of the image that it occupies in the horizontal scan. As a result, the remaining frequencies that meet conditions (3) and (4) are only 14.175M)h and 13.608MIk.

Comparing these two frequencies, 14.175M)Iz, which has a more appropriate ratio of effective video period, is superior.

Therefore, the reference clock (CK) for NTSC synchronization can be obtained by frequency-dividing the input clock by 7/8, as shown in the PLL circuit 5o°5 of FIG. 9. This clock is output to the output terminal 512, supplied to the intra-field video signal processing circuit 206, and used for various signal processing.

Horizontal counter 5o for NTSC synchronization and clock recovery
The frequency is divided by 6 by 900, and this output is supplied to a horizontal pulse decoding circuit 509 to obtain various horizontal pulses. Further, a vertical counter 507 divides the horizontal pulse by 262, a field counter 508 divides the frequency by 2 to form a frame period counter, and these outputs are sent to the vertical pulse decoding circuit 5.
10 to obtain pulses of various vertical periods.

Further, the output of the horizontal pulse decoding circuit 509 is also supplied to the vertical pulse decoding circuit 510, and is used, for example, to create a vertical synchronization signal. Input terminals 503, 50
A subsample phase control signal is input to 4, which is passed through a subsample phase determination circuit 527 to the Y subsample clock (YSS).

C subsample clocks (CSS) are output to output terminals 519 and 518, respectively. AND circuit 515.516
is used to synthesize the horizontal pulse and the vertical pulse, and the AND 515 is the pulse (YCEN) indicating the display period, and the AND 5
16 creates a pulse (BLK) indicating a retrace period and outputs it to output terminals 524 and 525, respectively. All signals output to output terminals other than those described above are used by the intra-field video signal processing circuit 206.

Next, the characteristics of the intra-field video processing circuit 206 will be briefly explained. This circuit receives the video signal read out in NTSC synchronization from the TCI decoding/speed conversion circuit 205.
This is a circuit that reproduces intra-field interpolated RGB color signals. This is the original MUSE method transmission lock. 16.2
Since signal processing can be performed at 7.0875MHz, which is lower than MHz, it is advantageous in terms of circuit size, heat generation, and power consumption.

In the in-field video signal processing circuit 206, 211
．． 212 is a field interpolation circuit, 213 is a sequential decoding circuit, 214 t' 215 is a blanking and period gate circuit, and 216 is an RGB matrix circuit. TCI
The luminance signal separated by the decoding/speed conversion circuit 205 is supplied to the intra-field interpolation circuit 211 to perform interpolation processing, and is further gated in the blanking period by the blanking period gate circuit 214 to form the RGB matrix circuit. 216. In addition, the color difference signal is processed by the field interpolation circuit 2.
12 performs interpolation processing, the line sequential decoding circuit 213 reproduces the color difference signals R-Y and B-Y, and returns a.
5, the blanking period is gated and the signal is supplied to the RGB matrix circuit 216. RGB matrix circuit 216
creates an RGB color signal from the luminance signal and color difference signal,
It is output to the output terminal 207.

Here, the main circuit configuration of the field interpolation circuit 206 will be explained. FIG. 11 is a diagram showing an example of an intra-field interpolation circuit, which performs interpolation processing on a luminance signal. In FIG. 11, 601 and 602 are video and image signal input terminals, 603 is a sub-sample clock input terminal, and 602 is a video signal input terminal.
04 to 60f3 are 2 line memories, 607 is a switching circuit,
608 to 612 are low pass filters (hereinafter abbreviated as LPF), 613 is an adder circuit, and 614 and 615 are clock input terminals. In relation to the other figures explained so far, the input terminals 601 and 602 have the output terminals 30 and 30 in FIG.
The input terminal 603 receives the video signal 6,307, the input terminal 603 receives the sub-sample clock for the luminance signal from the output terminal 519 in FIG. Figure 9 output terminal 517
clocks are supplied respectively.

The video signals input from input terminals 601 and 602 are 2
The signal is supplied to line memories 604 and 605 and a 2-line memory 606, and is supplied to a switching circuit 607 as a signal for five scanning lines. In the switching circuit 607, the incoming video signal and the zero level are alternately selected according to the sub-sampling clock input from the input terminal 603, and the LPFs 608 to 61
2. LPF608-612 is input terminal 6
1.5, it operates as an interpolation filter. These LPF608
An addition circuit 613 performs addition processing on the output signals of ~612, performs interpolation processing in two-dimensional horizontal and vertical directions, and outputs the result to an output terminal 616.

With this circuit configuration, intra-field interpolation can be performed using five lines of video signals. Also, 2 line me (-IJ 6
04 to 606 require a delay time of 2 lines, or 2x63.5 μS, but a memory capacity of 1
A line, that is, 374 pixels is sufficient. Further, the circuit configuration shown in FIG. 11 can also be applied to the field interpolation circuit 212 for color difference signals.

FIG. 12 is a diagram showing an example of a line +11Jt order decoding circuit 213 and a blanking period gate circuit 215 that perform one color difference signal processing. In FIG. 12, 617 is an input terminal for line-sequentially multiplexed color difference signals, 618 and 619 are 1-line memories, 620 is an adder circuit, 621 is a coefficient circuit, and 62
2 is a reference level generation circuit for the color difference signal R-Y, 623 is a reference level generation circuit for the color difference signal B-Y, 624 is a switching circuit for switching the selection of the color difference signal for each line, and 625 is for switching between the display period and blanking period. switching circuit, 626
．． 627 is an output terminal for a color difference signal, 628 is an input terminal for a pulse corresponding to the output signal (vO) of the least significant bit of the vertical counter 507 in FIG. 9, and 629 is an output terminal 5 in FIG.
This is an input terminal to which 25 retrace period pulses are input. The line-sequential color difference signal input from the input terminal 617 is added to the signal that has passed through the one-line memories 618 and 619 in an adder circuit 620, and the level is reduced to half in a coefficient circuit 621.

The processing is a two-line averaging process, in which the output of the one-line memory 618 is one of the color difference signals, for example, R-Y.
If it is a signal, the output of the coefficient circuit 621 becomes the other color difference signal, for example, a BY signal. Since the obtained color difference signals alternately change line by line, they are alternately selected by a switching circuit 624 and supplied to a switching circuit 625.

The switching circuit 625 switches between the obtained color difference signal and the output signals of the reference level generation circuits 622 and 623 using a blanking period pulse supplied from an input terminal 629, and adds a constant level to the blanking period. .

The reference level generation circuits 622 and 623 are simple circuits that output a zero level if the reference value of the color difference signal, that is, the color difference signal, is considered as a plus or minus signal. By slightly changing these three levels, the color difference reference changes, so it is also possible to change the hue.

Although the standard/high-definition television receiver according to the present invention has been described above in detail using FIGS. 1 to 12, the present invention is not limited to this example.

For example, switching between the standard television system and the high-definition television system was performed using RGB color (No. 1), but ignoring the influence of differences in gamma characteristics, the luminance signal (Y)
The switching may be performed in the state of the color difference signal (R-Y, B-Y).

Furthermore, the switching position of the scanning method conversion circuit is not limited to RGB color signals. As described above, the color difference signal may be used, or the color difference signal may be modulated with a color subcarrier. FIG. 13 shows such an example. FIG. 13 is a diagram showing another embodiment of the present invention, in which only the video signal system is shown, excluding the synchronization system, to simplify the explanation. In FIG.

601 is a scanning method conversion circuit that converts a high-definition television signal into a standard television signal with the same aspect ratio and approximately half the vertical resolution; 602 and 603 are switching circuits that each switch between a luminance signal and a color signal; 604;
is the color signal demodulation circuit.

605 is an aspect ratio conversion circuit that enables a video signal with an aspect ratio of 4:3 to be displayed on a screen with an aspect ratio of 16:9.

606, the video signal switched by the switching circuit 602 is
A video signal assuming an aspect ratio of 16:9 or 4:3
aspect ratio selection circuit that enables selection of aspect ratio depending on whether a video signal assumes an aspect ratio of 60;
7 is R for reproducing RGB color signals from luminance signals and color difference signals.
This is a GB playback circuit. Other components that are the same as those in FIG. 1 are designated by the same reference numerals. In the case of this configuration, the inputs of the standard television system and the high-definition television system are switched in the state of separated luminance signals and color signals, and this operation is performed by switching circuits 602 and 603. Further, the aspect ratio conversion is performed in the state of a luminance signal and a color difference signal. Since the operation shown in FIG. 13 will be easily understood by those skilled in the art from the above explanation, detailed explanation will be omitted. This circuit configuration has the advantage that the memory capacity required for conversion can be smaller than when converting the aspect ratio using RGB color signals. This is because the RGI single color signal requires a wide band for all three types of signals, but when the signals are separated into a luminance signal and a color difference signal, the required frequency band of the color difference signal can be reduced. Further, in the case of this configuration, the scanning method conversion circuit 601 can be sold not only in the case of being built into the device but also in the form of an adapter, which has a great economical effect.

Also, to the aspect ratio conversion circuits 115 and 605.

By combining the TCI decoding speed conversion circuit shown in FIG. 7 and the intra-field interpolation circuit shown in FIG. 11, it is possible to separately have a function of enlarging the image in the vertical direction. In this case, it is possible to realize a new function in which even images with visible blanking at the top and bottom, such as animal cages where movies are projected in conventional broadcasting, can be displayed on a 16:9 display device at the same time.

〔Effect of the invention〕

According to the present invention, it is possible to provide a standard/high-quality receiving device with a small circuit scale and equipped with a display device having an aspect ratio of 16:9 (or 5:3), which is economical.

In addition, the video signal transmitted in the 1MUSE system can be recorded using an existing recording/playback device, and the video signal transmitted in the 1MUSE format can be recorded again at 16:9 (or 5:9).
3) because it can be played back on the display device.

It is very economical for users.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG.
Figure 3 is a schematic diagram for explaining the operation of Figure 1, Figures 4 and 6 are block diagrams showing an example of the main circuit configuration of Figure 1, and Figure 5 is for explaining Figure 4. Signal waveform diagram, No. 7
On the diagram! Pm - A block diagram showing an example of the main circuit configuration in Fig. 6, and Fig. 8 is a block diagram for explaining Fig. 7. Waveform diagram, Figure 9 is a block diagram showing an example of a clock recovery circuit, Figure 1
Figure O is a diagram showing frequency specifications, Figure 11 is a block diagram showing an example of a field interpolation circuit, Figure 12 is a block diagram showing an example of a line sequential decoding circuit and a blanking period gate circuit, and Figure 13 is a block diagram showing an example of a blanking period gate circuit. The figure is a block diagram of another embodiment of the receiving device according to the present invention. 109... Video input terminal, 111... Video switching circuit, 113... Display device, 115... Aspect ratio conversion circuit, 116... Aspect ratio selection circuit, 117...
...Standard/high quality signal switching circuit, 118...Scanning method conversion circuit, 119...Encoding circuit, 120...
Video output terminal.

Claims (1)

[Claims] 1. A device capable of receiving two types of television signals, a standard television signal and a high-definition television signal,
a display device having a wide aspect ratio; a scanning method converter for converting the high definition television signal into a standard television signal having the aspect ratio of the high definition television signal and reduced vertical resolution; aspect ratio converting means for converting the aspect ratio to match the aspect ratio of the display device; and switching means for switching between the output signal of the scanning method converting means and the output signal of the aspect ratio converting means and outputting it to the display device. A standard/high definition television receiving device comprising: 2. The standard/high-definition television receiving apparatus according to claim 1, wherein said scanning method converting means reproduces RGB color signals only by in-field video signal processing. 3. Encoding means for encoding the output signal of the scanning method converting means into a luminance signal and a color signal of a standard television signal, an output terminal for outputting the output signal of the encoding means, and a luminance signal of the standard television signal. and a color signal, and an aspect ratio selection circuit that enables selection of an aspect ratio between a wide aspect ratio and a standard aspect ratio for the signal input from the input means. A standard/high definition television receiving apparatus according to claim 1 or claim 2. 4. The standard/high-definition television set according to claim 1, 2 or 3, wherein the clock signal used in the scanning system conversion means has a frequency that is 7/8 times as high as the clock frequency of the high-definition television transmission system. John receiving device.