JPH0228737A - Buffer storage control system - Google Patents

Abstract

PURPOSE:To reduce a case when an access time is long, to shorten a waiting time by means of the storage of a buffer memory and to improve the processing capacity of a processor by providing the second buffer storage device of a large-scale and high speed, a decision means, or the like. CONSTITUTION:The decision means 3 decides that data of an address which the processor 4 has designated is not stored in first and second buffer storage devices 1 and 2, and a first storage means 10 stores data of an area including the address which a main storage device 5 has designated. A second storage means 20 stores data of the area including the address which the device 5 has designated in the device 2 which has the scale larger than the device 1, and whose speed is faster than the device 5 in parallel to the access action of the device 4 to the device. When necessary data is not stored in the device 1, the device 4 access the instruction from the device 2, and it can execute the instruction. Thus, the case when the access time is long can be reduced, and the waiting time by the storage of the buffer memory is shortened and the processing capacity of the device 4 can be improved.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a buffer storage control method for a buffer memory placed between a processing device and a main recording device, and improves the processing capacity of a CPU by shortening the waiting time due to storage in the buffer memory. In a system having a first buffer storage device between a processing device and a main storage device, the first buffer storage device has a larger capacity than the first buffer storage device and A second memory that is faster than the main memory
a buffer storage device, a means for determining that data at an address specified by the processing device is not stored in both buffer storage devices, and based on the determination by the determining means,
The above 4. a first storage means for storing data in an area including the address of the a device in the first buffer storage device; and based on the judgment of the judgment means, the first buffer 82 of the processing device to the i1 device. a second storage means for storing data in an area including the address of the main storage device in the second storage device in parallel with the access operation;
The processing device is configured to access the first buffer storage device or the second buffer storage device to execute instructions.

[Industrial application field]

The present invention relates to a buffer memory (cache memory) that is placed between a processing device and a main storage device of a computer system, and that increases the speed of the processing device by adjusting the speed difference between the two.
's Ha Sophia T! Regarding control method.

In recent years, with the demand for higher performance of computer systems, various speed-up techniques have been adopted as well as high-speed technologies. The buffer memory method, in which programs and data are transferred in advance to a buffer memory provided between the processing unit and main memory, and the processing unit accesses this memory to speed up processing, is widely used in computer systems. It's been done.

Therefore, there is a need for a storage control method that can efficiently transfer data from the main storage device to the buffer memory to improve system performance.

[Conventional technology]

The conventional Hesso memory control system has a set of small-capacity, high-speed buffer memories, and when a processing unit (hereinafter referred to as CPU) accesses the buffer memory, the command word addressed is present in the buffer memory. If there wasn't,
The CPU is stopped and the data block in the area of the main memory that includes that address is transferred to the buffer memory, and the instruction word at the address that triggered is transferred to the buffer memory and simultaneously passed to the CPU. The instruction word of the address required by C
The PU used to fetch and execute instructions from a buffer memory.

[Problem to be solved by the invention]

As described above, according to the conventional method, if the data at the instruction address specified by CPTJ is not registered in the buffer memory, the instruction is not read from the main memory and a data block of a predetermined length is read from the area containing the instruction address. Since the instruction is read out and stored in the buffer memory, it takes time to read out the instruction, and during the storage period, the CPU is unable to access the next instruction in the buffer memory and has to wait. Therefore, if the block is large, the CPU
In addition, when the block is small, the access time becomes long and the number of times of waiting increases.In either case, there is a problem that the processing capacity of the CPU decreases.

The present invention reduces cases where access times are long, and
An object of the present invention is to provide a buffer storage control method that can shorten the waiting time due to buffer memory storage and improve the processing ability of a CPU.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 4 is a processing device, 5 is a main storage device, and 1 is a first storage device provided between the processing device 4 and the main storage device 5.
2 is a second buffer storage device with a larger capacity than the first storage device 1 and faster than the main storage device 5; 3 is a second buffer storage device in which the data at the address specified by the processing device 4 is stored in both buffers; means for determining that the data is not stored in the storage devices 1 and 2; 10 stores the data in the area including the address in the main storage device 5 in the first buffer storage device 1 based on the determination by the determination device 3; The first storage means 20 stores the data in the area of the main storage device 5 including the Arles in parallel with the access operation of the processing device 4 to the first storage device 1 based on the determination by the determination device 3. Second buffer memory is a second storage means for storing in the jQ device 2.

Therefore, the processing device 4 is configured to access the first buffer storage device 1 or the second buffer storage device 1a 2 to execute instructions.

[Effect]

According to the present invention, the determining means 3 determines that the data at the address specified by the processing device 4 is not stored in the buffer storage devices 1 and 2, and based on the determination, the first storing means 10 stores the data in the main memory. The data in the area including the address of the device 5 is stored in the first buffer storage device 1, and the second storage means 20 mainly stores the data in the area including the address of the processing device 4 in parallel with the access operation to the first buffer storage device 1 of the processing device 4. Start 1. Since the data in the area including the address of the a device 5 is stored in the second buffer storage device 2, the processing device 4 stores the data in the area including the address of the device 5 in the first buffer storage device 2. Instructions can be accessed and executed from the second buffer storage device 2 of capacity.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 2 to 4. The same reference numerals indicate the same objects throughout the figures. Second
In the figure, parts corresponding to FIG. 1 are surrounded by a dashed line.

Since programs and related data are usually configured in units of pages, which are storage units on data media, this embodiment uses a normal small-capacity hasher memory and a hasher memory having a capacity in page units. The main objective is to improve the processing power of the CPU by increasing the probability that instructions accessed by the CPU exist in the hasher memory when used in combination.

FIG. 2 is a block diagram showing an embodiment of the present invention, which includes a CPU 4a that performs processing such as arithmetic operations, a main storage unit that stores programs and data, and a main storage unit that stores programs and data.
5a (hereinafter referred to as MSU) and a block of data from the MSU 5a to the small-capacity, high-speed block memory 1a to speed up the instruction processing of the CPU 4a. The page buffer unit 2A, which forms the main part of the address bus (A00 to A31) and the data bus (D00 to D
31).

Each block memory 1a of the professional sofa part IA is 1
It has 256 memory sections for storing 6-height data, and each memory section stores a 16-height data block from the MSU 5a.

The block table 11 has 256 blocks in the block memory 1a.
The MSU address of the block data registered (stored) in each memory unit is stored corresponding to each memory unit.

Based on the address designation of the CPU 4a, the block control unit 15 inspects the block table 11 to determine whether or not the data is registered in the block memo 1 month a, and if so, reads it out and transfers it to the data bus. Output to. In addition, if it is not registered, and the page memory 2 described later
If it is not registered in block memo January a, control is performed to register it in block memo January a.

The page memory 2a of the page buffer section 2A includes four memory sections each having a storage capacity of 4 words (K=1024 hides) at the same speed as the block memory 1a, and each memory section has 4 words from the MSU 5a. Write down the page data.

The page table 3t stores each 20-bit page number (page address AOO''A19) of the page data registered in the four memory sections of the page memory 2a.

The comparison unit 3c includes four comparison circuits, each of which compares the contents of the corresponding page table 3t and the address buses AOO to A.
19 to determine whether the data accessed by the CPU 4a is registered in the page memory 2a.

If the comparison unit 3c determines that the data is not registered in the page memory 2a, the registration unit 20a reads the data from the MSU 5a and registers it in the page memory 2a. That is,
Based on the determination of the comparison unit 3c, addresses AOO-A19 and A20-A31 are set in the upper and lower parts of the address register 26, and addresses A20-A31 are set in the counter 27 (the count value is reset from the maximum value to 0). (a circular counter that counts up again). The MSU 5a is addressed by the upper part of the address register 26 and the counter 27, and the read data is sequentially stored in the page memory 2a. When the old value of the counter 27 reaches the value of the lower part of the address register 26, the page data is The registration is completed and the upper part of the address register 26 is set in the corresponding memory part of the page table 3t.

The page control unit 25 controls each unit to read the data accessed by the CPU 4a if it has been registered in the page memory 2a, or to register it if it has not been registered.

The address selection unit 7 selects (11) the command address from the CPU U4a, (2) the block data address output by the block control unit 15 at the time of block memo January a registration, or (3)
) The address (the upper part of the address register 26 and the contents of the counter 27) output when registering the page memory 2a is selected and output to the MSU 5a.

Driver/receivers (D/Rs) 8 and 9 specifically conduct C
Access to PU4a block memo 'Jla and MS
This enables simultaneous or parallel operation with data transfer between the tJ5a and the page memory 28.

The present invention will be described in detail with reference to the flowchart of FIG. 3. (1) The CPU 4a outputs an instruction address (assumed α) to the address bus in order to fetch an instruction.

(2) The processor sofa unit IA determines whether the data at the address α has been registered in the block memo 1 month a based on the address on the address bus and the address information in the block table 11, and if it has been registered, reads it out and outputs it to the data bus.

The CPU 4a can process instructions at high speed based on this data.

■When it is determined that it is not registered in the above ■, the page buffer unit 28 determines whether the deck at address α has been registered in the page memory 2a by comparing with the comparison unit 3c, and if it has been registered, it reads it and outputs it to the data bus. do. The CPU 4a can process instructions at high speed based on this data.

(2) When it is determined in (2) that the data is not registered, the deck is read from the MSU 5a and transferred to the CPU 4a, and is also registered in the block memo 1/a and the page memory 2a.

(2) The CPU 4a executes instructions based on the transferred data.

■In parallel with the instruction execution operation of CPU U4a, MSU5a
1 from the area containing address α (normally, since instructions are executed in ascending order of addresses, starting from atlus α)
6-height data is registered in the block memory 1a.

(2) In parallel with the instruction execution operation of the CPU 4a and the operation (2) above, one page's worth of data from the page containing the address α is registered in the hasher memory 2a.

The operation of the embodiment of the present invention will be explained with reference to the timing diagram of FIG. Reads and executes instructions from MSU5a,
In parallel with this operation, the data at addresses 0 to 15 of the MSU 5a are registered in the block memo 'Jla and the page memory 2a.

■Next, when the CPU 4a specifies instruction address 4, the data at addresses 4 to 7 has already been registered in the block memo January a, so the CPU 4a specifies the block memo January a.
Fetch and execute instructions from In parallel with this, the page buffer unit 28 stores addresses 16 to 31 of the MSU 5a.
The data is read out and registered in the page memory 2a.

(2) When the CPU 4a specifies the instruction address 16, since the data after address 16 has already been registered in the page memory 2a, the CPU 4a fetches the instruction from the page memory 2a and executes it.

In this way, the CPU 4a uses the high-speed page memory 2a.
By fetching instructions from , the instructions can be executed at high speed.

〔Effect of the invention〕

As explained above, according to the present invention, data is transferred from the MSLJ 5a to the block memory 1a and the page memory 2a in parallel with the instruction execution operation of the CPU 4a.
A has the effect of realizing high-speed processing by fetching and executing instructions from the high-speed block memory 1a or page memory 2a.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a flowchart of the embodiment of the invention, and Fig. 4 is a timing diagram of the embodiment of the invention. be. In the figure, ① is the first buffer storage device, IA is the block buffer unit, 1a is the block memory, 2 is the second buffer storage device, 2A is the page buffer unit, 2a is the page memory, 3 is the determination means, and 3c is the 4 is a processing unit, 5 is a main memory, 7 is an address selection unit, 8.9 is a driver/receiver 10 is a first storage means, 11 is a block table, 15 is a block control unit, 20 is a second 20a is a registration unit, 25 is a page control unit, 26 is an address register, and 27 is a counter. 3t is a page table, 4a is a CPU. 5a is MSU. (D/R),

Claims (1)

[Claims] A system having a first buffer storage device (1) between a processing device (4) and a main storage device (5), which has a larger capacity than the first buffer storage device (1). , and a second buffer storage device (
2); means (3) for determining that the data at the address specified by the processing device (4) is not stored in both of the buffer storage devices (1, 2); and the determining means (3). Based on the determination, the main storage device (5)
a first storage means (10) for storing data in an area including the address in the first buffer storage device (1); and based on the determination by the determination means (3), the processing device (4) A second buffer storage device (2) that stores data in an area including the address of the main storage device (5) in parallel with the access operation to the first buffer storage device (1). storage means (20), and the processing device (4) accesses the first buffer storage device (1) or the second buffer storage device (2) to execute instructions. Buffer storage control method.