JPS5842546B2 - Store control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for storing data to be stored in a main memory based on a store control method, particularly a store-through method in a data processing system having a buffer memory. The present invention relates to a store control method in which the contents of the buffer memory are stored in a buffer memory, the contents of the buffer memory are read out and stored in the main storage device, and the buffer memory itself is used as a so-called store buffer. It is something.

Generally, in a data processing system, a buffer memory composed of ultra-high-speed memory is provided, and data is transferred from the main memory in units of, for example, 1 block.
In proceeding with the processing, the buffer memory is accessed.

In this type of data processing system, a so-called store-through method is usually adopted when performing store processing on the main memory.

The store-through method is a method in which store processing is performed on data on the buffer memory and store processing is also performed on the main storage device, but in order to efficiently perform the store processing on the main storage device. For example, 8 [byte] x 1 or 8 [byte] is called store buffer.
A register group of 1302 bytes is provided, store data is temporarily held in the register group, and store processing is performed using free time in the main storage device without stagnation of the central processing unit.

However, the conventionally known systems still have the following problems.

That is, 1) In order to prevent the central processing unit from being held up due to store processing for the main storage device, it is desirable to prepare multiple stages of the store buffers;
Store data must be stored in multiple stages, resulting in a huge amount of hardware.

. 2) In the above store processing, there are store processing for the buffer memory and store processing for the main storage device as described above, and the buffer memory and the store buffer exist independently from each other. , it becomes complicated to control each of them.

3) Most of the store processing to the main memory in this type of system involves so-called partial writing, and the busy time in the main memory becomes long.

This has a particularly strong impact on multiprocessor systems.

In other words, the main memory generally adopts 8 [byte] interleaving and has an error correction code for every 8 [bytes], so when writing data of 8 [bytes] or less, the main memory is first used. Eight bytes of data are read from the device, the read data and the write data are merged to generate an error correction code, and then the original write is performed.

This increases the busy time in the main memory.

The present invention aims to solve the above-mentioned problems. (1) The buffer memory itself is used as a so-called store buffer to reduce the amount of hardware, and (2)
) The purpose is to reduce the busy time in the main memory by minimizing the number of partial writes described above.

Therefore, the store control method of the present invention uses a buffer that transfers a predetermined unit of data on the main memory.
Provides memory and uses the buffer as the process progresses.
In a data processing system that accesses the contents of a memory, the data to be stored is stored in the buffer memory during store processing to the main storage device, and the data to be stored is read from the buffer memory and the data is stored in the buffer memory. One or more store buffer control units for storing in the main memory are provided, and the store buffer control unit autonomously reads the contents of the buffer memory and stores them in the main memory. It is characterized by

This will be explained below with reference to the drawings. The figure shows the configuration of an embodiment of the present invention.

In the figure, 1 is a central processing unit (processor), 2 is a main storage device control device that intermediately controls access to the main storage device (not shown), 3 is a buffer memory, and 4 is a tag section of the buffer memory. 5 is the data section in which the address information of the block unit data transferred and held is stored in the data section, which will be described later.
Those in which block units (32 [bytes]) are stored, 6
7 is an address register, 7 is a buffer storage register in which data to be stored in buffer memory 5 is set, 8 is a comparison circuit, and 9 is an instruction word register for reading from buffer memory 3. 10
is an operand word register to which the operand read from buffer memory 3 is set;
11 is a main memory address register in which address information is set when accessing the main memory; 12-0, 12-1, . . . are store buffer control units; 13; 14 is a main memory partial write flag register, 14 is a store byte mark register, and the store byte position is determined based on the contents when a partial write is performed; 15
is a valid bit ■, which is given a logic "l" when there is data to be stored on the buffer memory and the store processing has not yet been performed on the main memory, and 16 is a partial write flag Logic "1" when PF should perform partial writing to main memory.
is given, 17 is store address information, 18
19 is a set number that indicates which set on the buffer memory 3 the data to be stored resides in, and 19 is a byte mark in which byte is to be selected when partial writing is to be performed. 20 is a comparison circuit, 2 indicates whether a store should be performed for
1 represents the main memory store data register.

First, the fetch operation will be explained.

4) Address information given from an instruction control unit (not shown) in the central processing unit is set in the address register 6, and the buffer memory is accessed.

5) At this time, each set of the buffer memory 3 is accessed by the lower bits of the block address of the address information.

The upper bits of the block address read from each tag section 4 are compared with the upper bits of the block address given to the address register 6 by a comparator circuit 8.

6) When the comparison circuit 8 issues a match output, the contents of the data section 5 read from the set position are selected and set in the register 9 or 10.

That is, if it is an instruction, it is set in register 9, and if it is an operand, it is set in register 10, and transferred to the instruction control section.

7) At this time, if the necessary data is not transferred and held on the buffer memory 3, the comparator circuit 8 does not issue a coincidence output.

As a result, the contents of the address register 6 are transferred to the main memory device 2 side via the register 11, and a block fetch is performed to the main memory device (not shown).

8) One block of data fetched from the flock is
The data is set in the buffer storage register 7 and stored on the buffer memory 3, but at the same time, only necessary data is also set in the register 9 or 10 and transferred to the instruction control unit.

Next, the store operation will be explained.

9) Address information to be stored is set in register 6, and data to be stored is set in register 7.

Then, the buffer memory 3 is accessed by this.

10) That is, when the comparator circuit 8 issues a match output, the contents of the register 7 are stored in the corresponding set position.

Then, store/buffer control unit 12-0.12
-1. Register in one of...

In other words, the contents of register 6 are written to store address information 17, the set position stored on buffer memory 3 is written to set number 18, byte mark 19 is written, and valid bit 15 is set to logic "1". Make it.

11) In the above process 9), if the comparison circuit 8 does not issue a match output, in order to minimize the possibility of partial writing in the store process to the main memory,
A block fetch is performed with respect to the main memory, and the data in units of one block is transferred and held on the buffer memory 3, and then the above process 10) is performed.

12) When the access to the buffer memory 3 becomes vacant in the state registered in the store buffer control unit by the above process 10), the store buffer control unit autonomously changes the store address information 18 to the address・Set in register 6.

13) Depending on the contents of address register 6, the buffer
The data stored at the address location of the set location in the memory 3, that is, the store data, is read and set in the main storage store data register 21.

On the other hand, the contents of address register 6 are set in register 11, thereby performing store processing on the main memory.

Note that the store processing for the main memory in this case is a write of the entire 8 [bytes] (ie, not a partial write) regardless of the byte mark.

Of course, as a result of the store processing, the valid bit 15 in the store buffer control section is set to logic "0".

14) When another store process is issued in the state registered in the store buffer control unit according to 10) above, the registration for the other store process is sent to other store buffer control units 12-1, etc. It is done.

Next, buffer invalidation processing will be explained.

15) In the case of a multiprocessor system, when another processor performs a store process to the main memory, the store address information (referred to as invalidation address information) is transferred to each processor, and the store address information (called invalidation address information) is transferred to each processor.
If data of a block whose address information matches the address information exists on the buffer memory 3, its contents need to be invalidated.

16) The above invalidation address information is set in register 6.

At this time, each store buffer control unit 12-0, 12
-1, . . . , the comparison circuit 20 compares the invalidation address information with the store address information 17.

17) When the comparator circuit 20 issues a match output, the partial write flag 16 is set to logic "1" to instruct partial write in the next store process to the main memory device.

18) That is, when store processing is performed on the main memory in this state, the store address information 17 is set in the address register 6, and the data to be stored is read from the buffer memory 3 and set in the register 21. Ru.

At the same time, address information to be accessed is set in the register 11, and store processing is performed on the main memory.

19) At this time, a logic "1" is set in the main memory partial write flag register 13, indicating that partial writing should be performed.

At the same time, byte mark 19 is set in store byte mark register 14 to indicate the byte position to be written when performing the above partial write.

20) As mentioned above, the reason why partial writing is performed in buffer invalidation processing can be considered to be based on the following reasons.

That is, for example, when two processors write into the same block of the main memory device one after the other, there is a risk that the data written earlier may be destroyed by the later write.

Therefore, when writing is performed later, only the data to be stored is correctly written by partial writing as described above.

As described above, according to the present invention, the buffer memory 3 can be used as a store buffer, and when preparing multiple stages of store buffers, it is sufficient to simply increase the number of store buffer control units 12. .

Furthermore, the frequency of partial writing during store processing to the main storage device is significantly reduced.

In addition, in the above process 11), block 2 etching will be performed, but (a) when the above store is performed, there is a very high possibility that the data in the same block will be accessed later, and the block・There is sufficient meaning in performing a fetch, and (b) once a block is fetched and stored, stores that may be performed one after another will almost all become so-called full writes, and the above processing 11), the efficiency is better than when partial writing is performed, so there is no overall performance deterioration.

[Brief explanation of drawings]

The figure shows the configuration of an embodiment of the present invention. In the figure, 1 is a central processing unit, 2 is a main memory controller, 3 is a buffer memory, 4 is a tag section, 5 is a data section, 6 is an address register, 11 is a main memory address register, 12-0 .12-1゜・・・・・・ is the store, respectively.
The buffer control unit 13 is a main memory partial write flag.
register, 14 is a store byte mark register,
21 represents a main memory store data register.

Claims (1)

[Scope of Claims] 1. A data processing system comprising a buffer memory for transferring predetermined units of data on a main storage device and accessing the contents of the buffer memory as processing progresses, 1. Storing data to be stored in the buffer memory during store processing to the main storage device, and reading the data to be stored from the buffer memory and storing it in the main storage device.
A store control method characterized in that one or more store buffer control sections are provided, and the store buffer control section autonomously reads out the contents of the buffer memory and stores them in the main storage device. . 2. A patent claim characterized in that the store buffer control unit is configured to hold at least store address information of the data to be stored, and read out the buffer memory based on the address information. range 1
Store control method described in section. 3 When storing the data to be stored in the buffer memory, if the unit of data including the data to be stored has not been transferred to the buffer memory, the data in the unit is Once transferred from the storage device to the buffer memory, the data to be stored is stored on the buffer memory, and the data to be stored is transferred to the buffer memory.
3. The store control system according to claim 1, wherein the buffer control unit is configured to store data from the buffer memory to the main storage device. 4. The store control method according to any one of claims 1 to 3, wherein the data processing system constitutes a multiprocessor system. 5 The store buffer control unit compares the store address information with buffer invalidation address information given when the other processors constituting the multiprocessor system store in the main storage device. the main memory is configured to perform a partial write process when storing the contents of the buffer memory in the main memory when the address compare means generates a match output; 5. The store control method according to claim 4, wherein: